KR100482339B1 - Driving method of plasma display panel - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel to obtain a high resolution.

A method of driving a plasma display panel of the present invention includes: a first pixel including red, green, and blue subpixels in a triangular form; A second pixel including the first slope of the first pixel in common and including a color subpixel different from the subpixel included in the first slope; A third pixel including a second slope of the first pixel in common, and including a subpixel having a color different from that of the subpixel included in the second slope, in an inverted triangle shape; Is selectively driven for each frame or subfield.

Description

Driving method of plasma display panel {DRIVING METHOD OF PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a plasma display panel, and more particularly, to a method for driving a plasma display panel to obtain a high resolution.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. Such flat panel displays include Liquid Crystal Display (LCD), Field Emission Display (FED), Plasma Display Panel (PDP), and Electro-Luminescence (EL). And display devices.

PDP is a display device using a gas discharge has the advantage that it is easy to manufacture a large panel. As a PDP, a three-electrode AC surface discharge type PDP having three electrodes and driven by an alternating voltage is typical.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP has a first electrode 12Y and a second electrode 12Z formed on the upper substrate 10, and an address formed on the lower substrate 18. An electrode 20X is provided.

The first and second electrodes 12Y and 12Z are made of a transparent material to transmit light supplied from the discharge cells. Bus electrodes 13Y and 13Z formed of a metal material are formed on the rear surfaces of the first electrode 12Y and the second electrode 12Z to be parallel to the first and second electrodes 12Y and 12Z. The bus electrodes 13Y and 13Z are used to supply driving signals to the first and second electrodes 12Y and 12Z having high resistance values.

The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the first electrode 12Y and the second electrode 12Z side by side. Wall charges generated during plasma discharge are accumulated in the upper dielectric layer 14. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge, and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used.

The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in a direction crossing the first electrode 12Y and the second electrode 12Z. The partition wall 24 is formed in parallel with the address electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells.

The phosphor 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. In the discharge space provided between the upper and lower plates 10 and 18 and the partition wall 24, ultraviolet rays are discharged by a discharge gas or discharge composed of an inert gas such as He, Ne, Ar, Kr, Xe, or a combination thereof for gas discharge. Excimer gas that can be generated is injected.

In the conventional PDP, the first electrode 12Y and the second electrode 12Z are installed to face each other in each of the discharge cells as shown in FIG. 2. The reset pulse, the scan pulse and the first sustain pulse are supplied to the first electrode 12Y. The second sustain pulse is supplied to the second electrode 12Y.

The discharge cells are initialized when the reset pulse is supplied to the first electrode 12Y. When scan pulses are supplied to the first electrode 12Y, data pulses synchronized with the scan pulses are supplied to the address electrode 20X. At this time, address discharge occurs in the discharge cells supplied with the scan pulse and the data pulse.

After the address discharge is generated in the discharge cells, the first and second sustain pulses are alternately supplied to the first electrode 12Y and the second electrode 12Z. When the first and second sustain pulses are supplied to the first electrode 12Y and the second electrode 12Z, the sustain discharge occurs in the discharge cells in which the address discharge has occurred. In this sustain discharge, the discharge time is determined according to the gray scale value, so that an image corresponding to the gray scale value is displayed.

On the other hand, the conventional first electrode 12Y and the second electrode 12Z are formed to face each other with a large area in the discharge cells. As described above, when the first electrode 12Y and the second electrode 12Z have a large area, a large amount of power is consumed, thereby lowering the discharge efficiency of the PDP.

In order to overcome this disadvantage, the PDP as shown in FIG. 3 has been proposed.

Referring to FIG. 3, the PDP according to another exemplary embodiment has a delta structure in which discharge cells positioned adjacent to each other up and down form one pixel. In other words, the PDP according to another embodiment of the present invention has one R subpixel and B subpixel positioned on the nth (n is an integer) line and one G subpixel positioned with the n + 1 or n-1 lines. Form a pixel.

The PDP according to another exemplary embodiment of the present invention has the address electrode 30X, the first and second bus electrodes 32Y and 32Z provided in a direction crossing the address electrode 30X, and the first bus electrode ( A first electrode 34Y extending from 32Y and a second electrode 34Z extending from the second bus electrode 32Z are provided.

The first electrode 34Y is alternately extended on the first and second sides of the first bus electrode 32Y. In other words, if the first electrode 34Y intersecting the n-th address electrode 30X is extended on the first side of the first bus electrode 32Y, the first electrode intersects the n + 1th address electrode 30X. The electrode 34Y extends on the second side of the first bus electrode 32Y.

Similarly to the first electrode 34Y, the second electrode 34Z is alternately extended on the first and second sides of the second bus electrode 32Z. At this time, the second electrode 34Z is formed to face the first electrode 34Y. In other words, if the first electrode 34Y crossing the n-th address electrode 30X extends from the first side of the first bus electrode 32Y, the second electrode crossing the n-th address electrode 30X ( 34Z extends on the second side of the second bus electrode 32Z.

In the PDP according to another conventional embodiment, since the first and second electrodes 34Y and 34Z are formed only at the portion where the discharge cells are formed, the total area may be reduced while keeping the length of the electrode sufficiently long. Accordingly, power consumption is reduced as the area of the first and second electrodes 34Y and 34Z is reduced, thereby improving the discharge efficiency.

4 is a diagram illustrating a partition structure used for a PDP according to another conventional embodiment.

Referring to FIG. 4, the partition wall 42 used in the PDP according to another exemplary embodiment includes a plurality of first partition walls 36 and parallel to the bus electrodes 32Y and 32Z, and the first partition wall 36. And a second partition 38 formed parallel to the address electrode 30X. That is, in another embodiment of the present invention, a delta partition wall is used.

The bus electrodes 32Y and 32Z formed of an opaque metal are provided to overlap the first partition 36 so as not to block visible light generated in the discharge cells 40. The first and second electrodes 34Y and 34Z extending from the bus electrodes 32Y and 32Z are installed in the discharge cells 40 formed by the first and second partitions 36 and 38.

5 is a diagram illustrating a pixel center of a PDP according to another exemplary embodiment.

Referring to FIG. 5, the PDP according to another exemplary embodiment selects three subpixels R, G, and B present at a predetermined position in order to select a pixel for displaying an image. That is, the center of the pixel is positioned at the j-2 th address line j-2 and the j + 1 th address line j + 1. In addition, when the centers of the three subpixels R, G and B constituting the pixel are connected to each other, a triangular shape appears, and the center of gravity of the triangle is located between the two subpixels R and B.

6 is a diagram illustrating a frame structure for implementing an image of a conventional PDP.

Referring to FIG. 6, the PDP is time-divisionally driven by dividing one frame into several subfields having different number of emission times in order to implement grayscale of an image. Each subfield is divided into an initialization period for initializing the full screen, an address period for selecting a scan line and selecting a cell in the selected scan line, and a sustain period for implementing gray levels according to the number of discharges. For example, when the image is to be displayed in 256 gray levels, as shown in FIG. 3, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into an initialization period, an address period, and a sustain period. The initialization period and the address period of each subfield are the same for each subfield, while the sustain period and the number of sustain pulses allocated thereto are 2 ⁿ (n = 0,1,2,3,4,5,6) in each subfield. , 7).

When the pixel is increased to increase the resolution of the conventional PDP, the size of the discharge cell is reduced. There is a problem in that the brightness is reduced by the discharge cell having a reduced size, thereby degrading the image quality. In addition, the production of a high-definition structure when manufacturing the PDP will cause difficulties in the manufacturing process.

Accordingly, it is an object of the present invention to provide a method of driving a plasma display panel in which a high resolution can be obtained.

In order to achieve the above object, the present invention provides a method of driving a plasma display panel having a delta three-electrode surface discharge structure, comprising: a first pixel including red, green, and blue subpixels in a triangular form; A second pixel including the first slope of the first pixel in common and including a color subpixel different from the subpixel included in the first slope; A third pixel including a second slope of the first pixel in common, and including a subpixel having a color different from that of the subpixel included in the second slope, in an inverted triangle shape; Is selectively driven for each frame or subfield.

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R, G, and B subpixels constituting the first to third pixels may be adjacent to each other in a horizontal direction.

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The driving method of the plasma display panel includes a first subfield driven to position a first pixel, a second subfield driven to position a second pixel, and a third subfield driven to position a third pixel. Characterized in that.

The plasma display panel may include the first to third subfields in one frame.

The driving method of the plasma display panel includes a first frame including a subfield in which the first pixel is positioned, a second frame including a subfield in which the second pixel is positioned, and the third pixel is positioned. In order to achieve the above object, a driving method of a plasma display panel having a three-electrode surface discharge structure according to the present invention includes red, green, and blue subpixels. A first pixel arranged side by side ; Article consisting of two sub-pixels, and the two sub-pixels and sub-pixels of different colors including a first surface of the first pixels of red, green and blue subpixels of the two subpixels in common are side-by-side arrangement 2 pixels ; Article consisting of two sub-pixels, and the two sub-pixels and sub-pixels of different colors and a second side of the second pixel red, green, and blue subpixels of the two sub-pixels of a common are side-by-side arrangement 3 pixels, wherein the first to third pixels It is characterized in that it is selectively driven for each frame or subfield.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 7 to 9.

7A to 7C are diagrams illustrating centers of first to third pixels of the plasma display panel according to the first embodiment of the present invention, respectively.

Referring to FIG. 7A, in the first pixel of the PDP according to the first embodiment of the present invention, the center of the first pixel is located in the j-2th address line j-2 and the j + 1th address line j + 1. Will be placed.

The R subpixel R11 disposed in the i + 1th scan line i + 1 in the first pixel overlaps the (j-3) th address line j. The B subpixel B11 disposed in the i + 1th scan line i + 1 overlaps the j−th address line j−1. The G subpixel G10 disposed in the i th scan line i overlaps the j th-2 th address line j-2. In addition, the R subpixel R10 disposed in the i th scan line i in the first pixel overlaps the (j-1) th address line j-1. The B subpixel B10 disposed in the i th scan line i overlaps the j + 2th address line j + 2. The G subpixel G11 disposed in the i + 1th scan line i + 1 overlaps the j + 1th address line j + 1.

As such, the R and B subpixels R and B overlap the same scan line in the first pixel, and the G subpixel G overlaps the scan line adjacent to the R and B subpixels R and B. Is formed. That is, when the centers of the R and B subpixels R and B are connected to each other, an equilateral triangle or an inverted triangle is formed at the bottom side, and the vertices of the equilateral triangle or the inverted triangle are positioned at the G subpixel G.

Meanwhile, as shown in FIG. 7B, the second pixel is positioned on the right side of the first pixel. In the second pixel, the center of the second pixel is positioned at the j-1 th address line j-1 and the j + 2 th address line j + 2.

The R subpixel R20 disposed in the i th scan line i in the second pixel overlaps the j th address line (j, j is an integer of 0 or more). The B subpixel B21 disposed on the i + 1th scan line i + 1 overlaps the j−th address line j−1. The G subpixel G20 disposed in the i th scan line i overlaps the j th -th address line j-2. In addition, the R subpixel R21 disposed in the i + 1 th scan line i + 1 in the second pixel overlaps the (j + 3) th address line j + 3. The B subpixel B20 disposed on the i th scan line i overlaps the j + 2th address line j + 2. The G subpixel G21 disposed on the i + 1 th scan line i + 1 overlaps the j th +1 address line j + 1.

As such, in the second pixel, the R and G subpixels R and G overlap with the same scan line, and the B subpixel B overlaps the scan line adjacent to the R and G subpixels R and G. Is formed. That is, when the centers of the R and G subpixels R and G are connected to each other, the bottom and bottom sides of the forward triangle and the inverted triangle are formed, and the vertices of the forward triangle and the inverted triangle are positioned in the B subpixel B.

As such, the center of the second pixel is horizontally moved to the right by one address line from the center of the first pixel.

In addition, as shown in FIG. 7C, the third pixel is positioned on the left side of the first pixel. In the third pixel, the center of the third pixel is positioned at the j-3 address line j-3, the j address line j, and the j + 3 address line j + 3.

The R subpixel R30 disposed in the i th scan line i in the third pixel overlaps the j th address line (j, j is an integer of 0 or more). The B subpixel B31 disposed in the i + 1th scan line i + 1 overlaps the j−th address line j−1. The G subpixel G31 disposed on the i + 1 th scan line i + 1 overlaps the j th +1 address line j + 1. In addition, the R subpixel R31 disposed in the i + 1 th scan line i + 1 in the second pixel overlaps the (j-3) th address line j-3. The B subpixel B30 disposed in the i th scan line i overlaps the j th-4th address line j-4. The G subpixel G30 disposed in the i th scan line i overlaps the j th-2th address line j-2.

As such, the B and G subpixels B and G are formed to overlap the same scan line in the third pixel, and the R subpixel R is a scan adjacent to the scan line of the B and G subpixels B and G. It is formed to overlap with the line. That is, when the centers of the B and G subpixels B and G are connected to each other, the bottom sides of the equilateral triangle or the inverted triangle are formed, and the vertices of the equilateral triangle or the inverted triangle are positioned in the R subpixel R.

As described above, when the third pixel and the first pixel are compared, the center of the third pixel is horizontally moved to the left by one address line from the center of the first pixel.

8 is a plan view illustrating a PDP according to a second embodiment of the present invention.

Referring to FIG. 8, the PDP according to the second embodiment of the present invention has a grid-shaped partition wall structure and forms one pixel with R, G, and B subpixels adjacent in the horizontal direction.

In the first pixel 1P of the PDP having such a structure, the pixel center is positioned at the j-3 th address line j-3, the j th address line j, and the j + 3 th address line j + 3. do. That is, in the first pixel 1P, the pixel is disposed in the G subpixel formed to overlap the j-3 th address line j-3, the j th address line j, and the j + 3 th address line j + 3. The center will be located. R and B subpixels are positioned on both sides of the G subpixel in the same direction as the scan line.

Meanwhile, in the second pixel 2P, the second pixel 2P is disposed in the j-2th address line j-2, the j + 1th address line j + 1, and the j + 4th address line j + 4. The center is located. That is, in the second pixel 2P, the second pixel 2P is overlapped with the j-2th address line j-2, the j + 1th address line j + 1, and the j + 4th address line j + 4 line. The B subpixel is centered at the pixel. G and R subpixels are positioned on both sides of the B subpixel in the same direction as the scan line.

In addition, in the third pixel 3P, the third pixel 3P may be disposed on the j-4th address line j-4, the j-1th address line j-1, and the j + 2th address line j + 2. The center is located. That is, in the third pixel 3P, R formed to overlap with the j-4 th address line j-4, the j-1 th address line j-1, and the j + 2 th address line j + 2. The center of the pixel is positioned at the subpixel. B and G subpixels are positioned on both sides of the R subpixel in the same direction as the scan line.

As described above, when the first pixel 1P and the second pixel 2P are compared, the center of the second pixel 2P is horizontally moved to the right by one address line from the first pixel 1P. When comparing the first pixel 1P and the third pixel 3P, the center of the third pixel 3P is horizontally shifted to the left by one address line in the first pixel 1P.

9 is a diagram illustrating a method of driving a PDP according to the first and second embodiments of the present invention.

Referring to FIG. 9, the PDP performs time division driving by dividing one frame into several subfields having different number of emission times in order to implement gradation of an image. Each subfield is divided into a reset period for initializing the full screen, an address period for selecting a scan line and selecting a cell in the selected scan line, and a sustain period for implementing gray scale according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into a reset period, an address period, and a sustain period. The reset period and the address period of each subfield are the same for each subfield, while the sustain period and the number of sustain pulses allocated thereto are 2 ⁿ (n = 0,1,2,3,4,5,6) in each subfield. , 7).

The subpixels constituting the pixel are formed differently for each frame, so that image display time is formed differently for each frame. That is, the first frame includes a plurality of subfields driven by the first pixel, the second frame includes a plurality of subfields driven by the second pixel, and the third frame includes a plurality of subfields driven by the third pixel. It consists of subfields.

Alternatively, the image display time is formed differently for each subfield by forming different subpixels forming pixels for each subfield. That is, within one frame, the first pixel is driven to the first pixel in the nth subfield, the second pixel in the n + 1th subfield, and the third pixel in the n + 2th subfield.

In this way, pixels selected for each subfield or frame are formed differently. That is, the number of pixels that can be represented is increased by partially overlapping pixels selected for each adjacent subfield or for each adjacent frame.

As described above, according to the driving method of the plasma display panel according to the present invention, the number of pixels that can be represented is increased because the pixels are partially overlapped with pixels driving adjacent subfields or frames when selecting pixels. Accordingly, the resolution can be increased without reducing the area of the pixel.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

FIG. 2 is a plan view illustrating an electrode structure of the plasma display panel shown in FIG. 1. FIG.

3 is a plan view showing an electrode structure of a plasma display panel according to another conventional embodiment.

4 is a diagram illustrating a partition structure applied to the plasma display panel shown in FIG. 3.

FIG. 5 is a diagram illustrating a pixel center of the plasma display panel shown in FIG. 3; FIG.

6 is a diagram illustrating a subfield configuration method of a conventional plasma display panel.

7A to 7C are diagrams showing pixels of the plasma display panel according to the first embodiment of the present invention.

Fig. 8 is a diagram showing pixels of a plasma display panel according to a second embodiment of the present invention.

9 is a view showing a subfield or frame configuration method of a plasma display panel according to the present invention;

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 12Y, 34Y: first electrode

12Z, 34Z: Second electrode 13Y, 13Z, 32Y, 32Z: Bus electrode

14,22 dielectric layer 16: protective film

18: lower substrate 20X, 30X: address electrode

24, 36, 38, 42: partition 26: phosphor layer

40: discharge cell

Claims (8)

Delta 3-electrode Cotton discharge  Structure plasma  display Panel  In the driving method, Red, green and blue sub Pixels  First to include in the form of a triangle Pixel ; The first Pixel  A sub included in the first inclined plane in common With pixel  Different color serve Pixels Inverted triangle  A second comprising in form Pixel ; A subpixel including the second slope of the first pixel in common and included in the second slope  Serve of different colors Pixels Inverted triangle  Third to include in form Pixels  Equipped, The first to third Pixels are Per frame  Or selectively driven for each subfield. plasma  display Panel  Driving method. delete The method of claim 1, The R, G, and B subpixels forming the first to third pixels are adjacent to each other in a horizontal direction. delete The method of claim 1, A first subfield for selectively driving the first pixel; A second subfield for selectively driving the second pixel; And a third subfield for selectively driving the third pixel. The method of claim 5, wherein And the plasma display panel includes the first to third subfields in one frame. The method of claim 1, A first frame including a subfield for selectively driving the first pixel; A second frame including a subfield for selectively driving the second pixel; And a third frame including subfields for selectively driving the third pixel. 3-electrode Cotton discharge  Structure plasma  display Panel  In the driving method, Red, green and blue sub Pixel  First side by side Pixel ; The first Pixel  Red, green and blue sub pixel  Two sub Pixel  Two subs with common first face Pixel , Those two subs Pixel  Serve of different colors Pixel  A second side by side Pixel ; The second Pixel  Red, green and blue sub pixel  Two sub Pixel  Two subs with common second side Pixel , Those two subs Pixel  Serve of different colors Pixel  A third, arranged side by side Pixels  Equipped, The first to third Pixels are Per frame  Or selectively driven for each subfield. plasma  display Panel  Driving method.