KR100481332B1 - An audio a/d convertor using frequency modulation - Google Patents

Abstract

According to an exemplary embodiment, the voltage or current-controlled oscillator is frequency controlled by a signal from the microphone (ie, voltage or current). The frequency modulated signal is applied to a direct digital discriminator that provides a digital representation of the instantaneous frequency at the desired voice sampling rate. A digital discriminator is formed, for example, by applying an oscillator signal along with a reference frequency to a direct phase digitalization circuit and calculating the instantaneous phase sequence of the oscillator for the reference frequency. The phase sequence is then applied to a digital phase locked loop (otherwise numerically differential) to generate a sequence of binary words representing a speech waveform since it represents an instantaneous frequency. Since low-level speech waveforms do not actually enter integrated circuits except for high-level frequency-modulated carriers, the technique is immune to noise generated by high-speed random logic circuits such as DSPs operating on microprocessors and chips. Do not.

Description

Audio A / D converter using frequency modulation {AN AUDIO A / D CONVERTOR USING FREQUENCY MODULATION}

The present invention generally relates to the integration of various electronic components on a single silicon chip, thereby reducing the cost of electronic systems including voice processing, such as telephones and cell phones. In particular, the present invention relates to an analog-to-digital converter that minimizes the number of analog components used and is relatively insensitive to noise pick-up from digital circuits operated on the same chip.

For example, many forms of prior art using known techniques such as Successive Approximation, Delta-Sigma Modulation, and Continuously Variable Slope Delta Modulation (CVSD). There is an analog-to-digital converter. The purpose of these devices is to provide a number of streams representing samples of instantaneous signal values at a desired sample rate. The desired sampling rate is usually higher than the minimum Nyquist rate, which is twice the maximum frequency of the analog signal represented numerically. A disadvantage of these prior art relates to the very small signal level output from the microphone, which in turn makes the connection between the microphone and the analog-digital converter sensitive to noise pickup.

Summary of the Invention

According to an exemplary embodiment, the variable frequency oscillator is frequency controlled by variable electrical parameters in the microphone, typically variable capacitance. The frequency modulated signal is applied to a direct digital discriminator that provides a digital representation of the instantaneous frequency at the desired voice sampling rate. A digital discriminator is formed, for example, by applying an oscillator signal directly to the phase digitization circuit at a reference frequency and calculating the instantaneous phase sequence of the oscillator related to the reference frequency. The phase sequence then represents an instantaneous frequency and is then applied to a digital phase locked loop (or otherwise differentially differentiated) to generate a sequence of binary words representing the speech waveform. Since low-level speech waveforms do not enter the integrated circuit except in the case of substantially high-level frequency-modulated carriers, the technique is sensitive to noise generated by high-speed random logic circuits such as microprocessors and DSPs operating on the chip. Practically unaffected.

According to another exemplary embodiment of the present invention, a microphone circuit can be provided which is less sensitive to noise than conventional microphone circuits and based on variable electrical parameters of voltage or current. For example, conventional FET preamplifiers may be omitted in accordance with the present invention so that noise typically generated by bias supply is avoided.

1 is a block diagram of a digital speech processing circuit in accordance with an exemplary embodiment of the present invention.

FIG. 2 is a graph showing exemplary speech frequency spectrum prior to downsampling for three exemplary quantization accuracy.

3 and 4 are graphs showing quantized signal and noise spectra during a quiet period.

5 and 6 are graphs showing quantized signal and noise spectra using a 1 KHz sine wave test.

7 is a graph showing harmonic distortion for a silent period signal.

8 is a graph illustrating the reduction of harmonic distortion by the presentation of a planned frequency offset in accordance with the present invention.

9-11 are graphs showing that harmonic distortion is reduced when the signal level is reduced when a deliberate frequency offset is applied in accordance with the present invention.

12 is a graph showing the spectrum of a test signal, such as noise, with a planned frequency offset.

13 is a graph showing a reduced signal level version of the test signal of FIG. 12.

14 and 15 are graphs showing residual quantization noise after subtracting a desired signal from the frequency spectrum.

16 and 17 are graphs showing speech interruption in a signal using 6-bit quantization and residual noise, respectively, for a signal with frequency offset applied;

18 is a block diagram of a digital phase locked loop that may be used in a system in accordance with the present invention.

FIG. 19 is a graph showing the residual noise spectrum for an exemplary digital phase locked loop including the frequency offset presented in accordance with the present invention. FIG.

20 is a graph showing the residual noise spectrum for a phase locked loop when no frequency offset is provided.

21-23 are graphs illustrating various frequency transfer characteristics of an exemplary secondary phase locked loop.

24 illustrates exemplary dynamic ranging in a typical wireless communication application.

25 is a block diagram illustrating a phase locked loop that can be used as a demodulator in accordance with the present invention.

FIG. 26 is a block diagram illustrating modification of the exemplary embodiment of FIG. 25 including frequency adjusting means.

FIG. 27 illustrates word length for various digital quantities used in the exemplary embodiment of FIG. 26. FIG.

FIG. 28A shows a conventional microphone circuit arrangement; FIG.

FIG. 28B illustrates an electret microphone controlling an oscillator in accordance with an exemplary embodiment of the present invention. FIG.

FIG. 29 illustrates a source coupled multivibrator that may be used as a current controlled oscillator in accordance with an exemplary embodiment of the present invention. FIG.

30 is a block diagram illustrating a digital mixer in accordance with an exemplary embodiment of the present invention.

US Patent No. incorporated herein by reference 5,084,669 describes a technique for using digital logic to determine instantaneous phase and frequency or frequency-modulated radio signals with a series of numerical values at a desired sample rate. United States Patent No. assigned to Holmqvist, which is also incorporated herein by reference. 5,220,275 describes a method for determining the instantaneous phase of a signal with a numerical value calculated at a desired sample rate. These digital phase / frequency determination circuits are described in these patents to demodulate modulated radio signals received by a wireless receiver. The present invention uses this kind of circuit in a new application to digitalize a speech signal by first using a digital discriminator to convert the speech signal into a frequency modulated carrier and then convert the modulated carrier signal into a numerical sample sequence representing the speech waveform. do.

A first exemplary embodiment of the invention is described using FIG. 1. Here, the active microphone 20 comprises a variable capacitance microphone element 10 which forms part of the LC resonance circuit 11 of the oscillator 12. The oscillator output signal is for example at a frequency of 1 MHz and is preferably output at the active microphone 20 as a balanced signal from the buffer amplifier 13. Thereby, the use of balanced signal outputs in which antiphase signals travel in parallel conductor tracks on printed circuit boards minimizes coupling to other nearby circuits, reducing the risk of interference and reducing interference susceptibility. The acoustic voice waveform is interpreted as the vibration plate movement of the microphone element 10, that is, the capacitance change and the oscillator frequency change. So, the speech waveform modulates the oscillator signal, and the F.M. The signal is fed directly to the phase digitizer 30 as described in the patent mentioned above. Phase digitizer 30 is F.M. Both positive or negative transitions of the carrier signal are compared with the reference clock, and this prior generation time is quantized, for example, with an accuracy of half the clock period. The numerical result from the circuit 30 is a 6-bit binary value representing the instantaneous phase at an output sample rate, for example, a coefficient larger than the final desired speech sampling rate of 8 KHz. For example, the sampling rate may be 256 K samples / second, which is 32 times larger. In any case, the sampling rate should be high enough so that the instantaneous phase deviation of the carrier frequency from the nominal phase cannot vary by more than +/- 180 degrees (ie half cycle) during one sample period. This means that the sample period should be at least twice the maximum frequency deviation from the nominal carrier frequency given by the voice-induced diaphragm vibration. This is preferable because a phase value of 180 degrees or more cannot be distinguished from a negative phase value of 180 or less. Advantageously, the phase change over one sample period should be less than or equal to +/- 90 degrees to provide a maximum margin to distinguish the positive phase from the negative phase change and to avoid ambiguous areas around +/- 180 degrees. .

The phase samples from the phase digitizer 30 are supplied to the numerical differentiator 31 and calculate the difference modulo 2Pi between successive samples. Due to the preemption relationship between the sample rate and the maximum frequency deviation described above, the phase difference lies within the range +/- 90 degrees. Thus, the difference nominally has the same word length as the original phase sample. For example, if the phase is calculated with 6-bit accuracy, positive integers 0 to 31 represent angles greater than 0 and less than 180 degrees, and negative integers represent angles less than 0 and greater than -180 degrees. Therefore, the nominal phase difference between +/- 90 degrees can be represented by an integer between 16 and +16, allowing space for a sufficient and larger peak value within a 6-bit word length.

For example, the 6-bit phase difference at 256K samples / s is downsampled to 8K samples / s by a digital lowpass filter. The first step of such a lowpass filter involves calculating the sum of 32 consecutive samples, for example, through a 32-sample wide moving window. In this example this results in an amount of 11-bits.

The second step of the filtering process may include accumulating together 32 consecutive 11-bit moving averages once for a 32-sample block to obtain 16-bit values at a sample rate of 8K samples / s as desired. Can be. United States Patent Application Serial No., filed September 14, 1993, by Paul W. Dent, which is incorporated herein by reference. As described in 08 / 120,426, this downsampling reduces the frequency response at the highest voice frequency of 3.4 KHz, which can be compensated for by resetting the accumulator before each new accumulation on some of the negative values of the previous values. .

Assuming that the quantization noise in the phase difference is uniformly distributed between the Nyquist frequency of 0 and 128 KHz, the downsampling filter reduces the quantization noise power by a 32: 1 bandwidth reduction factor equal to 2.5 bits of precision. The precision of this method is only 8.5 bits, not the 16-bit length of the calculated value. However, the quantization noise is uniform in the phase domain, but because the phase is differentiated to perform frequency demodulation, the spectrum is expected to rise to 6 dB per octave of frequency, with less noise at lower frequencies than higher frequencies. . In this way, most of the quantization noise power is expected to be dense at half the sampling rate, the amount of which is significantly reduced in the 0-3.4KHz audio band.

2 shows the spectrum before downsampling of the phase difference. The desired signal modulation is a white noise signal with an extended spectrum from 200Hz to 3.3KHz representing speech, which produces an RMS frequency deviation of 1/3 of the 50KHz peak deviation, chosen for less than 1/4 of the 240KHz sample rate for the reasons mentioned above. Is adjusted to This ensures that the 3-sigma limit of the desired signal, such as noise, remains within the peak deviation. The spectrum of FIG. 2 shows quantization noise other than 3.4 KHz to be removed by the downsampling filter, with varying phase quantization accuracy in bits. Thus, it is confirmed that the quantization noise spectrum tends to fall toward zero frequency as predicted above. However, quantization noise within 3.4 KHz cannot be shown when obscured by the signal spectrum in FIG. Another figure, which will be discussed later, shows quantization noise in the audio band minus the desired signal. 2 shows the band edge quantization noise density, where the signal spectral density is given in the following amounts.

Phase quantization 4-bit 8-bit 12-bit Band Edge N / S Density -35 dB -60 dB -85 dB

These values follow the 6 dB per bit improvement in quantization accuracy, or the expected rule of 24 dB per 4-bit.

Assuming that in-band noise drops from 6 dB per octave towards zero frequency, the total noise power can be calculated by an integration that provides an overall signal-to-noise ratio that is three times better (4.77 dB) than the figure above. have. Thus, the in-band quantization noise can be expressed in Hz RMS as a clear caught frequency deviation as follows.

Phase quantization 4-bit 6-bit 8-bit 10-bit 12-bit In-band Noise Deviation (Hz RMS) 167 Hz 43 Hz 10 Hz 2.6 Hz 0.53 Hz

Speech volume is generally thought to be more related to noise at speech interruption than noise at speech peak. 3 and 4 show the quantized signal + noise spectrum with speech modulation reduced to 20 and 40 dB, respectively. In this figure it is noted that as an advantageous trend, the quantization noise at the 3.4 KHz band edge is reduced with reduced signal power, but the spectrum tends to be flat as not so advantageous. The greater proportion of noise in the lower frequency portion of the spectrum is seen to be caused by the signal itself driving the phase through the quantization level. At lower signal amplitudes, the quantization level crosses at lower rates, so the quantization noise spectrum has more energy at lower frequencies. In a sine wave signal, since level crossing occurs at regularly defined points in the signal waveform, quantization noise appears as harmonics of the signal frequency. This is confirmed by FIGS. 5 and 6 which show exemplary signal + quantization noise spectra using 1 KHz sine wave test signals in 8- and 4-bit phase quantization, respectively. Since the quantization levels are arranged symmetrically in the phase plane, odd harmonics are superior, and the third harmonic is around 66 dB below the fundamental in 8-bit quantization, and around 40 dB in 4-bit quantization. However, the relative distortion of the third harmonic wave is increased as the signal is reduced as shown in Fig. 7, where the third harmonic wave is raised to only 14 dB under the signal level reduced by 20 dB.

This effect can be mitigated by using a deliberate carrier frequency offset such that the signal phase rotates quickly through all quantization levels even in the absence of speech modulation. For example, FIG. 8 shows an exemplary spectrum where a 20,625 Hz carrier frequency offset is used. This particular carrier frequency value is not critical and was chosen to facilitate the calculation of the spectrum by providing a 4096 repeated phase waveform with a finite number of samples at 240 K samples / sec. Thus, those skilled in the art will appreciate that any carrier frequency may be applied, but the offset should be chosen high enough so that the quantization step change of the system occurs at frequencies above the maximum audio frequency. It can be seen that the third harmonic in the 4-bit phase quantization has dropped from -40 dB to almost 50 dB of the fundamental wave. As shown in Fig. 9, when the signal deviation is reduced, the harmonic distortion is not increased but is actually reduced, and is still within the -40 dB to -50 dB region with the 20 dB reduced signal. FIG. 10 shows that even with a 40 dB reduced signal, the product of noise and distortion is still below 25 dB. FIG. 11 shows that odd harmonics appear to be equal to the signal when the signal power is reduced by 60 dB. 5 to 11 all confirm that the quantization noise spectrum falls toward zero frequency.

12 and 13 illustrate a noise like test signal using a deliberate frequency offset. In FIG. 12 the full test signal deviation is used to provide a quantization noise spectrum of 4-bit phase quantization similar to the 4-bit quantization spectrum of FIG. 2 without frequency offset. However, FIG. 13 shows that when the signal is reduced by 40 dB, the noise spectrum now drops about 15 dB, in contrast to FIG. 4, which did not use the frequency offset according to the present invention. 14 and 15 show in-band quantization noise for the entire signal and a 40 dB reduced signal, respectively, subtracting the desired signal so as not to mask residual noise. The noise spectrum is found to be 10-15 dB lower and fall towards zero frequency during -40 dB voice interruption (FIG. 15) compared to the overall voice activity (FIG. 14).

16 and 17 show the signal + noise and residual noise spectra during -40 dB speech interruption using 6-bit phase quantization and deliberate frequency offset, respectively, according to an exemplary embodiment of the present invention. Residual noise, expressed as an in-band RMS frequency deviation, is similar to that obtained in FIG. 17 approximately 8 Hz, ie, 8-bit quantization without frequency offset (see FIGS. 2 and 3).

For A to D performance, the exemplary technique according to the invention using 6-bit phase quantization is 100000 units of dynamic range (+/- 50 KHz deviation or more), i.e. full dynamic range, with quantization noise of 10 units RMS. Obtain -80dB for. Conventional A / D converters require 11.5 bits of accuracy to achieve the same performance, or 9-bits to achieve the same performance using the same oversampling coefficients.

Another method for converting phase samples into frequency samples in accordance with the present invention is described in US Pat. As described in 5,084,669, it is to use a digital phase-locked loop. 18 illustrates an exemplary form of digital PLL applied to the present invention. Here, the streams of the digitized phase samples PHI1, PHI2, PHI3, ..., PHIi ... are input to the phase comparator 100. This comparator subtracts the expected phase THETAi from the actual phase PHII to find the error Ei between the actual phase and the estimated phase. The phase estimate THETAi uses the delay register 105 to delay the previous update delay value delayed through the delay register 101 to predict the new phase from the spherical phase by linear extrapolation using frequency as the slope. Calculated by combining with the frequency estimate. The frequency and phase are then both updated by adding some BETA of the satellite error to the previous frequency estimate and adding some ALPHA of the phase error to the previous phase estimate.

ALPHA and BETA determine the characteristics of the secondary digital phase locked loop thus configured. For example, it is also possible to construct higher order loops using estimates of the rate of change of frequency that are updated using the coefficient GAMMA.

19 shows the residual noise spectrum of a frequency estimate formed of an exemplary digital PLL with coefficients ALPHA = 0.5, BETA = 1/32. ALPHA and BETA can be chosen to be the inverse power of the two so that multiplication can be done with a simple shift, for example. By comparing the noise spectrum of FIG. 19 with FIG. 17, it can be seen that there is little difference in the range when the loop does not attenuate the component in the audio range of 0 to 3.4KHz. However, the decrease in quantization noise density at +/- 15 KHz is evident when the loop is partially attenuated at these frequencies.

To illustrate that the use of a deliberate frequency offset is valuable even in a digital PLL FM demodulator, FIG. 20 shows residual quantization noise from a PLL FM demodulator with the frequency offset removed. Since the quantization noise within 0-3.4KHz is greater than 10dB, it can be seen that the benefit of frequency offset is independent of the type of FM demodulator used.

21, 22, and 23 are provided to illustrate how the coefficients ALPHA and BETA can be selected. 21-23 provide loop attenuation from frequency input to frequency output as a function of modulation frequency for ALPHA values of 1, 0.5, and 0.25 and BETA values of 1 to 1/64. The loop attenuation feature should be practically flat from 0 to 3.4KHz, and excessive peaks, signals of upcoming instability, should not appear at any frequency. Another function of this loop is to track the maximum rate of change of frequency. This happens when voice modulation is large. In simulation, loops with ALPHA = 1/2, BETA = 1/32 track voice modulation when the RMS deviation is 16.67 KHz, but tracking deviation of 33.33 KHz RMS fails. 22, it can be seen that the frequency response is approximately 3 dB below 3.4 KHz when BETA = 1/32. Increasing the value of BETA to 1/16 when ALPHA = 0.5 provided a nearly flat loop at 3.4 KHz, which was found to track 33.33 KHz RMS with these parameters. From Figure 21, the values ALPHA = 0.25, BETA = 1/16 are also proposed, and the loop also tracks the 33.333 KHz deviation with these parameters. Audio SNR with 6-bit phase quantization and 20625 Hz frequency offset is calculated to yield the following diagram:

RMS deviation Audio SNR Equal noise deviation 33.33KHz 63.8 dB 22 Hz 16.67KHz 56.5 dB 25 Hz RMS 1.667KHz 46.6 dB 8.8 Hz RMS 167 Hz 25.2 dB 9 Hz RMS

The results show that the voice digitalization system according to the present invention using frequency modulation includes some of the desirable features of the companding method, whereby the quantization noise for small signals is smaller than the quantization noise for large signals. Thus, during silence periods or speech interruption, quantization noise is reduced, improving the quality of the main audio. The above results can be compared against the typical dynamic range specification for wireless telephone applications. This dynamic ranging is shown in FIG.

Here, the level 'A' represents the RMS level of the general voice. The dynamic range is designed to accommodate what the speaker says at an average level 'B' that is 15dB higher than the normal voice level 'A'. In addition, the negative peak of the largest speaker is accepted without distortion. This is usually taken to be intended in the kind of designation where the 3-sigma limit of the hypothesized Gaussian amplitude probability distribution is acceptable, or where a +10 dB crest factor is used. The result at that level is indicated by 'C' in FIG.

An exemplary system also satisfies the minimum signal-to-noise ratio for the quietest speakers. The quietest speaker may be characterized by uttering at a level 'D', 15 dB below the normal speaker. However, the signal-to-noise ratio is a sinusoidal test tone with a peak level equal to the maximum speech level, that is, defined at the peak level 'E', not the RMS level 'D' of the quietest speaker. When defined in this way, the Test Tone to Noise Ratio (TTNR) is 50dB. Moreover, noise is defined as the residual noise when the test tone signal is switched off, that is, the noise during the silent period. Given that the RMS value of the desired sine wave test tone energy is 3 dB below its peak value, this means that the noise floor is at 53 dB below level 'E'. Comparing the noise floor level 'F' with the largest voice peak level 'C', the total dynamic range required for a typical wireless communication application is proposed to be 83dB.

The noise floor should be 83dB below this at 8.4Hz RMS, considering that the maximum deviation that can be handled using the 240KHz phase sampling rate without exceeding the phase shift of Pi between samples is within level C (ie 120KHz). The exemplary signal-to-noise simulation above shows a noise layer of 9 Hz with 6-bit phase quantization, which is close enough to be considered satisfactory. Nevertheless, it is beneficial to find a way to further reduce the quantization noise layer to provide some execution margin. Exemplary techniques for reducing the noise floor may include some or all of the following: the use of preemphasis, an increase in the number of bits used in phase synchronization, an increase in frequency deviation, and an increase in phase sampling rate. . Each of these methods is considered in turn.

Pre-emphasis is a technique already known in conventional FM radio systems for improving sound quality. Note that most of the quantization noise energy is generated at the top end of the audio frequency band, the frequency deviation given by the higher audio frequency is increased in the modulator and the output of the demodulator is correspondingly reduced at that frequency, thereby Attenuates dominant noise components

Microphones are generally designed to provide a flat frequency response from the sound pressure wave input to the electrical signal output. Therefore, in order to use the pre-emphasis, a frequency response shaping is required between the output of the microphone and the response to the frequency modulator. This frequency response shaping will result in amplification of the high frequency components, which may require active circuitry. However, one object of the present invention is to facilitate the integration of all active circuits on integrated circuit chips. Thus, as a solution, one can design the acoustic (ie mechanical) components of the microphone, such as the diaphragm and the surrounding cavity, to implement acoustic pre-emphasis. Alternatively, the pre-emphasis circuit can be integrated into the chip, preferably externally connected to the microphone. The microphone signal enters the chip at a low level before amplification, a point sensitive to noise pickup. Therefore, this type of pre-emphasis is not a preferred method even if one of the prior art knows when a design exchange makes it an acceptable solution.

The preferred form of pre-emphasis is to use a microphone with a naturally rising frequency response that provides greater electrical input for the same sound sound pressure vibration level at higher frequencies. However, such specially tailored microphones are generally not available, so other methods of obtaining improved sound quality (eg, using one more bit of phase precision) in conjunction with the available microphones can be used.

One way to improve sound quality is to increase the number of bits used to represent the quantization phase. The extra bits of phase quantization accuracy each improve the audio quality by 6dB. Increasing the phase quantization accuracy is equivalent to timing shifting the FM carrier signal with finer time accuracy. This can be done by using a higher clock frequency as a reference for the phase digitizer, or by timing transitions to part of the clock cycle. For example, the sawtooth clock waveform may be repeatedly reset to zero, resulting in a linear upward slope. The slope can be sampled when a transition of the FM carrier signal occurs to determine the amplitude, thereby quantizing the transition time to a portion of the clock cycle. Another related method may include the generation of sine and cosine clock waveforms that are sampled when a transition occurs, where the fractional phase value is given as an arctangent of the sine / cosine sample ratio. These methods include the analog circuit concept, which is particularly undesirable for integration onto digital integrated circuits. A more suitable method for integration is to calculate the average phase over one or more transitions that occur between phase sampling instants. For example, if the phase is sampled at 240K samples / s and the FM carrier frequency is nominally 1 MHz, then the carrier transition is at least three positive values and the carrier transition is at least three negative values within each 240 KHz period. There is. If a phase sample given a negative transition is corrected for a 180 degree phase difference between half cycles, both negative and positive transitions can be used. The exact average of -179 and +179 degrees is 180 degrees, not zero, so care must be taken when calculating the average value of the angle measurement. Theoretically the best way to average the angles is to average their sine and cosine values separately and calculate the resulting ARCTAN values. This technique is known as circular averaging.

The digital phase locked loop (PLL) described above provides a simpler practical method for averaging phase measurements from a large number of signal transitions. Moreover, the phase digitizer (not shown) preceding the digital PLL of FIG. 18 is removed so that phase digitization is performed by the PLL itself. This reduction is possible because the application of current PLLs for inventive digitalization of audio signals involves digital FM demodulation in the absence of radio noise.

25 shows an exemplary PLL system. The FM input signal is applied to the transition detector 110. When the input signal transitions from the previous logic '0' level that was stored in flip-flop 111 to the logic '1' level, the Q output of flip-flop 111 becomes '1'. The input of the NAND gate 112 of two inputs is performed, and a logic '0' is applied to the D input of the flip-flop 113. This input is registered to flip-flop 113 upon generation of a reference clock pulse, resulting in a rising edge at the Q output of 113 and a falling edge at the Q output. Binary logic '1' at the Q output operates gate 127 such that the contents of phase accumulator 120 appear at the output of gate 127 as long as the control input is logic '1'. This value is multiplied by ALPHA in multiplier 125 and subtracted from the phase value PHI received from accumulator 120 in subtractor 122. This occurs during a single reference clock cycle since the Q output of the flip-flop 113 returns to logic '0' after the transition of the FM signal input has passed to cause the gate 127 to resume the output of zero value. Thus, the ALPHA.E value is added only once to the phase accumulator 120, while the frequency value ω is added every reference clock pulse. While gate 127 conveys the phase accumulator value, it is also multiplied by BETA in multiplier 126 and subtracted from the previous value of ω in subtractor 124. At this time, the new value is registered in the integrator register 12 at the rising edge of the Q output of the flip-flop 113, coinciding with the return of the gate 127 to the zero output state. Subtracting BETA.E from the previous value of ω is unchanged. The modified value of ω permanently affects the rate at which phase accumulator 120 is increased. That is, while this affects the phase deviation, the ALPHA.E value only affects the phase once, permanently affecting the phase value but not the deviation. In this method, the coefficients ALPHA and BETA are chosen to form a second order digital phase locked loop with the desired characteristics as above. ALPHA and BETA are preferably chosen to be the inverse of the two such that the multiplication is reduced by shifts. The values of ALPHA and BETA are similar to those discussed previously in the digital PLL design, except that the value of BETA is reduced because the phase deviation value ω is added to the phase accumulator 120 several times between each iteration. The number of additions is equal to the number of reference clock pulse periods in the nominal period of the FM input signal. For example, assume that the FM input signal frequency is 620 KHz and the reference clock is 19.2 MHz. On average, the ω value is approximately 19200/620 = 31 times added to the phase accumulator per cycle of the FM input. Thus, the value of BETA should be about 1/32 times the value shown in FIGS. 21-23 for this exemplary PLL. Moreover, the loop frequency response characteristic shows a wider bandwidth in proportion to the increased update frequency, which is now equal to the FM input frequency, for example 620 KHz instead of 240 KHz. Therefore, lower ALPHA and BETA values should be used to maintain similar loop frequency response. Since the frequency value ω is sampled by a lower frequency sampling clock using a sampler 130, it is preferable that the loop frequency characteristic attenuate the frequency at least half of the final sampling rate to prevent aliasing. Do. 21 can be used to find appropriate values of ALPHA and BETA as follows.

The loop update rate (eg 620 KHz) is 620/240 times that used to make FIG. 21. ALPHA = 0.25 and BETA = 1/32 create a flat bandwidth before about 4KHz, so at a higher update rate, it is flat at 4KHz x 620/240 = 10.33KHz. The loop previously exhibited 30dB of attenuation at approximately 45KHz. Thus, a 30 dB attenuation occurs at 45 KHz x 620/240, which is less than half of the 240 KHz sampling rate conceived for the sampler 130. Thus, the loop must provide sufficient attenuation of the aliasing component without further digital filtering before sampling. The exemplary values of ALPHA and BETA proposed for the arrangement of FIG. 25 are ALPHA = 0.25, BETA = 1/1024, and the BETA reduction to 32: 1 is due to the reasons mentioned above.

The ω value held in the flip-flop 123 of FIG. 25 represents the instantaneous frequency deviation dω due to the input signal carrier frequency ω ₀ + audio modulation. Since only the latter is of interest, the average frequency ω ₀ should be removed before sampling. In FIG. 25 this is done by the subtractor 131. Since the subtracted average frequency can be calculated and supplied again later by digital signal processing, a specific circuit for calculating the average frequency is not shown in FIG.

In another exemplary embodiment, it is desirable to set the initial content of flip-flop 123 to the expected average frequency to prevent delays in the initial acquisition of phase synchronization. This can be done at the same time as subtracting the average frequency with the rearrangement of FIG. In FIG. 26, the frequency flip-flop 123 maintains the frequency deviation dω from the mean. Instead of the subtractor 131 of FIG. 25, the adder 132 of FIG. 26 is provided. The adder 132 adds the average frequency ω ₀ to find the increase rate ω = ω ₀ + dω of the phase accumulator. This average frequency is thought to be set by feedback from another process and thus achieves both the removal of the average frequency and the initial frequency setting function from the sampled output of the sampler 130.

FIG. 27 illustrates exemplary word lengths of various digital quantities in FIG. 26. Phase accumulator 120 is shown as a 21-bit register A with phase and frequency significance of the bits. The frequency significance value is applied when the displayed bits are added at a 19.2 MHz rate. For example, if the highest value 11 is added repeatedly, the phase accumulator executes the sequences 10000 ..., 00000 ...., 10000 .... and so on, and the phase sequence 0, Pi, 0, Pi,. Indicates. This makes a complete cycle every two reference clock periods. That is 9.6 Megacycles per second. Each successive bit has half the frequency significance and the least significant bit has a significance of approximately 9 Hz (9.6 MHz / 2 ** 20).

The increment ω ₀ required to create a nominal frequency of 620.625 KHz is shown in register B of FIG. 27. The four most significant bits of the increment are zeros, like the least significant bit, so 16-bit is sufficient to define ω ₀ . The frequency deviation dω near ω ₀ is represented by register C. If the frequency deviation is within +/- 150KHz, it can be represented as a 16-bit value. The most significant bit (ie, 150 KHz accumulator bit) is considered a sign and is an extended sign to add to phase accumulator 120. The instantaneous frequency deviation value dω is updated by subtracting 1/1024 of the value of the phase accumulator at the instant the input signal becomes a positive transition. Register D shows the accumulator value shifted by 10 binary digits representing division by 1024. The remaining 12 bits are the sign extended to 16 bits in register D to add to the 16-bit dω value C. Finally, register E shows the accumulator multiplied by ALPHA (eg, 0.25), which is a 2-bit left shift.

In FIG. 26, the accumulator phase value is tested every time the input signal transitions from low level to high level at a rate greater than 470 KHz so that the frequency displacement never becomes more than 150 KHz. If the phase change between samples is absolute maximum and never greater than +/- Pi, a peak frequency deviation of 235 KHz can be used. Indeed, according to this embodiment, the frequency can only deviate from +/- 150 KHz, but there is still an increase in the exemplary system of FIGS. 2 to 24 where the frequency deviation was limited to about 100 KHz. Normal speech deviation is increased by approximately 3dB compared to previously considered values, improving the dynamic range by 3dB. On the other hand, it was previously thought that the input signal transition is quantized with half a cycle of a 19.2 MHz reference clock providing 6-bit phase quantization. The transition is quantized in one cycle of the reference clock in the systems of Figures 25 and 26, reducing the loss of 6dB, i.e., the same phase quantization accuracy to 5-bit. However, this further consists in increasing the sampling rate from approximately 240KHz to 600KHz when the quantization noise power within the 3.4KHz audio range is reduced by the cube of the sampling rate (9dB for 2: 1). Thus, the arrangement of FIGS. 25-27 is expected to indicate that the quantization noise is reduced by at least 6 dB after downsampling the frequency output word to 8K samples / second.

Methods for converting acoustic sound pressure waves into frequency or phase modulated electrical signals include capacitor microphones forming part of the resonator circuit of the oscillator, variable inductance microphones forming part of the oscillator circuit, and one or more variable capacitance diodes forming part of the oscillator circuit. Air electret or piezoelectric crystal microphones, or microphones that generate voltage or current signals to control voltage or current controlled oscillators. 28A shows a conventional microphone arrangement. Conventional arrangements include a microphone 210 including a piezoelectric transducer 208, a high value resistor 207, and a FET preamplifier 206. Since the FET preamplifier generally has an open collector output that is both used to bias the FET and also to obtain the audio output, the microphone thereby retains the components of the two terminals. The bias is applied from the low noise bias voltage source 201 through a resistor 205 through which current flow through the FET develops the audio signal. The DC voltage level on the output is an arbitrary value and is removed by the blocking capacitor 204 before further amplification in the microphone amplifier 202. An inconvenience in this conventional arrangement is that an exceptionally low noise bias source 201 is required. Typically, the normal RMS speech signal from the microphone corresponding to level A of FIG. 24 is 5 mV RMS. The noise floor is required to be 58dB below this level, or 6μV. However, the conventional circuit of FIG. 28A is very sensitive to noise pick-up for the signal from the resistor 205 to the microphone amplifier 202 through the capacitor 204 and the resistor 203 as well as the noise from the bias source.

An exemplary microphone arrangement that addresses these inconveniences in accordance with the present invention is shown in FIG. 28B. Here, the microphone 220 includes a piezoelectric element 208 and a resistor 207 as before, but without the FET preamplifier 206. Therefore, no bias supply current is needed. Instead, the piezoelectric element (electret) 208 output voltage is coupled to the capacitance of varactor diodes 211 and 212, which together with the inductor 213 form a resonant circuit for the oscillator 230. Change. The oscillator is preferably a relatively low level oscillator that does not apply sufficient AC voltage swing to the varactor diodes 211 and 212 driven by omnidirectional conduction. It is desirable to operate varactor diodes 211 and 212 at zero reverse bias voltage to avoid the need to generate a low noise bias voltage and to maximize the frequency-modulation sensitivity of the oscillator. A ground line from the center tap on inductor 213 (shown in dashed lines in FIG. 28B) to ensure that low frequency (audio) noise pickup does not occur on lines between varactors 211 and 212 and inductor 213. Is suggested. Nevertheless, the low level oscillation produced by oscillator 230 may be over 100 mV when the varactor diode is not driven in forward conduction until 300-400 mV is reached. Thus, the oscillator signal is a high frequency FM signal that is 20 times higher than the microphone signal of the conventional microphone circuit arrangement of FIG. 28A and furthermore is relatively insensitive to interference pickup. In this way, the system of the present invention not only simplifies the circuit by removing the bias source 201 and the microphone amplifier 202, but also significantly reduces the sensitivity to noise pickup.

Alternatively, a circuit using the current controlled oscillator shown in FIG. 29 can be used. A known type of current controlled oscillator is an emitter-coupled multivibrator or a source-coupled multivibrator, which is the same FET, which is shown in FIG. The microphone 210 includes an electret element 208 and two identical FET transconductance amplifiers 206a and 206b that convert the electret audio voltage into a pair of audio current sources of magnitude I. . These currents form the tail current of N-type FETs 241 and 242 that are cross-connected drain-to-gate and source-connected by timing capacitor C 240. It can be seen that the circuit oscillates at a frequency proportional to the source waveform and the current I, which is approximately represented. Assuming that FETs 206a and 206b are good current sources, audio current I and frequency modulation do not strongly depend on supply voltage Vcc, so a measure of immunity to supply voltage noise is obtained.

In order to obtain a sufficiently high frequency deviation by the above-described method, it is preferable to use a high frequency frequency modulated oscillator mixed downward in the desired 620 KHz range. Otherwise, for example, creating a peak deviation of +/- 150KHz in a 620KHz oscillator can be difficult because this is a high percentage change. On the other hand, it is simpler to create a +/- 150KHz peak deviation in an 18.6MHz oscillator downmixed to 600KHz versus a 19.2MHz reference oscillator. Suitable mixing arrangements can be formed using digital logic components as shown in FIG.

Here, the FM input signal at nominally 18.6 MHz is applied to the D inputs of flip-flops 400 and 401 that are triggered at the edge. The flip-flop 400 is clocked by a 19.2 MHz reference clock and the flip-flop 401 is clocked by an inverted clock. Flip-flops provide square wave outputs with a relatively inverted 100KHz differential frequency. The relative inversion is flip-is rectified by using the Q output of the flop (401) - and Q output of flip-flop 400. Moreover, the 600 KHz output of flip-flop 400 has a transition synchronized to the 19.2 MHz clock rising edge, and the output of flip-flop 401 is synchronized to the falling edge. Thus, a transition of 600 KHz differential frequency between the two is preserved at half the cycle accuracy of the reference clock, which is used to obtain 6-bit phase quantization.

The 19.2 MHz clock also drives circuit 402, which is divided by 32. The output of circuit 402 is increased on the rising edge of the clock and stabilized during the falling edge of the clock. The output of circuit 402 is also timed to the falling edge of the clock by latch 405. Thus, the count sequence produced by circuit 402 and latch 405 is for example:

Circuit 402: ... 25 26 27 28 29 30 31 0 1 2 .....

Latch (504): ..... 25 26 27 28 29 30 31 0 1 2 ....

Now, depending on the transition timing of the 18.6 MHz FM input signal, a rising edge on the 600 KHz output of the flip-flop 400 may occur half a cycle of the reference clock before the rising edge on the Q output of the flip-flop 401. May occur. For example, if the former occurs first at count 27 of counter 402, then the contents of latch 405 are 26, and the number is latched by latch 404. Then, if the output of flip-flop 401 occurs at count 27 of latch 405, then circuit 402 includes 27, the number of which is latched by latch 403. The sum of the latches 403 and 404 given by the adder 406 adds up to a six-bit number 26 + 27 = 53.

On the other hand, if a transition on the Q output of flip-flop 401 occurs half a cycle of the clock prior to the Q output of 400 at value 26 at latch 405, then circuit 402 contains a value 26. The value is latched by the latch 403. Subsequently, when a transition on the Q output of flip-flop 400 occurs at count 27 of circuit 402, latch 405 continues to include 26, the value of which is latched to latch 404. The sum given by adder 406 in this example is 26 + 26 = 52, which reflects an 18.6 MHz input transition occurring half a clock cycle first. In this way, the summation output of adder 406 represents the signal phase with half the timing accuracy of the reference clock cycle. The 6-bit phase sequence is applied to the digital PLL 407 according to FIG. 18 with a clock derived from the Q output of the flip-flop 401 to ensure that the phase value is only used long after the output of the adder 406 has stabilized. Check it. The ALPHA, BETA values of the PLL 407 are selected to provide the desired frequency response at a clock rate of 600 KHz as described above. The increased clock rate of 600 KHz, compared to the 240 KHz value detailed above, reduces quantization noise by at least 9 dB. The frequency estimate calculated and filtered by the PLL is then downsampled to 240 KHz by circuit 408 dividing by 80. This ensures that downsampling occurs after the updated frequency value has stabilized since the clock is adjusted by the rising edge of the reference clock while the PLL 407 updates its value in synchronization with the falling edge. The 240K samples / s frequency value can then be further downsampled to 8KHz using known downsampling filter techniques.

While numerous modifications of the invention have been described in which other derivatives may be made by one skilled in the art, these are in addition to the scope and spirit of the invention as described by the following claims.

Claims (30)

In the method of digitizing an audio signal, Frequency modulating an oscillator into the audio signal; Applying the frequency modulated oscillator signal to a digital frequency discriminator for calculating a sequence of instantaneous frequency values; And Using the instantaneous frequency value as the digitalized audio signal Audio signal digitalization method comprising a. A method of digitizing an audio signal that produces a sequence representing a numerical value at a desired sampling instant, Frequency modulating an oscillator into the audio signal; Combining the frequency modulated oscillator signal with a reference frequency clock to generate a sequence of instantaneous phase values of the oscillator signal; And Numerically estimating the rate of change of the instantaneous phase value at the desired sampling instant and using the estimated rate of change as the displayed numerical value Audio signal digitalization method comprising a. The method of claim 1, And the digital frequency discriminator is a digital phase lock loop. The method of claim 2, And wherein said phase change rate estimation is performed using a digital phase locked loop. The method of claim 2, And the phase change rate estimation is performed by differentiating successive phase values. A method of generating a sampled digital representation of an acoustic pressure wave, Converting the acoustic sound pressure wave into a change in a corresponding electrical capacitance; Generating a corresponding change in frequency of an electrical oscillator signal using the change in electrical capacitance; Applying the frequency modulated oscillator signal to a digital frequency discriminator for calculating a sequence of instantaneous frequency values; And Using the instantaneous frequency value as the digitalized audio signal Method comprising a. A method of generating a sampled digital representation of an acoustic pressure wave, Converting the acoustic sound pressure wave into a change in a corresponding electrical capacitance; Generating a corresponding change in frequency of an electrical oscillator signal using the change in electrical capacitance; Combining the frequency modulated oscillator signal with a reference frequency clock to generate a sequence of instantaneous phase values of the oscillator signal; And Numerically estimating the rate of change of the instantaneous phase value at the desired sampling instant and using the estimated rate of change as the display numerical value Method comprising a. The method of claim 7, wherein And the digital frequency discriminator is a digital phase locked loop. The method of claim 6, And wherein said phase change rate estimation is performed using a digital phase locked loop. The method of claim 6, And said phase change rate estimation is performed by differentiating successive phase values. The method of claim 6, Wherein the change in electrical capacitance is generated using a capacitance microphone. The method of claim 7, wherein Wherein the change in electrical capacitance is generated using a capacitance microphone. The method of claim 6, Wherein the change in electrical capacitance is generated using a piezoelectric microphone and a variable capacitance diode. The method of claim 7, wherein Wherein the change in electrical capacitance is generated using a piezoelectric microphone and a variable capacitance diode. The method of claim 1, And the center frequency of the oscillator is offset more than the highest audio frequency from the center frequency of the digital discriminator. The method of claim 2, And the center frequency of the oscillator is offset more than the highest audio frequency from a submultiple of the reference clock frequency. In an analog-to-digital convertor that generates a sequence of numerical sample values representing a signal waveform, Oscillator means for generating a high frequency signal; Frequency / phase modulation means for changing a frequency and a phase angle of the high frequency signal in response to the signal waveform; Digital frequency discriminator means for determining a numerical value for the instantaneous signal frequency of said oscillator at a predetermined sampling instant; And Output means for outputting the numerical value as the displayed numerical sample value Analog-to-digital converter comprising a. The method of claim 17, And downsampling means for filtering the instantaneous numerical frequency values to produce filtered samples at a reduced sample rate. An analog-to-digital converter for generating a sequence of numerical sample values representing a signal waveform at a first sampling rate, wherein Oscillator means for generating a high frequency signal; Frequency / phase modulation means for changing a frequency or phase angle of the high frequency signal in response to the signal waveform; Direct phase digitizing means for combining the oscillator signal with a reference frequency clock signal to produce a numerical value representing an instantaneous phase at a second sampling rate; And Processing means for processing said phase sample at said second sampling rate to produce said signal waveform display sample at said first sampling rate Analog-to-digital converter comprising a. The method of claim 19, And said processing means reduces quantization noise by digital lowpass filtering. The method of claim 19, And said processing means comprises a digital phase locked loop. A microphone circuit for generating a numerical sample stream representing sound pressure waves without being affected by electrical noise pickup, Transducer means for converting a change in sound pressure wave into a change in a corresponding electrical parameter; Oscillator means for generating an oscillator signal having a frequency that depends on the electrical parameters; Digital frequency discriminator means for determining a numerical value for the instantaneous signal frequency of said oscillator at a predetermined sampling instant; And Output means for outputting the numerical value to the display numerical sample stream Microphone circuit comprising a. A microphone circuit for generating a numerical sample stream representing a sound pressure wave at a first sampling rate without being affected by electrical noise pickup, Transducer means for converting a change in sound pressure wave into a change in a corresponding electrical parameter; Oscillator means for generating an oscillator signal having a frequency dependent on the electrical parameters; Direct phase digitizing means for combining the oscillator signal with a reference frequency clock signal to produce a numerical value representing an instantaneous phase at a second sampling rate; And Processing means for processing said numerical value at said second sampling rate to produce said numerical sample stream at said first sampling rate Microphone circuit comprising a. The method of claim 23, wherein And said processing means reduces quantization noise by digital lowpass filtering. The method of claim 23, wherein And said processing means comprises a digital phase locked loop. The method of claim 22, And the transducer means is a piezoelectric transducer. The method of claim 22, And the electrical parameter is capacitance. The method of claim 23, wherein And the transducer means is a piezoelectric transducer. The method of claim 23, wherein And the electrical parameter is capacitance. A microphone circuit for generating a numerical sample stream representing a sound pressure wave at a first sampling rate without being affected by electrical noise pickup, Transducer means for converting a change in sound pressure wave into a change in a corresponding electrical parameter; Oscillator means for generating an oscillator signal having a frequency that depends on the electrical parameters; Digital mixing means for combining the oscillator signal with a reference frequency clock signal to produce at least one differential frequency signal; Direct phase digitalization means for combining said at least one differential frequency signal with said reference frequency clock signal to produce a numerical value representing an instantaneous phase at a second sampling rate; And Processing means for processing said numerical value at said second sampling rate to produce said numerical sample stream at said first sampling rate Microphone circuit comprising a.