MXPA98009661A - An a / d audio converter using fraud modulation - Google Patents

Abstract

The present invention relates to exemplary embodiments, a voltage or current controlled oscillator is frequency controlled by the signal (i.e., voltage or current) from a microphone. The frequency-modulated signal is applied to a direct digital discriminator that produces a digital representation of the instantaneous frequency at the desired speech sampling rate. The digital discriminator can be formed, for example, by applying the oscillator signal as a direct phase digitalization circuit together with a reference frequency and calculating the instantaneous phase sequence of the oscillator relative to the reference frequency. The phase sequence is then applied to a digital phase locked circuit (or differently numerically differentiated) to generate a sequence of binary words representative of the instantaneous frequency and therefore representative of the speech waveform. Since the low-level speech waveform does not essentially support the integrated circuit except as a high-level frequency-modulated carrier, the technique is immune to noise caused by randomized logic circuits such as microprocessors and DSPS that work in the integrated circuit

Description

"AN A / D AUDIO CONVERTER USING FREQUENCY MODULATION" BACKGROUND The present invention relates generally to reducing the cost of electronic systems that involve voice processing, such as telephones or cell phones by integrating the different electronic systems into a single integrated silicon circuit. More particularly, the present invention relates to analog-to-digital converters which minimize a number of analog components used therein and which is also relatively immune to the pickup of noise from the digital circuits operating in the integrated circuit. There are many forms of conventional analog-to-digital converters, for example those known by the types of techniques used therein, such as Delta-Sigma Successive Approximation modulation, and Delta Modulation of Continuously Variable Tilt (CVSD). The purpose of these devices is to produce a stream of numbers presenting the samples of the value of the instantaneous signal at a desired sampling rate. The desired sampling rate is usually higher than the minimum Nyquist regime of twice the maximum frequency of the analog signal to be represented numerically. The drawbacks of these prior art techniques are related to a very small signal level output from the microphone, which results in the connection between the microphone and the analog-to-digital converter which is sensitive to picking up noise.

COMPENDIUM In accordance with exemplary embodiments, a variable frequency oscillator is frequency controlled by a variable electrical parameter in a microphone, typically a variable capacitance. The frequency-modulated signal is applied to a direct digital discriminator that produces a digital representation of the instantaneous frequency at the desired speech sampling rate. The digital discriminator can be formed, for example, by applying the oscillator signal to a direct phase digitizing circuit together with a reference frequency and calculating a sequence of instantaneous phases of the oscillator relative to the reference frequency. The phase frequency is then applied to a digital phase lock circuit (or differently numerically differentiated) to generate a sequence of binary words representative of the instantaneous frequency and therefore representative of the speech waveform. Since the low-level speech waveform essentially does not enter the integrated circuit except as a high-level frequency-modulated carrier, the technique is essentially immune to noise caused by high-speed random logic circuits such as microprocessors and DSPs that work in the integrated circuit. In accordance with other exemplary embodiments of the present invention, the microphone circuit still based on the variable electrical voltage or current parameter may be provided which is less susceptible to noise than the conventional microphone circuit. For example, conventional FET preamplifiers can be omitted according to the invention so as to avoid the noise typically created by polarization supplies.

BRIEF DESCRIPTION OF THE DRAWINGS These features and advantages of the applicant's invention will be more readily understood by reading the following detailed description together with the drawings, in which: Figure 1 is a functional diagram of a digital speech processing circuit in accordance with an exemplary embodiment of the present invention; Figure 2 is a graph illustrating an exemplary speech frequency spectrum before descending sampling for three exemplary quantization accuracies; Figures 3 and 4 are graphs that illustrate the spectrum of the quantized signal and noise during silent periods; Figures 5 and 6 are graphs that illustrate the spectrum of the quantized signal and noise using a 1 KHz sine wave test; Figure 7 is a graph illustrating the harmonic distortion for silent period signals; Figure 8 is a graph illustrating the reduction of harmonic distortion by introducing a deliberate frequency offset in accordance with the present invention; Figures 9 to 11 are graphs illustrating that the harmonic distortion decreases when the level of the signal is reduced and a deliberate frequency offset is applied in accordance with the present invention; Figure 12 is a graph illustrating the spectrum of a test signal similar to the noise into which the deliberate frequency offset has been introduced; Figure 13 is a graph illustrating a reduced signal level version of the test signal of Figure 12; Figures 14 and 15 are graphs illustrating residual quantization noise after subtraction of the desired signal from the frequency spectrum; Figures 16 and 17 are graphs illustrating a pause of speech in a signal using quantization of six bits and residual noise therein, respectively, for a signal to which frequency offset has been applied; Figure 18 is a functional diagram of a digital phase locked circuit that can be used in systems in accordance with the present invention; Figure 19 is a graph illustrating the residual noise spectrum for an exemplary digital phase locked circuit with frequency offset introduced in accordance with the present invention; Figure 20 is a graph illustrating the residual noise spectrum for an in-phase locked circuit when a frequency offset is not provided; Figures 21 to 23 are graphs illustrating the different frequency transfer characteristics of the exempted second phase order locked circuits; Figure 24 illustrates an exemplary dynamic scale specification for a typical wireless communication application; Figure 25 is a functional diagram representing an in-phase locked circuit that can be used as a demodulator in accordance with the present invention; Figure 26 is a functional diagram illustrating a modification of the exemplary embodiment of Figure 25, including the average frequency setting; Figure 27 illustrates exemplary word lengths for the various digital quantities used in the exemplary embodiments of Figure 26; Figure 28 (a) illustrates a conventional microphone circuit arrangement; Figure 28 (b) illustrates an electret microphone that controls an oscillator in accordance with an exemplary embodiment of the present invention; Figure 29 illustrates a multivibrator coupled with the exemplary source that can be used as a current controlled oscillator in accordance with an exemplary embodiment of the present invention; and Figure 30 is a representation of the functional diagram of a digital mixer in accordance with an exemplary embodiment of the present invention.

DETAILED DESCRIPTION U.S. Patent No. 5,084,669, which is incorporated herein by reference, describes the techniques for determining the instantaneous phase and frequency of a radio signal modulated in phase or frequency, as a series of numerical values at a desired sampling rate using a digital logic circuit US Patent Number 5,220,275 issued to Holmqvist, which is also incorporated herein by reference, discloses a method for determining the instantaneous phase of a signal as a numerical value calculated at a desired sample rate. These digital phase / frequency determination circuits are disclosed in these patents to demodulate a modulated radio signal received by a radio receiver. The present invention employs these types of circuits in a new application for digitizing a speech signal by first converting the speech signal into a frequency modulated carrier wave and then using digital discriminator circuits to convert the wave signal of the modulated carrier into a train of numerical samples representative of the speech waveform. A first exemplary embodiment of the invention is described with the aid of Figure 1. Therein, an active microphone 20 includes a variable capacitance microphone element 10 which forms part of the resonant circuit LC of an oscillator 12. The signal of oscillator output can be at a frequency of 1MHz, for example, and preferably exit the active microphone 20 as a balanced signal from the buffer amplifier 13. The use of balanced signal produces performance whereby antiphase signals are operated on parallel conductive tracks on a printed circuit board that minimizes coupling with other nearby circuits, reducing the risk of causing interference and reducing the susceptibility of interference. The waveforms of acoustic speech are translated into movements of the diaphragm of the microphone element 10 and therefore, into variations of capacitance and then of frequency reactions of the oscillator. The speech waveform in this way modulates the frequency of the oscillator signal and the F.M. signal. ^ is fed to a direct phase digitizer 30 such as that disclosed in the patents incorporated in the foregoing. The phase digitizer 30 compares both 5 transitions going to the positive and negative state of the carrier signal of F.M. in a reference clock and quantifies the time in which those transitions occur up to an accuracy of, for example, half a clock period. The numerical result of circuit 30 is, for For example, a 6-bit binary value representing the instantaneous phase at an output sample rate that is a large factor higher than the final desired 8KHz speech sampling rate. For example, the sampling rate can be 32 times higher, at 256K samples per seconds. The sampling regime must in any case be high enough so that the deviation from • The instantaneous phase of the carrier frequency from a nominal phase can not change by more than +/- 180 degrees (that is, a half cycle) during a sample period. That is, the The sample rate must at least be twice the deviation of the maximum frequency from the nominal carrier frequency produced by the vibrations of the diaphragm induced by speech. This is desirable because a phase value greater than 180 degrees can not distinguish in a negative phase value of less than 180 degrees, and vice versa. Preferably, the phase change through a sample period should be less than +/- 90 degrees to provide the greatest margin to discriminate the positive phase changes from the negative and avoid the ambiguous region around +/- 180 degrees . The phase samples of the phase analyzer 30 are fed to a numerical differentiator 31 which calculates the module 2Pi differences between the successive samples. Due to the preferential relationship described above between the sample rate and the deviation from the maximum frequency, the phase difference will be within the scale of +/- 90 degrees. The difference will therefore nominally have the same word length as the original phase sample. For example, if the phase is calculated to an accuracy of 6-bits, positive integers 0 to 31 represent angles greater than 0 and less than 180 degrees while negative integers represent angles less than 0 and greater than -180 ° degrees. A phase difference nominally between +/- 90 degrees is therefore representable by integers between 16 and +16, within a 6-bit word length and allowing a greater space for larger ridges. The 6-bit phase differences to, for example, 256K samples / S are then sampled down to 8K samples / S by a digital low-pass filter. The first stage of this low pass filter, for example, may comprise calculating the sum of 32 successive samples through a movable window of a width of 32 samples. This results in 11-bit quantities in this example. The second filtering step may comprise accumulating together 32 moving averages of 11 successive bits one time per block of 32 samples to obtain 16 bit values at a sample rate of 8K samples / S as required. As disclosed in US Patent Application Serial Number 08 / 120,426 filed on September 14, 1993, issued to Paul W. Dent, which is incorporated herein by reference, this downward sampling leads to a reduction in the response of frequency at the highest speech frequency of 3.4KHz, which can be compensated by readjusting the accumulator before each new accumulation up to a negative fraction of its previous value. Assuming that the quantization noise in the phase differences is uniformly distributed in frequency between zero and the Nyquist frequency of 128KHz, the down sampling filter reduces the quantization noise power by the bandwidth reduction factor of 32: 1 , which is equivalent to 2.5 bits of precision and in this way the equivalent accuracy of this method is only 8.5 bits and is not equal to the 16-bit length of the calculated values. The quantization noise spectrum however is uniform in the phase domain, but since the phase differentiates to carry out the frequency demodulation, the spectrum would be expected to rise up to 6dB per octave of frequency, and so it would have less noise at lower frequencies than at higher frequencies. In this way, the majority of the quantization noise power would be expected to be grouped towards half the sampling rate and the amount to be left in the audio band from 0 to 3.4KHz, to be significantly reduced. Figure 2 shows the broad spectrum of the descending sampling of the phase differences. The desired signal modulation is a white noise signal with a spectrum extending from 200Hz to 3.4KHz representing speech, and which is adjusted to produce a RMS frequency deviation of one third of the 50KHz peak deviation, which is selected to be less than a quarter of the 240KHz sample regime due to the reasons explained above. This ensures that the 3-sigma limits of the desired noise-like signal are maintained within the peak deviation. The spectrum in Figure 2 shows the quantization noise outside the 3.4 KHz scale that is fl | It will be removed by the downstream sampling filter, for different precisions of phase quantization in bits. Therefore, the tendency for the quantization noise spectrum to decrease toward a frequency of zero as predicted above is confirmed. However, the quantization noise within the 3.4KHz scale can not be seen in Figure 2 and this is masked by the signal spectrum. Other figures will be discussed later that show the quantization noise within the audio band by subtracting the desired signal. Figure 2 shows the density of the quantization noise of the edge of the band which is less than the spectral density of the signal by the following quantities. 15 WHAT IFICATION PHASE 4-bit 8-Lbit 12-bit DENSITY N / S BAND SHORE -35dB -60dB -85dB 20 These values follow the improvement law of 6dB per quantization accuracy bit, that is, 24dB per 4 bits. Assuming for the moment that the noise in band 25 decreases towards the frequency from zero to 6dB per octave, the total noise power can be calculated by integration providing a total signal to noise power ratio 3 times (4.77dB) better than the figures cited above. The band quantization noise in this manner can be expressed in an apparent noise frequency deviation in Hz RMS in the following manner.

QUANTIFICATION OF PHASE 4-bit 6-bit 8-bit 10-bit 12-bit Bandwidth deviation (Hz RMS) 167Hz 43Hz 10Hz 2.6Hz 0.53Hz Speech quality is generally considered to be more related to noise in the speech pauses of noise crests in speech. Figures 3 and 4 show the quantized signal spectrum plus noise with reduced speech modulation 20 and 40dB, respectively. A trend can be observed in these figures for the quantization noise at the edge of the 3.4KHz band in order to be reduced with the reduced signal power, which is a favorable trend, but there is also a tendency for the spectrum to become flat , which is not favorable. It can be shown that the greater proportion of the noise remaining in the lower frequency part of the spectrum is caused by the same one that drives the phase through its quantization levels. With smaller signal excursions, the quantization levels are crossed at a lower rate so that the quantization noise spectrum has more energy at low frequency. With these sinusoidal wave signals in addition, the quantization noise will appear in the harmonic of the frequency signal, since level crossing will occur at regularly defined points in the waveform of the signal. This is confirmed by Figures 5 and 6 which show an exemplary signal plus the quantization noise spectrum using a 1KHz sine wave test signal, with 8-bit and 4-bit phase quantization, respectively. Because the quantization levels are placed symmetrically in the plane of the phase, the odd harmonics dominate and the third harmonic is around 66dB down in the fundamental with quantification of 8-bits and 40dB down with quantification of 4- bits. However, the distortion of the third relative harmonic increases as the signal decreases as shown in Figure 7, where the third harmonic rises to only 14dB below a reduced signal level of 20dB. These effects can be considerably improved by the use of an off-centering of the deliberate carrier frequency such that the phase of the signal rapidly rotates through all levels of quantization even in the absence of speech modulation. For example, Figure 8 shows an exemplary spectrum where a carrier frequency offset of 20.625Hz is employed. This specific value of the carrier frequency is not critical and was selected to facilitate the calculation of the spectrum by providing a phase waveform that was repeated in a finite number of 4096 time samples at 240K samples per second. In this way, those skilled in the art will appreciate that any off-centering of the carrier frequency can be applied, however the off-center should be selected high enough so that changes occur in the systematic quantization step at frequencies greater than the maximum audio frequencies. It will be seen that the third harmonic with 4-bit phase quantization has decreased from -40dB to almost 50dB below the fundamental one. Now, when the signal deviation is reduced, as shown in Figure 9, the distortion of the harmonic does not increase but actually decreases, and is still within the region -40dB to -50dB with a reduced signal of 20dB. Figure 10 shows that even with a reduced signal of 40dB, the noise and distortion products are still below 25dB. Figure 11 shows that odd harmonics appear equal to the signal when the power of the signal is reduced by 60dB. Figures 5 to 11 all confirm that the quantization noise spectrum decreases to a frequency of zero. Figures 12 and 13 show the noise-like test signal using deliberate frequency offset. The deviation of the full test signal in Figure 12 is employed and provides a quantization noise spectrum with a 4-bit phase quantization that is similar to the 4-bit quantized spectrum of Figure 2, in an off-center frequency. Figure 13, however, shows that, when the signal is reduced to 40dB, the noise spectrum now decreases to approximately 15dB, in contrast to Figure 4, which did not use the frequency offset in accordance with the present invention. Figures 14 and 15 show the quantization noise in band for the complete signal and the reduced signal of 40dB respectively, having subtracted the desired signal to unmask the residual noise. The noise spectrum is confirmed to decrease toward a frequency of zero and that is less than 10-15dB using a voice pause of -40dB (Figure 15) compared to full speech activity (Figure 14). Figures 16"and 17 show respectively the signal spectrum plus noise and residual noise during a -40db pause of speech using 6-bit phase quantization and deliberate frequency de-centering in accordance with an exemplary embodiment of the present invention. Residual noise expressed as a frequency deviation of band RMS is, in Figure 17, of about 10 Hz, ie, similar to that obtained with 8-bit quantization without frequency offset (see Figures 2, 3). In terms of operation A to D, exemplary techniques in accordance with the present invention using 6-bit phase quantization achieve a dynamic scale of 100000 units (deviation of +/- 50KHz or more) with a quantization noise of 10 RMS units , that is, -80dB in relation to the entire dynamic scale.A conventional A to D converter would require 11.5-bit precision to achieve the same operation, or 9-bits for perform the same operation using the same oversampling factor. An alternative method for converting phase samples and frequency samples according to the present invention is to employ a digital phase locked circuit as described in U.S. Patent No. 5,084,669 which was incorporated by reference herein. Figure 18 shows an exemplary form of digital PLL adapted for the present invention. In it, a current of the digitized phase samples PHI1, PHI2, PHI3 .... PHIi ... is input to a phase comparator 100. This comparator subtracts an expected phase THETAi of real phase PHII to obtain the error Ei between the calculated phase and the real phase. THETAi phase calculation is calculated by combining an updated phase value previously delayed through the delay register 101 with a delayed prior frequency calculation through the delay register 105 in order to produce the new phase of the old phase by linear extrapolation using the frequency as the inclination. Both the frequency and the phase are then updated by adding a ^ BETA fraction in the phase error to the previous frequency calculation and an ALFA fraction of the phase error to the previous phase calculation. 20 ALPHA and BETA determine the characteristics of the blocked digital phase circuit of the second order constructed in this way. It is also possible to build higher order circuits using for example a calculation of the rate of change of the frequency that is would update using a GAMMA coefficient.

Figure 19 shows the residual noise spectrum of the frequency calculations formed by an exemplary digital PLL having coefficients ALFA = 0.5, BETA = 1/32. ALPHA and BETA, for example, can be selected to be inverse powers of two so that multiplication can be done by a single displacement. Comparing the noise spectrum of Figure 19 with that of Figure 17, it will be seen that there is little difference within the audio scale from zero to 3.4 KHz, since the circuit does not attenuate the components within this scale. However, a reduction in the density of the quantization noise is evident at +/- 15KHz, since the circuit has some attenuation at these frequencies. To demonstrate the use that a deliberate frequency offset is also valuable in the context of a PLL FM digital demodulator, Figure 20 shows the residual quantization noise from the FM PLL demodulator with the frequency offset off. It can be seen that the quantization noise within 0-3.4 KHz is 10 dB or larger, confirming that the benefit of the frequency offset is inddent of the type of FM demodulator used. Figures 21, 22 and 23 are provided to show how the ALFA and BETA coefficients can be selected. Figures 21 to 23 provide the attenuation of the circuit from the frequency to the input to the output frequency, as a function of the modulation frequency for ALFA values of 1, 0.5 and 0.25 BETA values of 1 to 1/64. The circuit attenuation characteristics should be essentially flat from 0 to 3.4KHz and not exhibit excessive peaks at any frequency, which is a sign of impending instability. Another function of this circuit is that it will follow the maximum rate of frequency change. This occurs when the modulation of speech is the highest. The simulations showed the circuit with ALFA = 1/2, BETA == 1/32 follows the modulation of the speech when the deviation of RMS is 16.67KHz, but it stops following a deviation of 33.33KHz RMS. It can be seen from Figure 22 that the frequency response is from about 3dB down to 3.4KHz with BETA = l / 32. Raising the BETA value to 1/16 with ALFA = 0.5 provides a circuit that is almost flat up to 3.4KHz and the circuit confirmed to follow the 33.33KHz RMS deviation with these parameters. From Figure 21, the ALFA = 0.25, BETA = 1/16 values are also suggested and the circuit also follows the 33.333KHz deviation with those parameters. The audio SNR with 6-bit phase quantization and decentered frequency of 20625Hz was calculated and yielded the following figures: DEVIATION OF RMS AUDIO SNR DEVIATION OF EQUIVALENT NOISE 33. 33 KHz 63.8dB 22 Hz 16. 67 KHz 56.5dB 25 Hz RMS 1. 667 KHz 46.6dB 8.8 Hz RMS 167 Hz 25.2dB 9 Hz RMS The aforementioned results show that the speech digitization systems according to the present invention using frequency modulation possess some of the desirable characteristics of a method whereby the quantization noise for small signals is less than the quantization noise for signals big. The noise of quantification in silent periods or pauses of speech is therefore reduced by improving the subjective audio quality. The aforementioned results can be compared against a typical dynamic scale specification for a wireless telephone application. This dynamic scale specification is expressed in the diagram of Figure 24. In the same, level 'A' indicates the RMS level of normal speech. The dynamic scale will be designed to accommodate loudspeakers that speak at an average level! B 'which is 15 dB higher than the' A 'level of normal speech. In addition, the loudspeaker crests of the highest loudspeaker are accommodated without distortion. This is usually taken as implying in these types of specifications that the 3-sigma limit of a supposed Gaussian amplitude probability distribution will be accommodated or that a crest factor of + 10dB will be used. This results in the level represented by 'C in Figure 24. The exemplary system will also fill a minimum signal-to-noise ratio for the quieter loudspeaker. The quieter loudspeaker may be characterized as speaking at a level that is 15 dB lower than a normal loudspeaker, namely, at the 'D' level. The signal-to-noise ratio, however, is usually defined with a sine-wave test tone that has the same peak level as the maximum speech level, that is, at the peak level 'E1 and not the MSY level' D1 of the quieter loudspeaker. The test-to-noise ratio (TTNR) will be 50dB when defined in this way. In addition, noise can be defined as residual noise when the test tone signal is ß disconnected, ie noise during periods of silence. Taking into account that the RMS value of the energy of the desired sine wave test tone is 3dB lower than its peak value, this means that the floor of the noise will be at 53dB below the EX level. Comparing the level 'F' of the noise floor with the highest peak c-level 'C' suggests that the total dynamic scale required for a wireless communication application ^^ 10 typical is 83dB. Attributing the maximum deviation that can be handled using a 240KHz phase sampling regime without exceeding a Pi phase change between the C-level samples (ie 120KHz) then the noise floor should be 83dB less than this, that is, 8.4Hz RMS. The aforementioned exemplary simulations of signal to ^ noise shows a 9Hz noise floor with 6-bit phase quantization that is close enough to be considered to fill the specification. However, it is It is of interest to find ways to further reduce the floor of quantization noise in order to provide some room for implementation. Exemplary techniques for reducing the noise floor could include any or all of the following: use of pre-emphasis, increase of number of bits used in phase quantization, increase the frequency deviation and increase the phase sampling rate. Each of these methods will be considered in turn. Pre-emphasis is a well-known technique in conventional FM radio systems to improve speech quality. With reference to the fact that most of the quantization noise energy occurs at the upper end of the audio frequency band, the frequency deviation produced by higher audio frequencies is increased in the modulator and the output of the demodulator is it reduces correspondingly to those frequencies, attenuating in this way the components of the dominant noise. Microphones are typically designed to produce a flat frequency response from the input of the sound pressure wave to the output of the electrical signal. Therefore, the use of pre-emphasis requires that frequency response settings be entered between the microphone output and the input to the frequency modulator. This frequency response configuration produces amplification of the high frequency components and therefore possibly requires an active circuit. One object of the present invention, however, is to facilitate the integration of the entire active circuit in an integrated circuit. Therefore, one solution may be to design the acoustic (ie, mechanical) components of the microphone such as its diaphragm and the surrounding cavities to effect an acoustic pre-emphasis. Alternatively, the pre-emphasis circuit would preferably be integrated into an integrated circuit with external connections to the microphone. The signals from the microphone would therefore admit into the integrated circuit at a low level before the amplification at which point they would be susceptible to pick up of noise. This form of pre-emphasis, therefore, is not the preferred solution even when those skilled in the art will recognize when design changes will make this an acceptable solution. A preferred form of pre-emphasis would be to use a microphone with a naturally rising frequency response that produces larger electrical inputs for the same level of sound pressure vibration at higher frequencies. These specially made microphones, however, will generally not be available so that other described methods can be employed to obtain improved speech quality (e.g. using one or more phase precision bits), along with any available microphone. One method to improve voice quality is to increase the number of bits used to represent the quantized phase. Each extra bit of phase quantization accuracy provides an improvement of 6dB of audio quality. Increasing the phase quantization accuracy is equal to synchronization transitions of the FM carrier signal to finer time accuracy. This can be done using a higher clock frequency as the reference for the phase digitizer, or synchronization transitions to a fraction of a clock cycle. For example, a sawtooth clock waveform can be generated with a linear ramp with a repetitive zero reset. The ramp can be sampled when the transitions of the FM carrier signal occur to determine its amplitude, thus quantifying the transition time up to a fraction of a clock cycle. Other related methods may include the generation of sinewave and cosine clock waveforms that are sampled at the occurrence of a transition, the fractional phase value being then provided by the arc tangent of the sinusoidal / cosine sample ratio. These methods involve analog circuit concepts that are not especially desirable for integration into a digital integrated circuit. A more appropriate method for integration is to calculate the average phase through more than one transition that occurs between the instants of phase sampling. For example, if the phase is to be sampled at 240K samples / S and the frequency of the FM carrier is nominally 1MHz, there will be at least three transitions going to the positive state and at least three transitions going to the negative state of the carrier within each 240KHz period. Both transitions to the negative state and to the positive state can be used if the phase samples produced by the first are connected for a phase difference of 180 degrees between half cycles. Care must be taken when averaging angle measurements since the correct average of -179 and +179 degrees is 180 degrees and not zero. The best method theoretically to average angles is to average their cosines and their sinusoids separately and calculate the 7ARCTAN of the result. This technique is known as circular averaging. The above-mentioned digital phase locked circuit (PLL) provides a simpler practical method for averaging phase measurements from a large number of signal transitions. In addition, the phase digitizer (not shown) preceding the digital PLL of Figure 18 can be eliminated and the phase digitization carried out by the PLL itself. This reduction is possible due to the application of PLL for the digitization of the invention of an audio signal that involves digital FM demodulation in the absence of radio noise. An exemplary PLL system is shown in Figure 25. The FM input signal is applied to the transition detector 110. When the transitions of the input signal from a previous logical '0' level that has not been stored in the flip-flop circuit 111 to a logical level '1', then the Q output of the flip-flop 111 will be a '1' and the inputs of gate circuit 112 NAND of two ^^ 10 inputs will be satisfied, applying a logical '0' to the input D of the flip-flop 113. This input will be recorded in the flip-flop 113 upon the occurrence of a reference clock pulse resulting in a shore that rises at the exit of Q of 113 and a shore that falls in the output of Q. A binary logic '1' circuit in the Q output operates the gate circuit • 127 to allow the contents of the phase accumulator 120 to appear at the output of the gate circuit 127 as long as the control input is a logical '1'.

This value is multiplied by ALPHA in the multiplier 125 and subtracted from the PH1 phase value received from the accumulator 120 in the subtraction device 122. This occurs for a single reference clock cycle, because after the transition of the entrance of the In the case of a FM signal, the Q output of the flip-flop circuit 113 will return to logic '0' causing the flB circuit gate 127 to resume the output of the zero value. The value ALFA.E would therefore be added to the phase accumulator 120 only once, while the frequency value 5 of? it is added during each reference clock pulse. Even when the gate circuit 127 is passing the value of the phase accumulator, it is also multiplied by BETA in the multiplier 126 and subtracted from the previous value of? on the subtraction device 124. The new The value is then recorded in the integrating register 123 on the raised edge of the Q output of the flip-flop 113, coincident with the gate circuit 127 which is returned to the zero-out condition. The BETA.E decreased to the previous value of? therefore it is permanent. The modified value of? permanently affects the regime to which the phase accumulator 120 is increased, that is, it affects the phase derivative, while the ALFA.E value affects the phase only once, permanently affecting the phase value but not its derivative. In this way, the coefficients ALPHA and BETA can be selected to form a second order digital phase blocking circuit with the desired characteristics as above. ALPHA and BETA are preferably selected to be inverse powers of so that the multiplication is reduced to a displacement.

The ALFA and BETA values are analogous to those of the previous M discussion in the digital PLL design, except that the BETA value is decreased because the value of the phase derivative? Phase accumulator 120 is added many times between each repetition. The number of additions is equal to the number of reference clock pulse periods in a nominal period of the FM input signal. For example, suppose that the frequency of the FM input signal is 620KHz and the clock of ^ 10 reference is 19.2MHz. On average, the value? it is added to the phase accumulator 19200/620 = 31 times to approximately per cycle of the FM input. The BETA value therefore must be about 1/32 of the values indicated in Figures 21 to 23 for this PLL copy. In addition, the frequency response characteristics of the circuit will exhibit a wider bandwidth in proportion to the increased refresh rate that is now equal to the FM input frequency, eg, 620KHz instead of 240KHz. In this way the lower values of ALPHA and BETA should be used to maintain frequency responses of similar circuits. Since the frequency value? will be sampled by a lower frequency sampling clock using the sampling device 130, it is desirable that the frequency characteristics of the circuit attenuate frequencies above half the final sampling rate in order to avoid the phenomenon of staggered. Figure 21 can be used to find the appropriate ALPHA and BETA values as follows: The circuit update rate (e.g. 620 KHz) is 620/240 times that used to produce Figure 21, so that the horizontal frequency scale is graduated accordingly. The values ALFA = 0.25, BETA = l / 32 produced a flat bandwidth up to approximately 4KHz before, and therefore, would be flat at 4KHz x 620/240 = 10.33KHz with a higher update rate. The circuit previously exhibited 30dB of attenuation at approximately 45KHz. Therefore, 30dB of attenuation at 45KHz x 620/240 will occur, which is less than half the sampling rate of 240KHz displayed for the sampling device 130. The circuit must therefore provide adequate attenuation of the stepped components without filtration. extra digital before sampling. The exemplary values of ALPHA and BETA suggested for the arrangement of Figure 25 are therefore ALPHA = 0.25, BETA = 1/1024, with the reduction of BETA 32: 1 due to the reasons discussed above. The value of ? retained in the flip-flop 123 of Figure 25 represents the frequency of the input signal carrier COQ plus the instantaneous frequency deviation d? due to audio modulation. Only the latter is of interest so that the average frequency COQ must be removed before sampling. In Figure 25 this is achieved by the subtraction device 5 131. The subtracted average frequency can be calculated by subsequent digital signal processing and fed again so that no specific circuit is shown in Figure 25 to calculate the average frequency. In other exemplary embodiments, a provision may be desirable to adjust the initial contents of the jog circuit 123 to the expected average frequency in order to avoid the delay in the initial acquisition of the phase lock. This can be achieved at the same time that the average frequency is subtracted by the rearrangement of Figure 26. In Figure 26, the circuit ^ frequency jogger 123 retains the frequency deviation d? from the average frequency. Instead of the subtraction device 131 of FIG. 25, the summing device 132 of FIG. 26 is provided. The summing device 132 adds the average frequency COQ to obtain the rate of increase? =? G + d? of the phase accumulator. This average frequency is envisioned to be adjusted by feedback from the additional method, and thus achieves both the function of adjusting the initial frequency and the elimination of the average frequency from the sampled output of the sampling device 130. Figure 27 illustrates Exemplary word lengths of the various digital quantities in Figure 26. The phase accumulator 120 is shown as the 21 bit A register, along with the meaning of phase and frequency of its bits. The meaning of frequency is applied when the indicated bit is added to a 19.2 MHz rate. For example, if the meaning 11 is added repetitively, the phase accumulator will execute the sequence 10000 ..., 00000 ..., 10000 ..., which represents the sequence of phase 0, Pi, 0, Pi .... This produces a complete cycle every two reference clock periods, that is, 9.6 Megacycles per second. Each successive bit has half the meaning of frequency and the smallest bit has approximately a meaning of 9Hz (9.6MHz / 2 ** 20). The increase with required to produce a nominal frequency of 620.625KHz is shown in register B of Figure 27. The four most significant bits of the increment are zero as well as the least significant bit, therefore 16 bits are enough to define cog. • The frequency deviation d? around with is presented by the C register. If the frequency deviation is within +/- 150KHz, it can be represented by a 16-bit value. The most significant bit (ie, the accumulator bit of 150KHz) is considered as the sign and is an extended sign to be added to the phase accumulator 120. The value d? The instantaneous frequency deviation is updated by subtracting 1/1024 from the value of the phase 5 accumulator at the moment when the input signal undergoes a positive transition. The register D shows the value of the accumulator moved again by means of 10 binary places that represent the deviation by means of 1024. The remaining twelve bits are of a sign extended to 16 bits in the Registry ^^% 10 D to be added to the 16-bit C value dw. Finally, the register E shows the accumulator multiplied by ALPHA (e.g., 0.25) which is a shift to the left of two bits. In Figure 26, the phase value of the accumulator is tested with each input signal transition from low to high, at a rate greater than 470KHz so that the frequency deviation is never greater than 150KHz. If the phase change between the samples to the absolute maximum will never be greater than + / PÍ, a deviation of peak frequency of 235KHz. In fact, in accordance with this exemplary embodiment, the frequency can be shifted by no more than +/- 150KHz, which is still an increase in the exemplary system of Figures 2 to 24 which restricts the frequency deviation to approximately lOOKHz. The The normal audio deviation can therefore be increased by approximately 3dB compared to the eM¡ values considered above, providing an improvement in the dynamic scale of 3dB. On the other hand, the input signal transitions were seen earlier as having been quantified up to half cycle of the 19.2 MHz reference clock providing a 6-bit phase quantization. The transitions are quantized in the systems of Figures 25 and 26 up to a cycle of the reference clock, reducing the precision of quantification of ^ P 10 phase equivalent to 5-bits, a loss of 6dB. However, this is compensated for by the increase in the sampling rate from 240KHz to approximately 600KHz, as the quantizing noise power within the 3.4KHz audio scale is reduced with the cube of the sampling regime (9dB for 2: 1). The provision of Figures 25 to 27 are therefore expected to show ß at least a net reduction of 6dB of quantization noise after descending sampling of the frequency output words to 8K samples per seconds. The methods for converting an acoustic pressure wave into a frequency or phase modulated electrical signal may include the use of a capacitor microphone, which is part of the resonant circuit of an oscillator; a variable inductance microphone that is part of an oscillator circuit; a piezoelectric crystal or air electret microphone connected to one or more variable capacitance diodes that are part of an oscillator circuit, or any microphone that produces a voltage or current signal that controls a voltage or current controlled oscillator. Figure 28 (a) illustrates a conventional microphone arrangement. The conventional arrangement includes the microphone 210 containing the piezoelectric transducer 208, the high-value resistor 207 and the FET preamplifier 206. The FET preamplifier commonly has an open collector output that is used both to apply polarization to FET and to obtain the audio output, thus remaining the microphone as a two-terminal component. The polarization is applied from the low noise bias voltage source 201 through the resistor 205 through which the current flows through the FET that develops the audio signal. The direct current voltage level at the output is arbitrary and is removed by the blocking capacitor 204 before further amplification at the microphone amplifier 202. A disadvantage of this conventional arrangement is the need for an exceptionally low noise biasing supply 201. Typically, the normal RMS speech signal of the microphone corresponding to level A of Figure 24 is of RMS of 5 mV. The noise floor is required to be 58dB lower than this level, that is, 5μV. The conventional circuit of Figure 28 (a), however, is very susceptible to the noise of this polarization supply as well as to the pickup of noise in the signal of the resistor 205 through the capacitor 204 and the resistor 203 to the amplifier 202 of the microphone. An exemplary microphone arrangement that overcomes these disadvantages in accordance with the present invention is shown in Figure 28 (b). In it, the microphone 220 now incorporates the piezoelectric element and resistor 207 as before but lacks the FET preamplifier 206. Therefore, a polarization supply current is not necessary. Instead, the output voltage 208 of the piezoelectric element (electret) varies the capacitance of the diodes 211 and 212 varactors which, with the inductor 213, form the resonant circuit for the oscillator 230. The oscillator is preferably a relatively low level oscillator but does not apply sufficient alternating current voltage oscillation to the varactor diodes 211 and 212 so that they can be driven towards the forward driving. It is preferred to operate the diodes 211 and 212 varactors with a reverse polarity of zero voltage to avoid the need to generate a low noise bias voltage also in order to maximize the frequency-modulation sensitivity of the oscillator. A ground line from a central branch in inductor 213 (illustrated by a dotted line in Figure 28 (b)) is suggested to ensure that low frequency (audio) noise pickup can not occur in the lines between the varactors 211 and 212 and the inductor 213. The low level oscillation produced by the oscillator 230 may, however, be lOOmV or more since the varactor diodes will not be driven forward until they reach 300-400mV. The oscillator signal is therefore 20 times higher than the microphone signal of the conventional microphone circuit arrangement of Figure 28 (a), and it is also a high frequency FM signal that is relatively immune to interference pickup. In this way, the system of the invention provides both circuit simplification by eliminating the polarization supply 201 and the microphone amplifier 202 as greatly reduced susceptibility to noise pickup. Alternatively, a circuit using a current-controlled oscillator can be used as an example of which is shown in Figure 29. A known form of the current-controlled oscillator is the multivibrator coupled to the emitter or its FET equivalent, the multivibrator coupled with the source, which is shown in Figure 29. The microphone 210 now includes an electret element 208 and two identical FET transconductance amplifiers 206a and 206b that convert the electret audio voltage into a pair of audio current sources of magnitude I. These currents form the tail currents of the N-type FETs 241 and 242 which are transversely coupled from the consumption to the gate and are coupled to the source by the synchronization capacitor C 240. It can be shown that the circuit will oscillate with approximately the indicated source waveforms and with a frequency that is proportional to the current I. As long as the FETs 206a and 206b are good f Current sources, the audio stream I and therefore the frequency modulation will not be strongly dependent on the supply voltage Vcc in this way a measure of the noise immunity of the supply voltage is obtained. It may be desirable, in order to obtain sufficiently high frequency deviation with any of the methods described above, to use a high frequency frequency modulated oscillator which is then mixed to the desired 620KHz scale. Producing a peak deviation, for example, of +/- 150KHz from a 620KHz oscillator could be otherwise difficult since this is a high percentage change. On the other hand, producing a peak deviation of +/- 150KHZ from an 18.6MHz oscillator, which is then mixed with the 600KHz scale against a reference oscillator 5 of 19.2MHz, is more straightforward. An appropriate mixing arrangement can be formed using digital logic components as shown in Figure 30. In them, the FM input signal to nominally 18.6MHz is applied to input D of the ^ M 10 rocker circuits 400 and 401 for shore firing. The flip-flop circuit 400 is synchronized by the 19.2MHz reference clock and the flip-flop 401 by the inverted clock. The tilting circuits produce square wave outputs at the 600KHz difference frequency which are relatively inverted. The relative inversion is rectified using a Q output of the dump circuit 400 and < In addition, the 600KHz output of the flipper 400 has transitions that are synchronized up to the lifting edges of the 19.2MHz clock while the output of the flipper circuit 401 is synchronized up to the drop edges. Between the two, the transitions of the 600KHz difference frequency are thus conserved up to a half-cycle accuracy of the reference clock, which is used to obtain 6-bit phase quantization.

The 19.2MHz clock also drives the division circuit 402 between reference 32. The output of circuit 402 increases the elevated edges of the clock and is stable during the falling edge of the clock. The output of the circuit 402 is also synchronized back to the edges that fall from the clock by the latch 405. Therefore, the count sequence produced by the circuit 402 and the latch 405 is for example: Circuit 402: ... 25 26 27 28 29 30 31 0 1 2 Hasp 405: 25 26 27 28 29 30 31 0 1 2 Now, depending on the transition timing of the FM input signal of 18.6MHz, a rising edge on the output of 600KHz Q of the jogger 400 can occur halfway through the cycle of the reference clock before a shore rising at the exit Q of the tilter circuit 401 or vice versa. If the former occurs, for example, in account 27 outside the counter 402, the contents of bolt 405 at that time will be 26, whose number will be latched onto bolt 404. Then, the output of flipper circuit 401 will occur on the account 27 of bolt 405, at which point circuit 402 still contains 27, whose number will be latched onto bolt 403. The sum of the locks 403 and 404 produced by the adder 406 will then be the 6-bit number 26 + 27 = 53.

If, on the other hand, the transitions on the output Q of the flip-flop 401 occur in the half clock cycle before the Q output of 400 to the value 26 outside the lock 405, then the circuit 402 during that time contains the value 26, Then, when the transition occurs at the output Q of the dump circuit 400 during the count 27 of the circuit 402, the bolt 405 still contains 26, whose value is latched on the bolt 404. sum produced by adder 406 in this case is 26 + 26 = 52, reflecting that the transition from the 18.6 MHz input to the previous half cycle has occurred. In this way, the summation output of the adder 406 represents the phase of the signal at the half-cycle synchronization accuracy of the reference clock. The 6-bit phase sequences are applied to a digital PLL 407 according to Figure 18 together with a clock derived from the Q output of the jog circuit 401, thus ensuring that the phase values are used only long after that the output of the adder 406 has become stable. The ALP, BETA values of PLL 407 are selected to provide the desired frequency response with the clock rate of 600KHz, as described above. The increased clock rate of 600KHz compared to the 240KHz value discussed in detail above provides at least a 9dB reduction in quantization noise. The frequency calculations calculated and filtered by the PLL are then sampled down to 240KHz by the output of the division circuit 408 between 80. This is synchronized by the edges that are raised from the reference clock while PLL 407 updates its values of synchronous way with the falling edges, thus ensuring that down sampling occurs after the updated frequency values have become stable. The frequency values of the 240K / S samples can then be further down-sampled up to 8KHz using known down-sampling sampling techniques. A number of variations of the invention have been disclosed from which derivatives can be interpreted by those skilled in the art while still adhering to the scope and spirit of the invention as described by the following claims.

Claims (35)

CLAIMS:

1. A method for digitizing an audio signal comprising the steps of: modulating an oscillator in frequency with the audio signal; apply the signal of the frequency modulated oscillator to a digital frequency discriminator that calculates a sequence of instantaneous ^ M 10 frequency values; and use the instantaneous frequency values as the digitized audio signal.

2. A method to digitize an audio signal to produce a sequence of numerical values 15 representative during the desired sampling times comprising the steps of: < flp modulate an oscillator frequency with an audio signal; combining the signal of the frequency modulated oscillator with a reference frequency clock to produce a sequence of instantaneous phase values of the oscillator signal; and numerically calculating a rate of change of the instantaneous phase values during the desired sampling instants and using the calculated regime of values of change as the representative numerical values.

3. A method for digitizing an audio signal according to claim 1, wherein the digital frequency discriminator is a digital phase blocking circuit.

4. A method for digitizing an audio signal according to claim 2, wherein the calculation of the phase change rate is carried out using a digital phase lock circuit.

A method for digitizing an audio signal according to claim 2, wherein the calculation of the phase change rate is carried out by different successive phase values.

6. A method for producing a sampled digital representation of an acoustic pressure wave comprising the steps of: converting the acoustic pressure wave into corresponding variations in electrical capacitance; using the variations in electrical capacitance to produce corresponding variations in a frequency of an electric oscillator signal; applying the signal of the frequency-modulated oscillator to a digital frequency discriminator that calculates a sequence of instantaneous frequency values; and use the instantaneous frequency values as the digitized audio signal.

7. A method for producing a sampled digital representation of an acoustic pressure wave comprising the steps of: converting the acoustic pressure wave into corresponding variations in electrical capacitance; using the variations in electrical capacitance to produce corresponding variations in a frequency of an electric oscillator signal; combining the frequency modulated oscillator signal with a reference frequency clock to produce a sequence of instantaneous phase values of the oscillator signal; and numerically calculating a rate of change of the instantaneous phase values during the desired sampling instants and using the calculated regime of values of change as the representative numerical values.

8. A method for digitizing an audio signal according to claim 7, wherein the digital frequency discriminator is a digital phase lock circuit.

9. A method for digitizing an audio signal according to claim 6, wherein the calculation of the phase change rate is carried out using a digital phase lock circuit.

A method for digitizing an audio signal according to claim 6, wherein the calculation of the phase change rate is carried out by different successive phase values.

11. A method according to claim 6 wherein variations in electrical capacitance are produced using a capacitance microphone.

12. A method according to claim 7, wherein variations in electrical capacitance are produced using a capacitance microphone.

13. A method according to claim 6, wherein variations in electrical capacitance are produced using a piezoelectric microphone and a variable capacitance diode.

A method according to claim 7, wherein variations in electrical capacitance are produced using a piezoelectric microphone and a variable capacitance diode.

15. A method according to claim 1, wherein the center frequency of the oscillator is offset from the center frequency of the digital discriminator by more than one higher audio frequency.

16. A method according to claim 2, wherein the center frequency of the oscillator is centered on a submultiple of the reference clock frequency by more than one higher audio frequency.

17. An analog to digital converter for producing a sequence of numerical sample values representative of a signal waveform comprising: an oscillating means for producing a high frequency signal; frequency / phase modulation means that the changes are of the frequency and phase angle of the high frequency signal to correspond to the waveform of the signal; a digital frequency discriminator means to determine the numerical values for the frequency of the instantaneous signal of the oscillator at determined sampling instants; the digital frequency discriminator means P-} determine the numerical values for the instantaneous signal frequency of the oscillator during determined sampling instants; and 5 the output means is to output the numerical values as the representative numerical sample values.

18. An analog-to-digital converter according to claim 17, further comprising: a downstream sampling means for filtering the numerical and instantaneous frequency values in order to produce filtered samples at a reduced sample rate.

19. An analog-to-digital converter for producing a sequence of numerical sample values at a first sampling rate representative of a signal waveform comprising: an oscillating means for producing a high-frequency signal; frequency / phase modulation means changing the frequency or phase angle of the high frequency signal to correspond to the waveform of the signal; Direct phase digitization means combining the oscillator signal into a reference frequency clock signal in order to generate numerical values representative of the instantaneous phase during the second sampling rate; and processing means processing the phase samples during the second sampling rate in order to generate the signal waveform representative of the samples of the first sampling regime.

20. An analog-to-digital converter according to claim 19, wherein the processing means reduces the quantization noise by digital low-weight filtering.

21. A digital analog converter according to claim 19, wherein the processing means includes a digital phase lock circuit.

22. A microphone circuit with immunity to pickup of electrical noise to produce a numerical sample stream representative of a sound depression wave comprising: a transducer means for converting the sound pressure wave variations into corresponding variations in a electrical parameter; an oscillating means for producing an oscillator signal having a frequency that depends on the electrical parameter; a digital frequency discriminator means 5 determining the numerical values for the frequency of the instantaneous signal of the oscillator during determined sampling instants; and an output means for outputting the numerical values as the representative sample stream 10.

23. A microphone circuit with immunity to pick up electrical noise to produce a numerical sample stream during a first sample rate representative of a sound pressure wave that 15 comprises: a transducer means for converting the variations of the sound pressure wave into corresponding variations in an electrical parameter; an oscillator means for producing a signal of the oscillator having a frequency that depends on the electrical parameter; a direct phase fingering means for combining the oscillator signal with a reference frequency clock signal in order to generate numerical values representative of the instantaneous phase during a second bB sampling rate; and a processing means for processing the numerical values at the second sampling rate in order to generate the numerical sample stream during the first sampling regime.

24. A microphone circuit according to claim 23, wherein the processing means reduces the quantization noise by filtering ^ M 10 digital low pass.

25. A microphone circuit according to claim 23, wherein the processing means includes a digital phase lock circuit.

26. A microphone circuit according to claim 22, wherein the transducer means a piezoelectric transducer.

27. A microphone circuit according to claim 22, wherein the electrical parameter is the capacitance.

28. A microphone circuit according to claim 23, wherein the transducer means is a piezoelectric transducer.

29. A microphone circuit according to claim 23, wherein the electrical parameter is the 25 capacitance.

30. A microphone with immunity to the pickup of electrical noise comprising: a ground terminal and a signal terminal; a piezoelectric transducer for converting the sound pressure waves into a corresponding electrical voltage signal between a first and a second terminal, the second terminal being connected to the ground terminal; an electrical resistance connected between the first and second terminals of the transducer; and a varactor diode has a terminal connected to the first terminal of the transducer and its other terminal connected to the terminal of the signal.

31. A microphone with immunity to the pickup of electrical noise comprising: a ground terminal and a first and second signal terminals; a piezoelectric transducer for converting the sound pressure waves into a corresponding electrical voltage signal between the first and second terminals, the second terminal being connected to the ground terminal; an electrical resistance connected between the first and second terminals of the transducer; a first varactor diode having an anode connected to the first transducer terminal and a cathode connected to the first signal terminal; and a second varactor diode having an anode connected to the first transducer terminal and a cathode connected to the first signal terminal.

32. A microphone according to claim 31, further comprising: an inductance connected to the first and second signal terminals and forming part of an oscillator circuit.

33. A microphone with immunity to the pickup of electrical noise comprising: a ground terminal and a first and second output terminals; a piezoelectric transducer for converting the sound pressure waves into a corresponding electrical voltage signal between the first and second terminals, the second terminal being connected to the ground terminal; an electrical resistance connected between the first and second terminals of the transducer; a first field effect transistor having a gate electrode connected to the first terminal of the transducer, a source electrode connected to the ground terminal and a consumption electrode connected to the first output terminal; and a second field effect transistor having a gate electrode connected to the first terminal of the transducer, a source electrode connected to the ground terminal and a consumption electrode connected to the second output terminal.

34. A microphone according to claim 33, further comprising: a current controlled oscillating means connected to the first and second output terminals to produce a frequency modulated oscillation signal.

35. A microphone circuit with immunity to pick up electrical noise to produce a numerical sample stream at a first sample rate representative of a sound pressure wave comprising: a transducer means for converting the pressure wave variations of sound in variations in an electrical parameter; an oscillating means for producing an oscillator signal having a frequency that depends on the electrical parameter; a digital mixing means for combining the oscillator signal with a reference frequency clock signal in order to produce at least one different frequency signal; a direct phase digitizing means for combining at least one different frequency signal with a reference frequency clock signal for generating numerical values representative of the instantaneous phase during a second sampling rate; and a processing means for processing the numerical values at the second sampling rate to generate the numerical sample stream at the first sampling rate. SUMMARY OF THE INVENTION In accordance with exemplary embodiments, a voltage or current controlled oscillator is frequency controlled by the signal (i.e., voltage or current) from a microphone. The frequency-modulated signal is applied to a direct digital discriminator that produces a digital representation of the instantaneous frequency at the desired speech sampling rate. The digital discriminator can be formed, for example, by applying the oscillator signal as a direct phase digitization circuit together with a reference frequency and calculating the instantaneous phase sequence of the oscillator relative to the reference frequency. The phase sequence is then applied to a digital phase locked circuit (or differently numerically differentiated) to generate a sequence of binary words representative of the instantaneous frequency and therefore representative of the speech waveform. Since the low-level speech waveform does not essentially support the integrated circuit except as a high-level frequency-modulated carrier, the technique is immune to noise caused by random-rate logic circuits - such as microprocessors and DSPs that they work in the integrated circuit.