KR100477940B1 - Method for forming shallow junction of semiconductor device - Google Patents
Method for forming shallow junction of semiconductor device Download PDFInfo
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- KR100477940B1 KR100477940B1 KR10-2002-0045025A KR20020045025A KR100477940B1 KR 100477940 B1 KR100477940 B1 KR 100477940B1 KR 20020045025 A KR20020045025 A KR 20020045025A KR 100477940 B1 KR100477940 B1 KR 100477940B1
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 73
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 37
- 229910052796 boron Inorganic materials 0.000 claims abstract description 25
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 22
- 238000002347 injection Methods 0.000 claims abstract description 21
- 239000007924 injection Substances 0.000 claims abstract description 21
- 238000002513 implantation Methods 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims abstract description 14
- 150000002500 ions Chemical class 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 14
- 229910052710 silicon Inorganic materials 0.000 abstract description 14
- 239000010703 silicon Substances 0.000 abstract description 14
- 238000010438 heat treatment Methods 0.000 abstract description 12
- 238000009792 diffusion process Methods 0.000 abstract description 10
- 230000000694 effects Effects 0.000 abstract description 5
- 238000005468 ion implantation Methods 0.000 description 7
- -1 germanium ions Chemical class 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 238000005280 amorphization Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
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Abstract
반도체 소자의 얇은 접합 형성 방법에 관한 것으로, 그 목적은 얇은 접합 두께를 유지하고 기존의 열처리 공정을 적용할 수 있는 얇은 접합을 형성하는 데 있다. 이를 위해 본 발명에서는 반도체 기판 내에 질소를 주입하여 질소주입영역을 형성하는 단계; 질소주입영역 내에 붕소 등의 불순물 이온을 주입하여 불순물주입영역을 형성하되, 불순물주입영역이 질소주입영역보다 얇은 두께가 되도록 형성하는 단계; 및 반도체 기판을 열처리하여 불순물 이온을 확산시키는 단계를 포함하여 얇은 접합을 형성하는 것을 특징으로 하며, 이 때 실리콘웨이퍼 내에 주입된 질소는 붕소의 열확산을 방해하기 때문에 얇은 접합을 쉽게 형성할 수 있을 뿐만 아니라 이후의 각종 열처리 공정에서도 얇은 접합 두께를 유지하는 것이 가능한 효과가 있다.The present invention relates to a method for forming a thin junction of a semiconductor device, and an object thereof is to form a thin junction capable of maintaining a thin junction thickness and applying a conventional heat treatment process. To this end, the present invention comprises the steps of forming a nitrogen injection region by injecting nitrogen into the semiconductor substrate; Implanting an impurity implantation region by implanting impurity ions such as boron into the nitrogen implantation region, wherein the impurity implantation region is formed to be thinner than the nitrogen implantation region; And heat-treating the semiconductor substrate to form impurity ions to form a thin junction, wherein nitrogen implanted into the silicon wafer can easily form a thin junction because it hinders thermal diffusion of boron. In addition, there is an effect that it is possible to maintain a thin junction thickness in various subsequent heat treatment processes.
Description
본 발명은 반도체 소자 제조 방법에 관한 것으로, 더욱 상세하게는 얇은 접합(shallow junction)을 형성하는 방법에 관한 것이다.TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a shallow junction.
반도체 장치가 고집적화 될수록 트랜지스터의 채널길이가 감소되고 이에 따른 단채널효과(short channel effect)로 소자특성의 열화가 발생하므로 이를 방지해야 하며, 또한 펀치쓰루(punch-through)에 대한 마진확보가 필요하게 되었다. 이를 위한 노력 중의 하나가 트랜지스터의 소스/드레인 영역을 접합저항이 낮은 얇은 접합으로 형성하는 것이다. As semiconductor devices become more integrated, the channel length of transistors decreases and device characteristics deteriorate due to a short channel effect. Therefore, it is necessary to secure a margin for punch-through. It became. One effort is to form the source / drain regions of transistors in thin junctions with low junction resistance.
얇은 접합을 형성하기 위한 방법에는 저에너지 이온주입법, 실리콘이나 게르마늄이온을 이용한 선(先)-비정질화 이온주입법(pre-amorphization) 등이 있는데, 가속전압을 10 keV로 사용하는 저에너지 이온주입법은 단채널효과를 줄일 수는 있으나 접합저항을 증가시키는 문제가 있다. 또한, 선-비정질화 이온주입법과 저에너지 이온주입법에서는 주입된 이온에 의해 기판에 점결합이 발생하고, 이온주입 후의 열처리 동안에 불순물의 확산하여 접합이 깊어지는 문제가 있다.The methods for forming thin junctions include low energy ion implantation and pre-amorphization ion implantation using silicon or germanium ions, and low energy ion implantation using an acceleration voltage of 10 keV is a short channel method. Although the effect can be reduced, there is a problem of increasing the junction resistance. In addition, in the pre-amorphous ion implantation method and the low energy ion implantation method, point bonding occurs to the substrate by the implanted ions, and there is a problem that the junction is deepened by diffusion of impurities during the heat treatment after the ion implantation.
종래 붕소(B)를 이온주입하여 p+ 얇은 접합을 형성하는 것은, 붕소의 심한 열확산 특성 때문에 매우 어렵다. 또한, 열처리 공정 중에 붕소가 실리콘웨이퍼의 내부로 확산되어 접합이 두꺼워지는 문제점이 있을 뿐만 아니라, 실리콘웨이퍼의 외부로 역확산(out-diffusion)되어 실리콘웨이퍼의 표면에서 원하는 붕소농도를 유지할 수 없는 문제점이 있다.Conventional implantation of boron (B) to form p + thin junctions is very difficult because of the severe thermal diffusion properties of boron. In addition, boron is diffused into the silicon wafer during the heat treatment process, resulting in a thickening of the junction, and out-diffusion to the outside of the silicon wafer, thereby preventing the desired boron concentration from being maintained on the surface of the silicon wafer. There is this.
이렇게 형성된 얇은 접합은 형성된 이후에도 각종 열처리 공정에서 확산되기가 쉽기 때문에 열처리 온도를 낮추어야 하며 가능하면 열처리 공정을 피해야 하는 어려움이 있었다.Since the thin junction formed is easy to diffuse in various heat treatment processes even after the formation, the heat treatment temperature should be lowered and, if possible, the heat treatment process should be avoided.
본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 얇은 접합 두께를 유지하고 기존의 열처리 공정을 적용할 수 있는 얇은 접합을 형성하는 데 있다.The present invention is to solve the problems as described above, the object is to form a thin joint that can maintain a thin joint thickness and can be applied to the existing heat treatment process.
상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 붕소 이온을 주입하기 전에 실리콘웨이퍼에 질소를 주입하는 것을 특징으로 한다.In order to achieve the object as described above, in the present invention, nitrogen is injected into the silicon wafer before the boron ions are injected.
이 때 실리콘웨이퍼 내에 주입된 질소는 붕소의 열확산을 방해하기 때문에 얇은 접합을 쉽게 형성할 수 있을 뿐만 아니라 이후의 각종 열처리 공정에서도 얇은 접합 두께를 유지하는 것이 가능해진다.At this time, since the nitrogen injected into the silicon wafer prevents boron from thermal diffusion, it is not only possible to form a thin bond easily but also to maintain a thin bond thickness in various subsequent heat treatment processes.
즉, 본 발명에 따른 반도체 소자의 얇은 접합 형성방법은, 반도체 기판 내에 질소를 주입하여 질소주입영역을 형성하는 단계; 질소주입영역 내에 붕소 등의 불순물 이온을 주입하여 불순물주입영역을 형성하되, 불순물주입영역이 질소주입영역보다 얇은 두께가 되도록 형성하는 단계; 및 반도체 기판을 열처리하여 불순물 이온을 확산시키는 단계를 포함하여 이루어진다.That is, the method for forming a thin junction of a semiconductor device according to the present invention comprises the steps of forming a nitrogen injection region by injecting nitrogen into the semiconductor substrate; Implanting an impurity implantation region by implanting impurity ions such as boron into the nitrogen implantation region, wherein the impurity implantation region is formed to be thinner than the nitrogen implantation region; And heat-treating the semiconductor substrate to diffuse the impurity ions.
여기서 질소주입영역을 형성할 때에는, 질소주입영역의 두께가 형성하고자 하는 접합 두께가 되도록 형성하는 것이 바람직하다.When forming the nitrogen injection region, it is preferable that the thickness of the nitrogen injection region is formed so as to be the bonding thickness to be formed.
또한, 질소주입영역을 형성할 때에는, 5~15 keV의 에너지 및 5×1014 ~ 5×1015 개/cm2의 양으로 질소를 주입하는 것이 바람직하다.In addition, when forming the nitrogen injection region, it is preferable to inject nitrogen in an energy of 5 to 15 keV and an amount of 5 x 10 14 to 5 x 10 15 atoms / cm 2 .
이하, 본 발명에 따른 반도체 소자의 얇은 접합 형성 방법에 대해 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming a thin junction of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 1c는 본 발명에 따른 반도체 소자의 얇은 접합 형성 방법을 도시한 단면도이다.1A to 1C are cross-sectional views illustrating a method of forming a thin junction of a semiconductor device according to the present invention.
먼저, 도 1a에 도시한 바와 같이, 실리콘웨이퍼(1)의 소정영역에 로코스 공정이나 트렌치 공정으로 필드 산화막(2)을 형성하여, 실리콘웨이퍼(1)에서 필드 산화막(2)이 형성된 부분을 소자 분리 영역으로, 그 외의 부분을 액티브 영역으로 정의한다.First, as shown in FIG. 1A, the field oxide film 2 is formed in a predetermined region of the silicon wafer 1 by a LOCOS process or a trench process, so that the portion where the field oxide film 2 is formed in the silicon wafer 1 is formed. In the device isolation region, other portions are defined as active regions.
다음, 얇은 접합을 형성하고자 하는 영역의 실리콘웨이퍼(1) 내로 질소 이온을 주입하여 원하는 접합 두께, 일예로 0.1㎛ 정도의 두께를 가지는 질소주입영역(3)을 형성한다. 접합 두께는 주입 에너지에 의해 조절되는데, 바람직하게는 5~15 keV의 에너지로 5×1014 ~ 5×1015 개/cm2의 양을 주입한다. 형성된 질소주입영역(3)은 이후 붕소의 확산방지벽으로 작용한다.Next, nitrogen ions are implanted into the silicon wafer 1 in the region where a thin junction is to be formed to form a nitrogen injection region 3 having a desired junction thickness, for example, a thickness of about 0.1 μm. The junction thickness is controlled by the implantation energy, preferably an amount of 5 × 10 14 to 5 × 10 15 pieces / cm 2 is injected at an energy of 5-15 keV. The formed nitrogen injection region 3 then serves as a diffusion barrier of boron.
다음, 도 1b에 도시된 바와 같이, 질소주입영역(3)이 형성된 실리콘웨이퍼(1) 내에 붕소 이온을 주입하여 붕소주입영역(4)을 형성하되, 그 두께는 질소주입영역(3)의 두께보다 작게 한다.Next, as illustrated in FIG. 1B, boron ions are implanted into the silicon wafer 1 in which the nitrogen injection region 3 is formed to form a boron injection region 4, the thickness of which is the thickness of the nitrogen injection region 3. Make it smaller.
종래 붕소 이온을 주입할 때 종종 발생하였던 채널링(channeling)은 질소 이온 주입 시 실리콘웨이퍼(1)의 표면이 손상되거나 비정질(amorphous)화된 것에 의해 방지되는 장점이 있다.Channeling, which often occurs when the conventional boron ions are implanted, has an advantage that the surface of the silicon wafer 1 is prevented from being damaged or amorphized during the nitrogen ion implantation.
다음, 도 1c에 도시된 바와 같이, 열처리하여 실리콘웨이퍼(1) 내로 주입된 붕소를 열확산시켜 활성화한다. 이 때 앞에서 설명한 바와 같이 질소주입영역(3)이 붕소의 확산방지벽으로 작용하기 때문에, 붕소는 질소주입영역(3)을 벗어나지 않고 질소주입영역(3)까지 확산되며, 따라서 붕소주입영역(4)은 도 1a에서 의도적으로 형성한 질소주입영역(3)과 거의 동일해진다. Next, as shown in FIG. 1C, the boron injected into the silicon wafer 1 by heat treatment is thermally diffused and activated. At this time, since the nitrogen injection region 3 acts as a diffusion barrier of boron as described above, boron diffuses to the nitrogen injection region 3 without leaving the nitrogen injection region 3, and thus the boron injection region 4 ) Is almost the same as the nitrogen injection region 3 intentionally formed in FIG.
이는 종래 붕소의 과도한 확산으로 인해 접합 내에서 붕소의 농도가 목표값보다 낮아지던 것과 비교할 때, 본 발명에 의하면 붕소가 원하는 접합 깊이 내에서 원하는 농도로 골고루 분포한다는 것을 알 수 있다.This indicates that, according to the present invention, the boron is evenly distributed at the desired concentration within the desired junction depth, compared to the conventional concentration of boron in the junction due to excessive diffusion of boron.
상술한 바와 같이, 본 발명에서는 붕소의 확산을 방해하는 질소를 실리콘웨이퍼에 먼저 주입한 다음 붕소를 주입하기 때문에, 붕소가 질소주입영역을 벗어나 확산되는 것이 방지되어 원하는 두께를 가지는 얇은 접합을 용이하게 형성하는 효과가 있다.As described above, in the present invention, since nitrogen that hinders the diffusion of boron is first injected into the silicon wafer and then boron is injected, boron is prevented from diffusing out of the nitrogen injection region, thereby facilitating thin bonding having a desired thickness. It is effective to form.
또한, 질소가 붕소의 확산을 방지하기 때문에 각종 열처리 공정에서 얇은 접합 두께가 유지되는 효과가 있으며, 따라서 기존의 열처리 공정을 적용할 수 있는 효과가 있다.In addition, since nitrogen prevents the diffusion of boron, there is an effect of maintaining a thin junction thickness in various heat treatment processes, and thus there is an effect that can be applied to the existing heat treatment process.
도 1a 내지 도 1c는 본 발명에 따른 반도체 소자의 얇은 접합 형성 방법을 도시한 단면도이다.1A to 1C are cross-sectional views illustrating a method of forming a thin junction of a semiconductor device according to the present invention.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61263274A (en) * | 1985-05-17 | 1986-11-21 | Hitachi Ltd | Manufacture of semiconductor device |
| JPH01309320A (en) * | 1988-06-07 | 1989-12-13 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH0878674A (en) * | 1993-09-16 | 1996-03-22 | Mitsubishi Electric Corp | Semiconductor device and its manufacture and bipolar transistor |
| KR20000004235A (en) * | 1998-06-30 | 2000-01-25 | 김영환 | Method for forming a junction of semiconductor devices |
-
2002
- 2002-07-30 KR KR10-2002-0045025A patent/KR100477940B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61263274A (en) * | 1985-05-17 | 1986-11-21 | Hitachi Ltd | Manufacture of semiconductor device |
| JPH01309320A (en) * | 1988-06-07 | 1989-12-13 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH0878674A (en) * | 1993-09-16 | 1996-03-22 | Mitsubishi Electric Corp | Semiconductor device and its manufacture and bipolar transistor |
| KR20000004235A (en) * | 1998-06-30 | 2000-01-25 | 김영환 | Method for forming a junction of semiconductor devices |
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|---|---|
| KR20040011253A (en) | 2004-02-05 |
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