KR100475456B1 - Method for manufacturing electric wiring of semiconductor device - Google Patents

Abstract

A wiring forming method is disclosed in which poor contact with neighboring contacts is reduced. A first conductive layer is formed on the semiconductor substrate. A hard mask pattern is formed on the first conductive layer. By isotropically etching the first conductive layer by a partial thickness using the hard mask pattern as a mask, the thickness is reduced compared to the first conductive layer and a conductive material protrudes below the hard mask pattern so that a portion of the bottom surface of the hard mask pattern is exposed. A second conductive layer supporting the film is formed. The second conductive layer is anisotropically etched using the hard mask pattern as a mask to form a conductive structure in which a conductive pattern having a relatively reduced upper edge portion and a conductive structure in which the hard mask pattern is stacked are formed. Since the width of the pattern is partially reduced only in the area where the defect is likely to occur, the conductive structure has the effect of reducing the bridge defect while stacking each pattern stably.

Description

Method for manufacturing electric wiring of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming method of a semiconductor device, and more particularly, to a wiring forming method in which contact failure with neighboring contacts is reduced.

As the semiconductor device is highly integrated, each pattern constituting the semiconductor device is further miniaturized, and not only the width of the pattern but also the distance between the pattern and the pattern is reduced. In addition, the contact sizes connecting the isolated devices formed on the semiconductor substrate become smaller and deeper.

As the semiconductor device is highly integrated as described above, an operation speed failure that does not satisfy the operation speed of the semiconductor device due to an increase in resistance due to a decrease in the line width of the wiring, and a bridge failure between the contact and the signal line due to the photo misalignment frequently occur. . In order to minimize such defects, a process of forming a wiring as a metal material having a low resistivity and a process of forming a contact in a self-aligned manner using a surrounding pattern are applied.

1A to 1C, a method of forming a conventional self-aligned contact will be briefly described.

Referring to FIG. 1A, conductive structures 16 including conductive layer patterns 12 and nitride layer patterns 14 are stacked on a semiconductor substrate 10, and then nitride layer spacers 18 are formed on sidewalls of the conductive structures. To form.

Referring to FIG. 1B, an insulating layer 20 is formed by depositing silicon oxide on the entire surface of the resultant product. Subsequently, a photoresist pattern 22 for forming a contact exposing the substrate between the conductive structures 16 is formed.

Referring to FIG. 1C, the conductive structures 16 may be etched using the photoresist pattern 22 as an etch mask, and the insulating layer 20 is etched by an anisotropic etching process using a selectivity ratio between the silicon oxide layer and the silicon nitride layer. A contact hole 24 is formed to expose the substrate region therebetween.

However, as the spacing between the conductive structures 16 becomes narrower, it is increasingly difficult to form the photoresist pattern 22 in place. When the photoresist pattern 22 is not formed at the proper position, one side surface of the nitride film spacer 16 is excessively etched when the anisotropic etching process is performed. At this time, when a part of the conductive layer pattern 12 is exposed on the side of the contact hole 24 (A), a bridge failure occurs between the contact formed by the subsequent process and the conductive patterns 12.

In order to reduce such defects, there is a method of reducing the line width of the conductive structure 16. However, when only the line width of the conductive structure is reduced in the state in which the height of the conductive structure 16 is fixed, the conductive structure may fall or be lifted.

Accordingly, it is a first object of the present invention to provide a wiring forming method in which poor contact with neighboring contacts is reduced.

In order to achieve the above object, the present invention forms a first conductive layer on a semiconductor substrate. A hard mask pattern is formed on the first conductive layer. By isotropically etching the first conductive layer by a partial thickness using the hard mask pattern as a mask, the thickness is reduced compared to the first conductive layer and a conductive material protrudes below the hard mask pattern so that a portion of the bottom surface of the hard mask pattern is exposed. A second conductive layer supporting the film is formed. The second conductive layer is anisotropically etched using the hard mask pattern as a mask to form a conductive structure in which the upper corner portion is relatively reduced in shape and a conductive structure in which the hard mask pattern is stacked to form wiring of the semiconductor device.

In the present invention, after the conductive structure is formed, an insulating layer may be formed to bury the conductive structure, and the contact layer may be further formed between the conductive structures by partially etching the insulating layer.

In order to achieve the above object, the present invention forms conductive structures in which a conductive pattern and a hard mask pattern are stacked on a semiconductor substrate. An insulating layer is formed to bury the conductive structures. The insulating layers between the conductive structures are etched to form contact holes on the side surfaces of the conductive patterns and the hard mask patterns. The exposed conductive pattern is selectively isotropically etched so that the hard mask pattern protrudes more than the conductive pattern exposed on the side surface of the contact hole. Subsequently, insulating film spacers are formed on the side surfaces of the contact holes to form wirings of the semiconductor device.

According to the above-described method, the conductive structure of the semiconductor device is partially reduced in the width of the conductive pattern only in a portion where bridge failure is likely to occur by a subsequent process. Therefore, the conductive structure has a stable stacking effect while reducing the bridge failure.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example 1

2 is a plan view of a DRAM cell for explaining the first embodiment of the present invention.

3A to 3H are cross-sectional views illustrating a wiring forming method of a DRAM device according to example embodiments. 3A to 3H are cross-sectional views taken along line BB ′ of the plan view of FIG. 2.

Referring to FIG. 3A, a device isolation oxide layer 101 is formed on the semiconductor substrate 100 using an element isolation process such as a shallow trench element isolation (STI) process to form an active region (FIG. 2, 101a).

Subsequently, a MOS transistor is formed on the active region of the substrate 100. The MOS transistor includes a gate electrode (FIG. 2, 102) in which a spacer is formed and a source / drain region 104 on both sides of the gate electrode 102. One of the source / drain regions 104 is a capacitor contact region to which the storage electrode of the capacitor contacts, and the other is a bit line contact region to which the bit line contacts. In this embodiment, the source region is a capacitor contact region and the drain region is a bit line contact region.

Subsequently, an interlayer insulating layer 106 made of oxide is deposited on the entire surface of the substrate 100 including the MOS transistor, and the interlayer insulating layer 106 is planarized by a CMP process. Subsequently, a self-aligned contact hole is formed to expose the source / drain region, and a pad material 108 is formed in contact with the source region and the drain region by filling a conductive material such as polysilicon into the contact hole. .

Subsequently, a first insulating layer 110 is formed on the substrate on which the pad electrodes 108 are formed.

Referring to FIG. 3B, the first insulating layer 110 is partially etched by a photolithography process to form bit line contact holes (FIGS. 2 and 111) exposing the pad electrode 108 in contact with the drain region. do. Subsequently, a first conductive layer 114 is formed in the first insulating layer 110 and the bit line contact hole 111.

Specifically, the first conductive layer 114 is a relatively thin thickness metal layer 114a and a metal layer 114b formed on the metal layer 114a provided to improve the deposition characteristics of the conductive material. Is formed. The groove metal layer 114a includes a Ti film, a TiN film, or a Ti / TiN composite film. The metal layer 114b includes a tungsten layer. At this time, the groove metal layer 114a is deposited about 100 to 500 kPa, and the tungsten layer 114b is deposited to about 1000 to 4000 kPa. The tungsten layer 114b has a specific resistivity lower than that of a metal silicide layer or a polysilicon layer mainly used in the related art, and thus an operation speed may be secured even if the line width of the wiring is reduced.

Referring to FIG. 3C, a silicon nitride film is deposited on the first conductive layer 114 and the silicon nitride film is patterned through a photolithography process to form a hard mask pattern 116. The hard mask pattern 116 serves as a mask for patterning the bit lines and protects the lower bit lines during a subsequent self-aligned contact process.

Referring to FIG. 3D, the hard mask pattern 116 is used as an etching mask, and the first conductive layer 114 is isotropically etched by a partial thickness to form the second conductive layer 115. The second conductive layer 115 is generally thinner than the first conductive layer 114 by an isotropic etching process. However, the portion of the first conductive layer 114 positioned below the hard mask pattern 116 is masked by the hard mask pattern and is etched relatively less than the surroundings. Accordingly, the second conductive layer 115 may have a form of supporting a portion of the bottom surface of the hard mask pattern 116 while protruding a portion of the conductive material provided under the hard mask pattern 116. Isotropic etching of the first conductive layer 114 may be performed by dry etching or wet etching.

For example, when the first conductive layer 114 is formed in a form in which a TiN layer and a tungsten layer are stacked, the tungsten layer should be etched isotropically by a part thickness. The tungsten layer may be isotropically etched by a wet etching method using a chemical including H ₂ O ₂ . The chemical may further add at least one of HF and H ₂ O to the H ₂ O ₂ . The etching rate of the tungsten layer may be controlled by the ratio of the H ₂ O _2, HF and H ₂ O included in the chemical. In general, as the ratio of H ₂ O ₂ in the chemical composition increases, the etching rate of the tungsten layer increases.

However, when the etching rate of the tungsten layer is too high, it is difficult to finely etch the tungsten layer to a desired thickness. In addition, it is not preferable that the etching rate of the tungsten layer is too low to be almost etched. Therefore, it is preferable that the etching rate of the tungsten layer has 500 mW / min or less.

In addition, even if the same chemical composition is used, the etching rate of the tungsten layer varies according to the temperature of the chemical. That is, as the temperature of the chemical increases, the etching rate of the tungsten layer also increases. Therefore, it is preferable to adjust the temperature of the chemical so as to obtain a desired etching rate for each composition of the chemical.

Referring to FIG. 3E, a bit line structure 120 is formed by anisotropically etching the second conductive layer 115 using the hard mask pattern 116 as a mask. The bit line structure 120 has a shape in which a bit line 119 and a hard mask pattern 116 having a relatively reduced upper edge portion are stacked.

Referring to FIG. 3F, a nitride film spacer 122 made of silicon nitride is formed on a side of the bit line structure 120, and then a second insulating layer 124 is formed to bury the bit line structure 120. . The second insulating layer 124 is formed of silicon oxide having a high etching selectivity with the nitride film spacer 122.

Referring to FIG. 3G, the second insulating layer 124a and the first insulating layer 110a between the nitride film spacers 122 are selectively etched to expose the pad electrode 108 connected to the source. The node contact hole 126 is formed.

Specifically, a photoresist pattern defining a contact hole region is formed on the second insulating layer 124a by a photolithography process. Using the photoresist pattern as an etching mask, the second insulating layer 124a and the first insulating layer 110a under the condition that the etching selectivity between the nitride film spacer 122 and the first and second insulating layers 110a and 124a is high. ) Is sequentially etched to form the storage node contact hole 126.

However, as the depth of the storage node contact hole 126 is deepened, the nitride spacers 122a and the hard mask pattern 116 may also be significantly etched during the etching of the second and first insulating layers 124a and 110a. Consumed. In particular, when photo misalignment occurs, the storage node contact hole 126 is consumed because the nitride layer spacer 122a and the hard mask pattern 116 are consumed more at one side of the storage node contact hole 126. A defect that exposes the bit line 119 occurs in terms of the side.

However, the bit line 119 according to the first embodiment of the present invention is relatively reduced in the upper corner portion. Therefore, even if the nitride layer spacer 122a and the hard mask pattern 116 are exhausted, a portion of the bit line 119 may be reduced from the side of the storage node contact hole 126. As a result, a bridge failure between the contact formed in the storage node contact hole 126 and the bit line 119 may be reduced.

In addition, since the bit line structure 120 has a form in which only the upper edge portion of the bit line 119 is partially reduced, the bit line structure 120 has a stable stacking structure compared to a form in which the line width of the bit line 119 is reduced.

Referring to FIG. 3H, a storage node contact 128 is formed by filling and planarizing a conductive material in the storage node contact hole 126. Subsequently, a capacitor (not shown) composed of a storage electrode, a dielectric film and a plate electrode is formed by a normal capacitor forming process.

Example 2

4A to 4E are cross-sectional views illustrating a wiring forming method of a semiconductor device in accordance with a second embodiment of the present invention. Specifically, a method of forming a bit line in a DRAM device will be described. Since the second embodiment to be described below is different only in the method of forming the storage node contact hole, overlapping description is omitted.

In FIG. 4A, the same process as described with reference to FIGS. 3A through 3E is performed. Briefly, pad electrodes 108 included in the MOS transistor (not shown), the interlayer insulating layer 106 and the interlayer insulating layer 106 are formed on the substrate. Subsequently, a first insulating layer 110 is formed on the interlayer insulating layer 106. A bit line structure 120 having a shape in which a bit line 119 and a hard mask pattern 116 in which an upper edge portion is relatively reduced is formed on the first insulating layer 110 is formed.

Referring to FIG. 4B, an oxide-based insulating material is deposited to bury the bit line structure 120 to form a second insulating layer 202. When the bit line 119 includes a tungsten layer, the bit line may be deposited at a high temperature, such as a high temperature oxide film, or when the second insulating layer 202 is deposited with an oxide film requiring a high temperature baking process after deposition, such as BPSG or SOG. Since the side surface of 109 is exposed, a problem occurs that tungsten is oxidized. Therefore, in order to prevent this, the second insulating layer 202 is formed of an HDP oxide film which can be formed at low temperature and realize gap filling without voids. Subsequently, the surface of the second insulating layer 202 is planarized by the CMP process.

Referring to FIG. 4C, a photoresist pattern (not shown) defining a contact hole region is formed on the planarized second insulating layer 202a by a photolithography process. In this case, the photoresist pattern may be formed in a line shape orthogonal to the bit line structures 120.

Subsequently, the second insulating layer 202a and the first insulating layer 110a are sequentially etched to expose the pad electrode 108 connected to the source using the photoresist pattern as a mask. In this case, since no spacer exists on the sidewall of the bit line 119, an etching condition having a high selectivity with the bit line 119 is used to minimize the consumption of the bit line 119. Then, the storage node contact hole 204 is self-aligned with respect to the bit line structure 120. One side surface of the bit line structure 120 is exposed at a side surface of the storage node contact hole 204. In addition, a residue 203 of the second insulating layer remains on the side of the upper edge portion of the bit line 119.

Referring to FIG. 4D, an insulating layer spacer 206 is formed on the side surface of the storage node contact hole 204. The insulating film spacer 206 is formed by performing an insulating film forming process and an anisotropic etching of the insulating film to expose the pad electrode 108 on the bottom surface of the storage node contact hole 204.

The insulating layer spacer 206 is formed to insulate the bit line 119 from a contact to be formed by a subsequent process. The insulating layer spacer 206 may be formed as a film that hardly reacts with the bit line 119 exposed at the side surface of the storage node contact hole 204. The insulating layer spacer 206 may be formed of one of a composite film made of a silicon oxide material, a silicon nitride material, a silicon oxide material, and a silicon nitride material.

An upper edge portion of the bit line 119 may be easily exposed during the anisotropic etching process. However, the bit line 119 according to the second embodiment of the present invention has a form in which the upper edge portion of the bit line 119 is reduced, and the second insulating layer 203 is formed on the side of the edge portion of the bit line. Residues remain. Therefore, the upper edge portion of the bit line 119 may be minimized during the insulating layer spacer 206 process. As a result, defects in which the bit line 119 and the contact formed thereafter are electrically connected to each other may be reduced.

In addition, since the bit line structure 120 has a form in which only the upper edge portion of the bit line 119 is partially reduced, the bit line structure 120 has a stable stacking structure compared to a form in which the entire line width of the bit line 119 is reduced.

Referring to FIG. 4E, a storage node contact 208 is formed by filling and planarizing a conductive material in the storage node contact hole 204 having the insulating layer spacer 206 formed at a side surface thereof. Subsequently, a capacitor (not shown) composed of a storage electrode, a dielectric film and a plate electrode is formed by a normal capacitor forming process.

Example 3

5A through 5H are cross-sectional views illustrating a method of forming wirings in a semiconductor device in accordance with an embodiment of the present invention. Specifically, a method of forming a bit line in a DRAM device will be described. The third embodiment described below is different from the first and second embodiments in the method of forming the bit line structure and the storage node contact hole. Other overlapping explanations are omitted.

FIG. 5A performs the same process as described with reference to FIG. 3A. Briefly, pad electrodes 108 included in the MOS transistor (not shown), the interlayer insulating layer 106 and the interlayer insulating layer 106 are formed on the substrate. Subsequently, the first insulating layer 110 is formed.

Referring to FIG. 5B, the first insulating layer 110 is partially etched by a photolithography process to form a bit line contact hole (not shown) exposing the pad electrode 108 in contact with the drain region. Subsequently, a conductive layer 302 is formed in the first insulating layer 110 and the bit line contact hole, and a hard mask layer 304 is formed on the conductive layer 302.

Specifically, the conductive layer 302 is formed on a relatively thin thickness of the metal layer 302a and the metal layer 302a provided to improve the deposition characteristics of the conductive material, and is a bit line for actual signal transmission. The metal layer 302b serving to form a laminate is formed. The groove metal layer 302a includes a Ti film, a TiN film, or a Ti / TiN composite film. The metal layer 302b includes a tungsten layer. At this time, the groove metal layer 302a is deposited about 100 to 500 kPa, and the tungsten layer is deposited to about 1000 to 4000 kPa. The tungsten layer has a lower specific resistance than a metal silicide layer or a polysilicon layer mainly used in the related art, and thus an operation speed may be secured even if the line width of the signal transmission line is reduced.

The hard mask layer 304 may be formed of silicon nitride and silicon nitride having a high etching selectivity.

Referring to FIG. 5C, the hard mask layer 304 and the conductive layer 302 are patterned to form a conductive structure 308 in which the conductive pattern 303 and the hard mask pattern 305 are stacked. The hard mask pattern 305 serves to protect the lower bit line during a subsequent self-aligned contact process.

Referring to FIG. 5D, the second insulating layer 310 is formed by depositing an oxide-based insulating material to bury the conductive structure 308. In this case, when the conductive pattern 303 includes a tungsten layer, when the second insulating layer 310 is deposited with an oxide film which is deposited at a high temperature like a high temperature oxide film or requires a high temperature baking process after deposition such as BPSG or SOG Since the side surface of the conductive pattern 303 is exposed, a problem occurs in that tungsten is oxidized. Therefore, in order to prevent this, the second insulating layer 310 is formed of an HDP oxide film which can be formed at low temperature and realize gap filling without voids. Subsequently, the surface of the second insulating layer 310 is planarized by the CMP process.

Referring to FIG. 5E, a photoresist pattern (not shown) defining a contact hole region is formed on the planarized second insulating layer 310a by a photolithography process. In this case, the photoresist pattern may be formed in a line shape perpendicular to the bit line structures.

Subsequently, the second insulating layer 310a and the first insulating layer 110a are sequentially etched using the photoresist pattern as a mask to expose the pad electrode 108 in contact with the source region. In this case, since a spacer does not exist on the sidewall of the conductive pattern 303, an etching condition having a high selectivity with the conductive pattern 303 is used to minimize the consumption of the conductive pattern 303. Then, a storage node contact hole 312 is self-aligned with respect to the conductive structure 308. One side surface of the conductive structure 308 is exposed at a side surface of the storage node contact hole 312.

Referring to FIG. 5F, the bit line 314 is formed by isotropically etching the conductive pattern 303 exposed on the side surface of the storage node contact hole 312a by a partial thickness. The bit line structure 316 has a structure in which the bit line 314 and the hard mask pattern 305 are stacked. When the isotropic etching is performed as described above, the hard mask pattern 305 exposed at the side surface of the storage node contact hole 312a may protrude more than the bit line 314. That is, the bit line 314 has a form in which the line width is reduced only in a portion exposed to the side surface of the storage node contact hole 312a.

When the conductive pattern 303 is formed by stacking a TiN layer pattern and a tungsten layer pattern, the tungsten layer should be etched isotropically by a partial thickness. The tungsten layer may be isotropically etched by a wet etching method using a chemical including H ₂ O ₂ . The chemical may further add at least one of HF and H ₂ O to the H ₂ O ₂ . The etching rate of the tungsten may be adjusted by the ratio of the H ₂ O _2, HF and H ₂ O included in the chemical. At this time, the etching rate of the tungsten layer preferably has 500 Å / min or less.

Referring to FIG. 5G, an insulating layer spacer 318 is formed on the side surface of the storage node contact hole 312a. The insulating layer spacer 318 may form an insulating layer on the storage node contact hole 312a and the second insulating layer 310a, and anisotropically etch the formed insulating layer to form a bottom surface of the storage contact hole 312a. It is formed by performing a process of exposing the pad electrode 108 to.

The insulating layer spacer 318 is formed to insulate between the bit line 314 and the contact to be formed by a subsequent process. The insulating layer spacer 318 may be formed as a film that does not react well with the bit line 314 exposed on the sidewall of the contact hole. The insulating layer spacer 318 may be formed of one of a composite film made of a silicon oxide material, a silicon nitride material, a silicon oxide material, and a silicon nitride material.

An upper edge portion of the bit line 314 may be easily exposed during the anisotropic etching process. However, the line width of the bit line 314 according to the second embodiment of the present invention is relatively reduced at a portion adjacent to the storage node contact hole 312a. Therefore, a defect in exposing the upper edge portion of the bit line during the insulating layer spacer 318 may be minimized.

In addition, since the bit line structure has a form that is partially reduced in only one side portion adjacent to the storage node contact hole 312a, the bit line structure has a stable stacking structure compared to a form in which the entire line width of the bit line 314 is reduced. .

Referring to FIG. 5H, a storage node contact 320 is formed by filling and planarizing a conductive material in the storage node contact hole 312a having the insulating layer spacer 318 formed on a side surface thereof. Subsequently, a capacitor (not shown) composed of a storage electrode, a dielectric film and a plate electrode is formed by a normal capacitor forming process.

As described above, according to the present invention, the conductive structure used as the wiring of the semiconductor device has a configuration in which the width of the conductive pattern is partially reduced only in a portion where bridge failure is likely to occur by a subsequent process. Therefore, the conductive structure has a stable stacking effect while reducing the bridge failure.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

1A to 1C are cross-sectional views illustrating a method of forming a conventional self-aligned contact.

2 is a plan view of a DRAM cell for explaining the first embodiment of the present invention.

3A to 3H are cross-sectional views illustrating a wiring forming method of a DRAM device according to example embodiments.

4A to 4E are cross-sectional views illustrating a wiring forming method of a semiconductor device in accordance with a second embodiment of the present invention.

5A through 5H are cross-sectional views illustrating a method of forming wirings in a semiconductor device in accordance with an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100 semiconductor substrate 106 interlayer insulating layer

108: pad electrode 110: first insulating layer

119, 314: bit line 120, 316: bit line structure

122: nitride film spacers 124, 202, 310: second insulating layer

126, 204, 312: storage node contact hole 206, 318: insulating film spacer

Claims (11)

delete delete delete delete delete delete delete delete Forming conductive structures having a conductive pattern and a hard mask pattern stacked on the semiconductor substrate; Forming an insulating layer to bury the conductive structures; Etching the insulating layer between the conductive structures to form a contact hole on a side surface of the conductive pattern and a part of the hard mask pattern; Selectively isotropically etching the exposed conductive pattern such that the hard mask pattern protrudes more than the exposed conductive pattern; And forming an insulating film spacer on a side surface of the contact hole. The method of claim 9, wherein the conductive pattern is formed of a tungsten material. The method of claim 10, wherein the tungsten material is isotropically etched by a chemical including H ₂ O ₂ .