KR100464451B1 - Circuit for reducing leakage current of processor - Google Patents

Abstract

end. The technical field to which the invention described in the claims belongs

An invention of a circuit for reducing the current consumption of a processor.

I. The technical problem to be solved by the invention

The present invention can reduce the leakage current in the electronic device having a processor having a J-tech test terminal, reduce the power consumption in the electronic device, and can increase the use time when the electronic device is composed of a mobile terminal To provide.

All. Summary of Solution of the Invention

The present invention is a circuit of an electronic device composed of a processor having a j-tag test terminal, the reset circuit for processing a reset signal input to the electronic device is connected to the reset terminal of the processor, j-tag provided in the processor A resistor is connected between the initialization test pin of the test terminal and the reset pin of the processor.

The resistor is configured to have the same value as the pull-up resistor provided in the J-tag initialization test pin of the processor.

la. Important uses of the invention

It is used in a processor having a J-Teg test terminal.

Description

CIRCUIT FOR REDUCING LEAKAGE CURRENT OF PROCESSOR}

The present invention relates to a circuit for reducing current consumption in a processor, and more particularly to a circuit for reducing current consumption by reducing leakage current.

In general, a processor is a device used to perform a control operation in an electronic device. Therefore, it is essential to electronic devices. Examples of such a processor are used in many fields such as home electronic devices such as computers or mobile phones and televisions that are commonly used, as well as base stations, base station controllers and mobile switching systems of mobile phones.

There is a case of operating with one processor among the electronic devices as described above. When present as one processor, that is, when driven by a single one chip (SOC), terminals for development of a program to be mounted and development of a peripheral circuit are provided. This will be described with reference to the MSM chip or the chip of the Intel company used in the mobile communication terminal for example.

The chip is provided with a JTAG (Joint Test Action Group) terminal for testing or the like. The j-tag terminal is composed of five pins, which will be described below.

First, the test clock is input to the TCK (Test Clock Input) pin, and second, the test reset input (TRSTB) pin is used to reset the test. Third, the test data output is TDO. 4) TD (Test Data Input) pin, and data input pin at test, and TMS (Test Mode Select Input) pin at last. For pins.

The J-tag terminal as described above monitors the progress of a program for testing a board or detecting a defective state of a board, upgrading a software to be tested on a product, or performing a program during development of a board composed of one chip. It is used to monitor. This will be described in more detail with reference to FIG. 1.

1 is a diagram illustrating some internal components of a chip having a J-tag terminal and a connection configuration of a test apparatus. Next, referring to FIG. 1, an internal configuration of a part of a chip having a J-tag terminal and an operation when the test apparatus is connected will be described.

The semiconductor chip supporting the JTAG test has a tap controller (not shown in FIG. 1) therein. In addition, the TRSTB pin P1 for initializing the tap controller of the semiconductor chip supporting the JTAG test maintains an initialization value by using a pull-up resistor R1 inside the chip for an initialization operation during the JTAG test. . The pin is connected to initiate processor operation within the chip in the normal operation mode of the system. Therefore, after the power of the chip is turned ON, it initially maintains a "low" (0) for a certain period of time and then converts it into "high" (1) ("0" → "1"). Or keep it "low" from the beginning so the internal processor can operate normally.

Therefore, the TRSTB (hereinafter referred to as "initialization test") pin P1 for initializing the tap controller in the semiconductor chip used in the configuration of the system supporting the J-tech test is the same as the general reset pin. The pull up resistor R1 is used to prevent a reset operation caused by an external noise component from occurring.

Data and control signals are received through other pins (not shown in FIG. 1) of the J-tag terminal. The data and control signals input as described above output the data and control signals (Data / Control Signal) converted in a form that can be processed in the processor in the J-tag interface circuit 11. That is, the data and control signals input from the test apparatus 20 are input through the pins of the J-tag terminal, processed by the J-tag interface circuit 11 provided therein, and then processed by the processor.

Meanwhile, the J-tag terminals are used only when performing a test or when uploading a program or updating a program at the time of manufacture of a product, so that they are not used when they are commercialized and released. Therefore, these pins are usually mounted open to the product because they do not perform any special function. However, the initialization test pin P1 among the J-tag pins resets the processor to a pin for performing a reset. Therefore, when the initialization test pin P1 maintains an open state, the processor is reset when noise is input due to a change in temperature, shock, or static electricity.

Therefore, in order to prevent this, a pull down resistor R2 is connected to the initialization test pin P1 of the processor 10 to configure the system. That is, the pull-down resistor R2 is connected to the outside of the processor 10. The pull down resistor R2 maintains a "low" (0) state from the beginning to initialize the processor in the chip in the normal operation mode. In addition, the pull-up resistor R1 is provided inside the processor chip 10 and is connected to the initialization test pin P1. Therefore, in the J-tag test mode, the signal received from the test apparatus 20 is received. That is, it is used to receive the low signal input in the "low" state at the time of reset, and to maintain the "high" state 1 stably after the reset operation.

However, in such a configuration, a product in which the processor is mounted has a current path formed between the pull-up resistor R1 inside the chip and the pull-down resistor R2 inside the chip. Through this, a certain amount of leakage current always flows. That is, a certain amount of unnecessary current consumption is brought. Therefore, when the processor uses a battery, for example, a battery using a battery, such as a mobile communication terminal or a notebook computer has a problem of reducing the use time of the product due to unnecessary leakage current even when not in operation.

It is therefore an object of the present invention to provide a circuit for reducing leakage current in an electronic device having a processor having a J-tech test terminal.

Another object of the present invention is to provide a circuit capable of reducing power consumption in an electronic device having a processor having a J-tag test terminal.

Still another object of the present invention is to provide a circuit which can extend the use time of a mobile terminal in a mobile terminal having a processor having a J-tag test terminal.

The present invention for achieving the above object is a circuit of an electronic device consisting of a processor having a J-tag test terminal, the reset circuit for processing a reset signal input to the electronic device is connected to the reset terminal of the processor, A resistor is connected between an initialization test pin of the J-tag test terminal provided in the processor and a reset pin of the processor.

The resistor is configured to have the same value as the pull-up resistor provided in the J-tag initialization test pin of the processor.

1 is a diagram illustrating a part of internal configuration of a chip having a J-tag terminal and a connection configuration of a test apparatus;

FIG. 2 is a diagram illustrating some internal components of a chip having a J-Teg test terminal according to a preferred embodiment of the present invention. FIG.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

FIG. 2 is a diagram illustrating some internal components of a chip having a J-tag test terminal according to a preferred embodiment of the present invention. Hereinafter, an internal configuration and operation of a chip having a J-tag test terminal according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 2.

The processor chip 10 includes a JTAG (joint test action group) terminal. The j-tag terminal is composed of five pins. Looking at the five pin configuration is as follows. First, the test clock is input to the TCK (Test Clock Input) pin, and second, the test reset input (TRSTB) pin is used to reset the test. Third, the test data output is TDO. 4) TD (Test Data Input) pin, and data input pin at test, and TMS (Test Mode Select Input) pin at last. For pins.

In FIG. 2, only the initialization test pin P1 used for reset among the above-described pins is illustrated. The initialization test pin P1 connects a pull up resistor R1 to the inside of the chip for an initialization operation during the J-tag test for initializing the tap controller of the semiconductor chip 10 supporting the J-tag test. . This is due to the characteristics of the pin. In detail, the power of the chip 10 for performing the J-tag test is turned on, and then initially maintained for a predetermined period of time and then " high " 1) or "low" from the beginning to keep the internal processor operating normally. The pull-up resistor (R1) is connected to the reset signal stage to facilitate the J-tag test.

On the other hand, the reset pin P2 is also connected to the pull-up resistor (R3) for maintaining the reset signal therein. The reset signal is input through the reset pin P2. In addition, the present invention is configured to remove the pull-down resistor (R2) connected between the J-tag initialization test pin (P1) and the ground and is connected to the reset pin (P2).

Meanwhile, a pull-up resistor R3 is connected to the inside of the processor chip 10 of the reset pin P2 to which the reset signal is input. As such, the reset pin P2 is configured to stably provide the reset signal through the pull-up resistor. The reset signal also consists of a reset circuit or a processor (not shown in Fig. 2) for reset. Therefore, since the pull-down resistor R2 connected to the J-tag initialization test pin P1 is connected to the reset pin P2, the current path is lost. Therefore, no leakage current occurs when a processor with a J-Teg test terminal is commercialized.

Next, the operation when the reset signal is input will be described. Since the J-tag initialization test pin P1 of the processor is connected to the reset pin P2, the same signal as the reset pin P2 is input to the processor in the normal operation mode. The reset pin P2 generally transitions to the "high" state 1 after maintaining a "low" state (0) for some time in normal operation. Therefore, since the same value is also maintained in the J-tag initialization test pin P1, it is possible to prevent the reset due to noise when the product is used in production.

In addition, when configured as described above, when the "low" signal is input as the "high" signal to the initialization test pin P1 to perform the reset in the J-tag test mode, the low period was initially maintained as "high". A slight voltage drop may occur at the reset pin P2. However, the Schmitt trigger characteristic generally used in the initialization test pin P1 is configured so as not to directly affect the processor chip 10. That is, to satisfy this, the value of the resistor R2 connected to the J-tag initialization test pin P1 and the reset pin P2 is equal to or smaller than the pull-up resistor R1. It is used to adjust according to the characteristics of the system.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the scope of the following claims, but also by the equivalents of the claims.

As described above, when the electronic device is commercialized as a processor having a J-tag test terminal, the circuit configuration of the test pin can be configured as described above to reduce the leakage current, and thus the use time when the electronic device is configured as a portable device. There is an advantage to increase.

Claims (2)

In the circuit of the electronic device consisting of a one-chip processor having a reset test pin and a reset pin and a J-Teg test terminal to which a circuit having a Schmitt trigger characteristic is connected to the initialization test pin. Pull-up resistors are respectively connected to the initialization test pin and the reset pin of the one-chip processor, The reset stage of the one-chip processor is connected to a reset circuit for processing a reset signal, And a pull-down resistor connected between the initialization test pin and the reset pin of the one-chip processor. The method of claim 1, wherein the resistance is, And a pull-up resistor having the same value as a pull-up resistor provided in the J-tag initialization test pin of the one-chip processor.