CN112181896A

CN112181896A - Operation control device, integrated circuit, radio device, and apparatus

Info

Publication number: CN112181896A
Application number: CN202011027571.6A
Authority: CN
Inventors: 沈阳
Original assignee: Calterah Semiconductor Technology Shanghai Co Ltd
Current assignee: Calterah Semiconductor Technology Shanghai Co Ltd
Priority date: 2020-09-25
Filing date: 2020-09-25
Publication date: 2021-01-05
Anticipated expiration: 2040-09-25
Also published as: CN112181896B

Abstract

The invention discloses an operation control device, an integrated circuit, a radio device and a device, wherein the operation control device is applied to a system on chip, the system on chip comprises a digital function module, and the control device comprises: the digital controller is in communication connection with the digital function module through a digital control interface and is used for generating a control signal for the digital function module to perform function detection; the configuration module is in communication connection with the digital controller and is used for storing configuration information and state information of the system on chip; and the state machine is respectively in communication connection with the configuration module and the digital controller and is used for controlling the running state of the system on chip according to the configuration information of the configuration module. According to the operation control equipment, the unified digital controller is connected with the digital function module of the system on chip through the digital control interface, and then unified configuration management of the operation state of the digital function module in the system on chip is realized through the configuration module and the state machine, so that the operation control efficiency of the system on chip is improved.

Description

Operation control device, integrated circuit, radio device, and apparatus

Technical Field

Embodiments of the present invention relate to computer technologies, and in particular, to an operation control device, an integrated circuit, a radio device, and a device.

Background

A System on Chip (SoC) usually includes a controller for monitoring the functional security of a digital control unit, and when the SoC includes different digital functional modules, a conventional SoC design often requires a plurality of different controllers to perform respective monitoring, which cannot implement uniform configuration management of all the controllers, and thus the control efficiency is low.

Disclosure of Invention

Based on this, the present invention provides an operation control device, an integrated circuit, a radio device, and a device, which can implement unified configuration management of digital function modules in a system on chip.

In a first aspect, an embodiment of the present invention provides an operation control device, which is applied to a system on chip, where the system on chip includes a digital function module, and the operation control device includes:

the digital controller is in communication connection with the digital function module through a digital control interface and is used for generating a control signal for the digital function module to perform function detection;

the configuration module is in communication connection with the digital controller and is used for storing configuration information and state information of the system on chip;

and the state machine is respectively in communication connection with the configuration module and the digital controller and is used for controlling the running state of the system on chip according to the configuration information of the configuration module.

According to the operation control equipment, the unified digital controller is connected with the digital function module of the system on chip through the digital control interface, and then unified configuration management of the operation state of the digital function module in the system on chip is realized through the configuration module and the state machine, so that the operation control efficiency of the system on chip is improved.

In one embodiment, the system on chip further includes an analog function module, and the operation control apparatus further includes:

and the analog controller is in communication connection with the analog function module through an analog control interface and is used for generating a control signal for the analog function module to perform function detection.

In one embodiment, the system on chip includes a plurality of digital function modules, and the digital controller is communicatively connected to each digital function module through a plurality of digital control interfaces.

In one embodiment, the configuration module includes a configuration interface, the configuration interface is an advanced processor bus architecture, and the configuration interface includes at least one of an advanced extensible interface, an advanced high-performance bus interface, an advanced system bus interface, and an advanced peripheral bus interface.

In one embodiment, the operating state of the system on chip includes at least one of a self-test state, a load state, a boot state, a detect state, and an error state.

In one embodiment, the self-test status includes a logic unit built-in self-test and/or a memory built-in self-test.

In one embodiment, the error state comprises a general error state, and the state machine performs a reset operation on the system-on-chip when the system-on-chip enters the general error state; and after the reset operation, the state machine controls the system on the chip to re-enter a starting state.

In one embodiment, the error state further includes a fatal error state, and when the number of times the system-on-chip enters the general error state reaches a preset threshold, the state machine controls the system-on-chip to enter the fatal error state and keep the system-on-chip reset.

In one embodiment, the state machine includes a plurality of operating modes for determining an operating state of the system-on-chip.

In one embodiment, the operation modes of the state machine include:

the system on chip comprises a first operation mode, a second operation mode and a third operation mode, wherein the operation states of the system on chip comprise a self-checking state, a loading state, a starting state, a detection state and an error state;

the operating state of the system on chip comprises a loading state, a starting state, a detection state and an error state;

the operating state of the system on chip comprises a self-checking state, a loading state, a starting state and a detection state;

and in a fourth operation mode, the operation state of the system on chip comprises a self-test state, a loading state, a starting state and a detection state.

In a second aspect, an embodiment of the present invention provides an integrated circuit, which includes a digital circuit, a digital function module, and the operation control device as described above, where the digital function module is respectively connected to the digital circuit and the operation control device in a communication manner;

the digital function module is used for detecting whether the digital circuit is abnormal or not, and the operation control equipment is used for controlling the digital function module to work.

The integrated circuit adopts the unified digital controller to be connected with the digital function module of the system on chip through the digital control interface, and then realizes the unified configuration management of the running state of the digital function module in the system on chip through the configuration module and the state machine, thereby improving the running control efficiency of the system on chip in the integrated circuit.

In one embodiment, the integrated circuit is a millimeter wave radar chip.

In a third aspect, an embodiment of the present invention provides a radio device, including:

a carrier;

the integrated circuit is arranged on the carrier;

an antenna disposed on the carrier;

the integrated circuit is connected with the antenna through a first transmission line and used for receiving and transmitting radio signals.

The radio device adopts the unified digital controller to be connected with the digital function module of the system on chip through the digital control interface, and then realizes the unified configuration management of the running state of the digital function module in the system on chip through the configuration module and the state machine, thereby improving the running control efficiency of the system on chip in the radio device.

In a fourth aspect, an embodiment of the present invention provides an apparatus, including:

an apparatus body; and

the radio device is arranged on the equipment body;

wherein the radio device is used for object detection and/or communication.

According to the equipment, the unified digital controller is connected with the digital function module of the system on chip through the digital control interface, and then unified configuration management of the running state of the digital function module in the system on chip is realized through the configuration module and the state machine, so that the running control efficiency of the system on chip in the equipment is improved.

Drawings

FIG. 1 is a block diagram of an operation control apparatus according to an embodiment;

FIG. 2 is a schematic configuration diagram of an operation control apparatus in one embodiment;

FIG. 3 is a schematic configuration diagram of an operation control apparatus in another embodiment;

FIG. 4 is a diagram illustrating an exemplary operating mode of a state machine.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Fig. 1 is a block diagram of an operation control apparatus in an embodiment, and as shown in fig. 1, in an embodiment, an operation control apparatus 100 is applied to a system on chip, the system on chip including a digital function block, and the operation control apparatus includes: the digital controller 120 is in communication connection with the digital function module through a digital control interface and is used for generating a control signal for the digital function module to perform function detection; a configuration module 140, communicatively connected to the digital controller 120, for storing configuration information and status information of the system on chip; and the state machine 160 is in communication connection with the configuration module 140 and the digital controller 120, respectively, and is configured to control an operating state of the system on chip according to the configuration information of the configuration module 140.

Specifically, in a system on chip (SoC), the digital function module is generally used to monitor the functional security of the external digital circuit, and according to the difference of the SoC function, the digital function module may be one or more, and the operation control device 100 may perform uniform configuration management on the digital function module in the SoC, thereby controlling the operation state of the SoC. In the operation control device 100, the digital controller 120, the configuration module 140, and the state machine 140 are communicatively connected to each other, the digital controller 120 may send a control signal for performing function detection to the digital function module through the digital control interface, the configuration module 140 stores configuration information and state information of the SoC, the configuration information may be obtained from the outside, the state machine 160 is configured to control a workflow of the SoC, and the state machine 160 may read the configuration information stored in the configuration module 140, so as to generate a corresponding control signal for controlling the digital controller 120 and output the control signal to the digital function module in the SoC, thereby implementing configuration management of the digital function module in the SoC.

Further, the configuration and status information in the configuration module 140 may be stored in the form of a register, and the configuration module 140 may include a configuration interface through which a user may input the configuration information into the configuration module 140. The digital controller 140 may include one or more sets of digital control interfaces, and the number and kind of the digital control interfaces may be determined according to the specific situation of the digital function module of the SoC. The state machine 160 may be composed of a state register, a combinational logic circuit, and the like, and the state machine 160 may perform state transition according to a preset operation state to make the digital controller 120 perform a specific operation.

It is understood that, in addition to the digital controller 120, other controllers such as an analog controller may be included in the operation control device 100 to control other types of functional modules in the SoC, and the state machine 160 may also control these other types of controllers according to the corresponding configuration information stored in the configuration module 120, so as to implement uniform control of the operation state of the whole SoC.

The operation control device 100 adopts the unified digital controller 120 to connect with the digital function module of the system on chip through the digital control interface, and then realizes the unified configuration management of the operation state of the digital function module in the system on chip through the configuration module 140 and the state machine 160, thereby improving the operation control efficiency of the system on chip.

Fig. 2 is a schematic structural diagram of an operation control device in an embodiment, and as shown in fig. 2, based on the above technical solution, the system on chip includes a plurality of digital function modules, and the digital controller 120 is respectively connected to each digital function module in a communication manner through a plurality of digital control interfaces 122.

Specifically, a plurality of digital function modules are generally included in the SoC, the digital controller 120 also includes a corresponding number of digital control interfaces 122, each digital control interface 122 is communicatively connected to one digital function module, and the plurality of digital control interfaces 122 collectively connect all the digital function modules in the SoC to the digital controller 120 for management. The digital control interface 122 may be a general bus interface or a custom interface, and the digital control interface 122 may specifically include transmission of a clock signal, an enable signal, a status signal, an error signal, and the like, and may also include transmission of control signals of other third-party tools in the SoC, such as a self-test circuit and other parts.

In one embodiment, the configuration module 140 includes a configuration interface 142, the configuration interface 142 is an advanced processor bus architecture, and the configuration interface 142 includes at least one of an advanced extensible interface, an advanced high-performance bus interface, an advanced system bus interface, and an advanced peripheral bus interface.

Specifically, the configuration Interface 142 is configured to transmit configuration information to the configuration module 140, and the configuration Interface 142 may be a general Bus Interface, and in a specific embodiment, the configuration Interface 142 employs an Advanced micro controller Bus Architecture (AMBA) Architecture, and the configuration Interface 142 may specifically employ interfaces such as an Advanced eXtensible Interface (AXI) in the AMBA Bus, an Advanced High-performance Bus Interface (AHB), an Advanced System Bus Interface (ASB), and an Advanced Peripheral Bus Interface (APB).

The specific choice of configuration interface 142 may be determined by the requirements of the connected device and SoC for speed, bandwidth, and power capabilities. For example, in the AMBA bus, the AHB interface is mainly a bus designed for high-efficiency, high-bandwidth and fast system modules, and can be connected to high-efficiency modules such as a microprocessor, an on-chip or off-chip memory module, and a DMA. The APB interface is mainly used for optimizing power consumption and complex interfaces for low-speed and low-power peripheral devices. The AXI interface mainly aims at the connection of high speed, high bandwidth, pipelined interconnection and one-way channels.

In other embodiments, the configuration interface 142 may also adopt a custom interface, and when the configuration interface 142 adopts the custom interface, the configuration interface 142 may specifically include an enable signal, a read-write control signal, an address line, a write data line, a read data line, and the like.

Fig. 3 is a schematic structural diagram of an operation control device in another embodiment, as shown in fig. 3, based on the above technical solution, in this embodiment, the operation control device 200 includes a digital controller 220, a digital control interface 222, a configuration module 240, a configuration interface 242, and a state machine 260, which may be respectively the same as corresponding structures in the above embodiments, the system on chip in this embodiment further includes an analog function module, and the operation control device 200 may further include: and the analog controller 230 is in communication connection with the analog function module through an analog control interface 232 and is used for generating a control signal for function detection of the analog function module.

Specifically, the SoC of this embodiment further includes an analog function module, where the analog function module may specifically be a radio frequency module, and the number of the analog function modules may be one or more, the operation control device 200 includes an analog-digital controller 230, the analog controller 230 may send a control signal for performing function detection to the analog function module through an analog control interface 232, the configuration module 240 is in communication connection with the analog controller 230, and the configuration module 240 stores therein configuration information corresponding to the analog function module. The number and type of the analog control interfaces 232 in the analog controller 230 may be determined according to the actual situation of the analog function module, the analog control interfaces 232 may be general bus interfaces or custom interfaces, and the analog control interfaces 232 may specifically include transmission of clock signals, reset signals, enable signals, clear signals, status signals, error signals, and the like.

In one embodiment, the operational state of the system-on-chip includes at least one of a self-test state, a load state, a boot state, a detect state, and an error state.

Specifically, after the SoC is powered on, the state machine may control the SoC to jump among a self-test state, a loading state, a starting state, a detection state, an error state, and the like. Specifically, the state machine reads the configuration information and the state information stored in the configuration module 140, and sends a signal to components such as a digital controller in the SoC to execute a corresponding operation, so as to implement a jump of the SoC operating state. According to the preset operation mode and the actual operation condition, the state machine can control the SoC to sequentially perform all the operation states, or only perform part of the operation states.

After the SoC is powered on, the SoC may first enter a self-checking state, where the self-checking state is to perform self-checking on an internal logic unit or a memory, etc. to avoid a fault, and after the self-checking is completed or fails, the SoC may correspondingly jump to a loading state or an error state, and in some operation modes, the SoC may not perform the self-checking state to increase the starting speed. In the loading state, the state machine controls an external One-Time Programmable (OTP) module through the digital controller, the OTP module loads OTP Memory information, and the state machine controls the SoC to jump to the starting state after the loading is finished. In a BOOT (BOOT) state, the processor loads and executes external application codes into an internal memory of the SoC by executing codes in the ROM, and the state machine controls the SoC to jump to a detection state after the BOOT is successful. In the detection (OPERATION) state, the processor runs the application code, monitors whether an error state occurs in the functional module in the SoC through a digital controller and the like, and when an error occurs, the state machine can control the SoC to jump to the error state. In the error state, the state machine may control to perform operations such as reset and the like to recover the normal operation of the SoC, and in some operation modes, the SoC may not perform the error state and directly perform operations such as shutdown or notification to a user for maintenance and the like.

In one embodiment, the self-test status includes logic unit built-in self-test and/or memory built-in self-test.

Specifically, after the SoC jumps to the Self-Test state, the state machine may specifically control the digital controller to perform Logic built-In Self-Test (LBIST for short) and Memory built-In Self-Test (MBIST for short), so as to implement pre-start detection on the Logic unit and the Memory In the SoC. The order of performing LBIST and MBIST can be determined according to actual conditions, and LBIST and MBIST can be performed first.

Further, in logic unit built-in self-test, the state machine enables an external LBIST module through a digital controller, the LBIST module generally tests a random logic circuit, the LBIST module generally adopts a pseudo-random test pattern generator to generate an input test pattern which is applied to a device internal mechanism, and a multiple input register (MISR) is adopted as a generator for obtaining an output signal. After LBIST is finished, the state machine can control the SoC to enter the MBIST or an error state and the like according to the detection result of the LBIST.

In memory built-in self-test, the state machine enables an external MBIST module through a digital controller, the MBIST module is used for memory test, the MBIST module can generally comprise a test circuit for loading, reading and comparing test patterns, and the algorithm of the MBIST module can specifically adopt March algorithm or Checkerboard algorithm and the like. After the MBIST is performed, the state machine can control the SoC to enter a loading state or an error state according to a detection result of the MBIST.

In one embodiment, the error state comprises a general error state, and the state machine performs a reset operation on the system-on-chip when the system-on-chip enters the general error state; the state machine controls the system-on-chip to re-enter the boot state after the reset operation. After detecting that an error occurs in the SoC, the state machine can control the SoC to enter a general error state, reset circuits such as a digital function module and an analog function module in the SoC, restart the SoC after resetting, and then continue to perform corresponding error detection.

Further, in one embodiment, the error state further includes a fatal error state, and when the number of times that the system-on-chip enters the general error state reaches a preset threshold, the state machine controls the system-on-chip to enter the fatal error state, and the system-on-chip is kept reset. When serious errors exist in the SoC, the reset restart cannot solve the generated errors, in order to avoid resource waste due to the continuous cycle reset, a threshold value can be set through the configuration module, and after the number of times of the reset restart when the SoC enters a general error state reaches the threshold value, the state machine cannot control the SoC to be continuously restarted or jump to other states, but keeps all functional modules in the SoC in the reset state, so that the SoC does not influence other external functional modules.

In one embodiment, the state machine includes a plurality of operating modes for determining an operating state of the system-on-chip. Due to different application scenes of the SoC, various operation modes of the state machine can be set through the configuration module, and the state machine under different operation simulation tests controls the operation states which can be jumped by the SoC to be different, so that different application requirements are met.

Fig. 4 is a schematic diagram of an operation mode of the state machine in an embodiment, as shown in fig. 4, in a specific embodiment, the operation mode of the state machine includes: in a first operation mode, the operation state of the system on chip comprises a self-test state, a loading state, a starting state, a detection state and an error state. In a second operating mode, the operating states of the system-on-chip include a load state, a boot state, a detect state, and an error state. And in a third operation mode, the operation state of the system on chip comprises a self-test state, a loading state, a starting state and a detection state. In a fourth operation mode, the operation state of the system on chip includes a self-test state, a loading state, a starting state and a detection state.

Specifically, the state machine may include four operation modes: in the first operation mode, the state machine can control the SoC to sequentially perform all the operation states, can judge whether the SoC has errors in the self-checking process or the starting process, and can realize more accurate error monitoring in the SoC operation process. In the second operation mode, the state machine does not include logic unit built-in self-test and memory built-in self-test, the self-test is not performed after the SoC is powered on, and the SoC directly enters an error state if dislocation occurs or starting failure occurs, so that the starting speed of the SoC can be improved. In the third operation mode, the state machine does not include a general error state and a serious error state, and is kept in a detection state after an error is detected, so as to adapt to an application scenario in which the SoC cannot be reset or restarted. In the fourth operation mode, the state machine does not include logic unit built-in self-test, memory built-in self-test, general error state and serious error state, and the SoC does not perform self-test and can not enter the error state after being electrified, so that the application scene that the requirement on starting speed is high and the SoC cannot be reset or restarted is adapted.

It should be understood that, the units and modules included in the operation control device provided in the embodiment of the present invention are only divided according to functional logic, but are not limited to the above division as long as the corresponding functions can be implemented; in addition, specific names of the functional units are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present invention.

In one embodiment, the present application further provides an integrated circuit, including a digital circuit, a digital function module and the operation control device as in the above embodiments, the digital function module is respectively connected to the digital circuit and the operation control device in a communication manner; the digital function module is used for detecting whether the digital circuit is abnormal, and the operation control equipment is used for controlling the digital function module to work.

Specifically, the integrated circuit comprises digital circuits, digital function modules and operation control equipment, wherein various digital circuits are formed by the basis of the integrated circuit, different digital circuits can realize different functions of the integrated circuit, the digital function modules are used for detecting whether the digital circuits work normally, the operation control equipment can carry out unified configuration management on the digital function modules, a digital controller in the operation control equipment can send control signals for carrying out function detection to the digital function modules through a digital control interface, configuration information and state information are stored in the configuration modules, the configuration information can be acquired from the outside, a state machine is used for controlling the working flow of the integrated circuit, the state machine can read the configuration information stored in the configuration modules and generate corresponding control signals for controlling the digital controller to output to the digital function modules, so as to control the digital function module to detect each digital circuit.

Further, in one embodiment, the integrated circuit may be a millimeter wave radar chip. The kind of digital function module in the integrated circuit can be determined according to actual requirements. For example, in the millimeter wave radar chip, the digital function module may be a power detector or the like, and may be configured to detect whether the voltage value of the antenna power amplifier is abnormal, and the operation control device may control the power detector to operate.

In one embodiment, the present application also provides a radio device comprising: a carrier; the integrated circuit of the above embodiment is disposed on the carrier; an antenna disposed on the carrier; the integrated circuit is connected with the antenna through the first transmission line and used for receiving and transmitting radio signals. The carrier can be a Printed Circuit Board (PCB), and the first transmission line can be a PCB wiring line.

In one embodiment, the present application further provides an apparatus comprising: an apparatus body; and a radio device as in the above embodiment provided on the apparatus body; wherein the radio device is used for object detection and/or communication.

Specifically, on the basis of the above-described embodiments, in one embodiment of the present application, the radio device may be provided outside the apparatus body, in another embodiment of the present application, the radio device may be provided inside the apparatus body, and in other embodiments of the present application, the radio device may be provided partly inside the apparatus body and partly outside the apparatus body. The present application is not limited thereto, as the case may be.

It should be noted that the radio device can perform functions such as object detection and communication by transmitting and receiving signals.

In an optional embodiment, the device body may be an intelligent transportation device (such as an automobile, a bicycle, a motorcycle, a ship, a subway, a train, etc.), a security device (such as a camera), an intelligent wearable device (such as a bracelet, glasses, etc.), an intelligent home device (such as a television, an air conditioner, an intelligent lamp, etc.), various communication devices (such as a mobile phone, a tablet electric energy, etc.), and various devices such as a barrier gate, an intelligent transportation indicator lamp, an intelligent sign, a transportation camera, various industrial manipulators (or a robot), and various instruments for detecting vital sign parameters and various devices carrying the instruments. The radio device may be a radio device as set forth in any embodiment of the present application, and the structure and the operation principle of the radio device have been described in detail in the above embodiments, which are not described in detail herein.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above embodiments only represent the preferred embodiments of the present invention and the applied technical principles, and the description thereof is specific and detailed, but not construed as limiting the scope of the invention. Numerous variations, changes and substitutions will be apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in more detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. An operation control apparatus applied to a system on chip including a digital function module, the operation control apparatus comprising:

2. The operation control apparatus according to claim 1, wherein the system-on-chip further includes an analog function module, the operation control apparatus further comprising:

3. The operation control device according to claim 1, wherein the system on chip includes a plurality of digital function modules, and the digital controller is communicatively connected to each of the digital function modules through a plurality of digital control interfaces, respectively.

4. The operation control device according to claim 1, wherein the configuration module includes a configuration interface, the configuration interface is an advanced processor bus architecture, and the configuration interface includes at least one of an advanced extensible interface, an advanced high performance bus interface, an advanced system bus interface, and an advanced peripheral bus interface.

5. The operation control device according to claim 1, wherein the operation state of the system on chip includes at least one of a self-test state, a loading state, a startup state, a detection state, and an error state.

6. The operation control device according to claim 5, characterized in that the self-test status comprises a logic unit built-in self-test and/or a memory built-in self-test.

7. The operation control apparatus according to claim 5, wherein the error state includes a general error state, and the state machine performs a reset operation on the system-on-chip in a case where the system-on-chip enters the general error state; and after the reset operation, the state machine controls the system on the chip to re-enter a starting state.

8. The apparatus of claim 7, wherein the error condition further comprises a fatal error condition, and wherein the state machine controls the system-on-chip to enter the fatal error condition to keep the system-on-chip reset when the number of times the system-on-chip enters the general error condition reaches a preset threshold.

9. The operation control device according to claim 5, wherein the state machine includes a plurality of operation modes for determining an operation state of the system on chip.

10. The operation control apparatus according to claim 9, wherein the operation mode of the state machine includes:

11. An integrated circuit comprising digital circuitry, a digital function block and an operation control device according to any one of claims 1 to 10, the digital function block being communicatively connected to the digital circuitry and the operation control device, respectively;

12. The integrated circuit of claim 11, wherein the integrated circuit is a millimeter wave radar chip.

13. A radio device, comprising:

a carrier;

an integrated circuit as claimed in any one of claims 11 or 12, disposed on a carrier;

an antenna disposed on the carrier;

14. An apparatus, comprising:

an apparatus body; and

the radio device of claim 13 disposed on the equipment body;

wherein the radio device is used for object detection and/or communication.