KR100461972B1 - Method for fabricating silicide region in cmos image sensor - Google Patents

Abstract

The present invention relates to a method of forming silicide of a CMOS image sensor, and in particular, to prevent silicide of an input / output circuit region by using a hard mask oxide film, and to improve the characteristics of an image sensor by silicide of a region except a photodiode in a pixel region. to be. According to an aspect of the present invention, in the method for forming a silicide of a CMOS image sensor including a pixel region including a photodiode, an input / output circuit region, and a peripheral circuit region, a spacer is formed on a substrate on which a device isolation film defining an active region and a field region is formed. Forming a gate electrode having both sidewalls; Forming an anti-reflection film on the entire structure and performing a front surface etching to expose the gate electrode; Forming a hard mask oxide film covering only the input / output circuit region; Forming a photoresist covering only the photodiode; Removing the anti-reflection film existing on the active area of the peripheral circuit area and the anti-reflection film existing on the active area of the pixel area except the photodiode by performing a front surface etching; And after removing the photoresist, forming a silicide.

Description

Method for fabricating silicide region in cmos image sensor

The present invention relates to a method for manufacturing a CMOS image sensor, and more particularly, to a method for manufacturing a CMOS image sensor in which silicide is formed in a contact formed in an active region of a pixel region to improve device characteristics.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal. Among them, a charge coupled device (CCD) includes individual metal-oxide-silicon (MOS) capacitors. A device in which charge carriers are stored and transported in a capacitor while being in close proximity to each other. Complementary MOS image sensors use CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits. A device employing a switching scheme that creates MOS transistors as many as pixels and sequentially detects outputs using the MOS transistors.

CCD (charge coupled device) has many disadvantages such as complicated driving method, high power consumption, high number of mask process steps, complicated process, and difficult to implement signal processing circuit in CCD chip. In order to overcome such drawbacks, the development of a CMOS image sensor using a sub-micron CMOS manufacturing technology has been studied in recent years. The CMOS image sensor forms an image by forming a photodiode and a MOS transistor in a unit pixel and sequentially detects signals in a switching method, and implements an image by using a CMOS manufacturing technology, which consumes less power and uses 30 to 40 masks as many as 20 masks. Compared to CCD process that requires two masks, the process is very simple, and it is possible to make various signal processing circuits and one chip, which is attracting attention as the next generation image sensor.

FIG. 1A is a circuit diagram showing a unit pixel composed of one photodiode PD and four MOS transistors in a conventional CMOS image sensor, and includes a photodiode 100 for generating photocharges by receiving light. The transfer transistor 101 for transporting the photocharges collected from the photodiode 100 to the floating diffusion region 102 and the potential of the floating diffusion region 102 to a desired value are discharged to discharge the floating diffusion region 102. A reset transistor 103 for resetting the drive transistor, a drive transistor 104 serving as a source follower buffer amplifier, and a select transistor enabling addressing as a switching role. 105). Outside the unit pixel, a load transistor 106 is formed to read an output signal. The three nodes 110, 111, and 112 are separately shown, which will be described later with reference to FIG. 1B.

FIG. 1B is a layout view of the unit pixel illustrated in FIG. 1A, which illustrates an isolation defining an active region in which a photodiode and a diffusion region are to be formed, and a polysilicon constituting a gate of each transistor. It is.

Referring to this, a square active region forms the photodiode 100, and the active region forming the photodiode is bent in a 'b' shape on the upper surface thereof and then extended in the X-axis direction. The gate polysilicon 101 of the transfer transistor Tx is formed over a bottleneck of a portion where the active region constituting the photodiode is bent by a letter 'a', and the floating diffusion region 102 is formed of the gate polysilicon 101 of the transfer transistor. The substrate is laid out at 90 ° from the Y-axis direction in contact with the other side to be in contact with one side of the gate polysilicon 103 of the reset transistor.

In the floating diffusion region 102, an FD contact 110 is formed to electrically connect the floating diffusion region 102 and the gate polysilicon 104 of the drive transistor Dx.

Next, the active region formed on the other side of the gate polysilicon 103 of the reset transistor Rx extends in the X-axis direction and is formed downward by 90 ° in the Y-axis direction from the middle to form the drive transistor Dx. It meets the gate polysilicon 104.

A V _DD contact 111 for applying a power supply voltage is formed in an active region of the reset transistor Rx extending in the X-axis direction from the other side of the gate polysilicon 103, and the gate of the drive transistor Dx is formed. In the polysilicon 104, a contact 114 for electrical connection with the floating diffusion region 102 is formed.

The active region that meets the gate polysilicon 104 of the drive transistor Dx continues to extend in the Y-axis direction to meet the gate polysilicon 105 of the select transistor Sx, and furthermore, the gate of the select transistor Sx. The Sx contact 112 is formed in the active region formed over the polysilicon 105. The Sx contact 112 is a contact for outputting the unit pixel.

Referring to the layout of the unit pixel illustrated in FIG. 1B, three contacts, such as the FD contact 110, the V _DD contact 111, and the Sx contact 112, are formed on the active region in the pixel. The FD contact 110, the V _DD contact 111, and the Sx contact 112 are referred to as active region contacts.

Conventionally, in the unit pixels thus formed, silicide is formed only on the upper portions of the gate polysilicon 101, 103, 104, and 105, and no silicide is formed on the active region. This is because when the silicide is formed on the photodiode 100 formed in the active region, the optical characteristics of the device may be reduced, so that the silicide is not formed on the active region of the unit pixel.

1C to 1E are diagrams illustrating a silicide forming method according to the related art, which is a process cross-sectional view showing a pixel region, an input / output circuit region, and a peripheral circuit region together.

Here, the input / output circuit area refers to a wire bonding area and a circuit in the vicinity of the package during manufacturing CMOS image sensor chip, and the peripheral circuit area refers to a pixel array. Refers to the logic circuit area to process the image information generated by.

First, an isolation layer 11 defining an active region and a field region is formed on the semiconductor substrate 10. A device isolation film using a trench structure may be used as the device isolation film, or a device isolation film may be manufactured using a thermal oxide film.

Next, the gate polysilicon is coated on the substrate 10 and patterned to form the gate electrode 12, and then spacers 13 are formed on both sidewalls of the gate electrode 12. Although not shown in Fig. 1C, a light receiving element including a photodiode or the like is formed in the substrate of the pixel region.

Next, the UGS (Undoped Silicate Glass) film 14 is deposited on the entire structure including the gate electrode, and the antireflection film 15 is coated on the USG film 14. In this case, an HLD (High temperature Low density Dielectrics) oxide film may be used instead of the USG film.

Next, the anti-reflection film 15 and the USG film 14 are sequentially etched by applying an etchbeck process to expose the upper surface of the gate polysilicon 12. Subsequently, as shown in FIG. 1D, when the silicide prevention mask 17 covering the pixel region and the input / output circuit region is formed and etched back, the silicide prevention layer 16 existing on the active region of the peripheral circuit region is formed. Is removed. The silicide prevention layer 16 shown in FIG. 1D refers to a structure formed by stacking the USG film 14 and the antireflection film 15, which is collectively referred to as a silicide prevention layer 16 for convenience of description.

Next, as shown in FIG. 1E, when the silicide forming process is performed after the silicide prevention mask 17 is removed, the gate polysilicon in the pixel region, the gate polysilicon in the input / output circuit region, the active region of the peripheral circuit region, Silicide 18 is formed on top of the gate polysilicon. That is, silicide is formed only in the upper portion of the gate polysilicon in the pixel region, and no silicide is formed in the active region of the pixel region.

Referring to the problems according to the prior art as follows. In line with the recent trend toward smaller devices, the size of image sensors and unit pixels is also becoming smaller and operating voltages are gradually decreasing.

If silicide is not formed in the contact formed in the active region of the pixel in such a situation that the operating voltage is gradually decreasing, the sheet resistance in the active region contact increases, which causes an additional voltage drop. .

This will be described in connection with the three active region contacts described above. First, referring to FIG. 1B, the V _DD contact is a contact formed in the source / drain region of the reset transistor 103 and the source / drain region of the drive transistor 104.

CMOS In the operation of the image sensor requires a reset operation to remove all of the charge remaining in the floating diffusion region 102 will be described this, by turning on the reset transistor 103 e of V _DD contacts remaining in the floating diffusion region 102, Pull out the power supply terminal connected to (111). In this case, when an additional voltage drop occurs in the non-silicided V _DD contact 111 and all of the power supply voltages are not applied, there is a disadvantage in that the efficiency of the reset operation is reduced.

In the case of the FD contact 110, since the FD contact 110 is a contact for electrically connecting the floating diffusion region 102 and the gate polysilicon 104 of the drive transistor, the FD contact 110 additionally due to non-silicide in the FD contact 110. If a voltage drop occurs, the drive transistor 104 cannot be driven to a desired level, thereby reducing the dynamic range. In addition, the Sx contact 112 is a contact formed at the output terminal of the unit pixel, and the voltage drop due to the unsilicide of the Sx contact has a disadvantage of lowering the output of the unit pixel.

In addition, the input / output circuit area usually requires high resistance in order to prevent electrostatic discharge (ESD), but when the silicide formation method according to the prior art is applied, unwanted silicide is used. Has the disadvantage that it is formed on top of the gate polysilicon.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and to prevent silicide in the input / output circuit region, and to form silicide in the active region of the pixel region except for the photodiode, thereby improving the characteristics of the CMOS image sensor. The purpose is to provide.

1A is a circuit diagram showing the configuration of a unit pixel of a conventional CMOS image sensor;

1B is a layout diagram showing a layout of unit pixels of a conventional CMOS image sensor;

1C to 1E are process flowcharts illustrating a silicide forming method of a CMOS image sensor according to the prior art;

2A to 2F are process flowcharts illustrating a silicide forming method of a CMOS image sensor according to an embodiment of the present invention;

* Description of the symbols for the main parts of the drawings *

20: substrate

21: device isolation film

22a: gate polysilicon in the input / output circuit area

22b: gate polysilicon in the pixel region

22c: gate polysilicon in the peripheral circuit area

23: spacer

24: n-type ion implantation area for photodiode

25: antireflection film

26: hard mask oxide film

27: the first mask

28: reverse deep n mask

29: silicide

In order to achieve the above object, the present invention provides a silicide forming method of a CMOS image sensor including a pixel region including a photodiode, an input / output circuit region, and a peripheral circuit region. Forming a gate electrode having spacers on both sidewalls on the formed substrate; Forming an anti-reflection film on the entire structure and performing a front surface etching to expose the gate electrode; Forming a hard mask oxide film covering only the input / output circuit region; Forming a photoresist covering only the photodiode; Removing the anti-reflection film existing on the active area of the peripheral circuit area and the anti-reflection film existing on the active area of the pixel area except the photodiode by performing a front surface etching; And after removing the photoresist, forming a silicide.

According to the present invention, silicide is prevented in an input / output circuit region requiring high resistance, and silicide is formed on an active region except for a photodiode in a pixel region to prevent additional voltage drop generated in the active region contact, thereby improving device characteristics. The present invention relates to a silicide forming method of a CMOS image sensor.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.

2A to 2F are diagrams illustrating a silicide forming method of a CMOS image sensor according to an embodiment of the present invention, and FIG. 3 is a layout diagram illustrating unit pixels of a CMOS image sensor according to an embodiment of the present invention. First, an embodiment of the present invention will be described with reference to FIGS. 2A to 2F.

First, as shown in FIG. 2A, an isolation layer 21 defining an active region and a field region is formed on the semiconductor substrate 20. A device isolation film using a trench structure may be used as the device isolation film, or a device isolation film may be manufactured using a thermal oxide film.

Next, gate polysilicon is applied to the entire region on the substrate 20 and patterned to form the gate electrodes 22a, 22b, and 22c, and then spacers 23 are formed on both sidewalls of the gate electrode 22. . The gate polysilicon 22b formed in the pixel region shows the gate polysilicon of the transfer transistor, and the remaining transistors constituting the unit pixel are not shown in FIG. 2A. A photodiode 24 is formed between the gate polysilicon 22b and the device isolation film 21 of the transfer transistor.

Typically, the photodiode is composed of a deep n-type ion implantation region (deep n-ion implantation region) and a p-type ion implantation region formed thereon, and the process of forming them is as follows.

First, after the gate electrode 22b of the transfer transistor is formed, an ion implantation process using a mask (deep n-mask) exposing only the photodiode region is performed, so that one side is aligned with the gate electrode of the transfer transistor and the other The side forms a deep n-type ion implantation region aligned with the device isolation film. Next, after the spacer is formed, a p-type ion implantation region is formed on the deep n-type ion implantation region by using the same mask.

In addition to the above process sequence, in the low voltage buried photodiode structure, the gate spacer may be formed after successively forming the deep n-type ion implantation region and the p-type ion implantation region.

A mask (deep n-mask) exposing only the photodiode region is modified in a subsequent process (reverse deep n-mask), which will be described later.

Next, an anti-reflection film is coated on the entire structure including the gate electrode 22. In an embodiment of the present invention, only the antireflection film 25 is used without using the UGS (Undoped Silicate Glass) film or HLD (High temperature Low density Dielectrics) oxide film used in the prior art.

In the exemplary embodiment of the present invention, since the silicide is not formed by using the hard mask oxide film and the photoresist in a subsequent process, the area where the silicide is not formed is protected from etching, and thus, the UGS film or the HLD oxide film may not be used. Even when a UGS film or an HLD oxide film is used at the bottom, the form in which the silicide is formed is the same.

Next, as illustrated in FIG. 2B, the anti-reflection film 25 is etched by using front etching to expose the upper surface of the gate polysilicon 22 in all regions.

Subsequently, as shown in Fig. 2C, after the hard mask oxide film 26 is deposited over the entire area, the first mask 27 covering only the input / output circuit area is formed. Next, the hard mask oxide layer 26 is etched using the first mask 27 and the etch selectivity between the hard mask oxide layer 26 and the anti-reflection layer 25. As a result, the hard mask is only on the upper portion of the input / output circuit region. The oxide film 26 remains.

Next, a state in which the first mask 27 is removed is shown in FIG. 2D. After removing the first mask 27 as described above, a reverse deep n mask 28 covering only the photodiode region of the pixel region is formed using a general photoresist.

In order to form a reverse deep n mask 28 covering only the photodiode region here, negative photoresist is used. The deep n-mask is a mask that exposes only the photodiode region, and typically uses a positive photoresist. Thus, if a negative photoresist is used, a reverse deep n mask 28 covering only the photodiode region can be easily formed.

Next, as shown in FIG. 2D, after the reverse deep n mask 28 is formed, the entire surface is etched to remove the anti-reflection film 25 and the photodiode on the active region of the peripheral circuit region. The anti-reflection film 25 existing in the active region of the pixel region is removed.

Since a hard mask oxide layer 26 remains on the upper portion of the input / output circuit region, and a reverse deep n mask 28 is formed on the upper portion of the photodiode region. Only the anti-reflection film 25 present on the surface and the anti-reflection film 25 existing in the active region of the pixel region except for the photodiode are removed.

Next, after removing the reverse deep n mask 28, a silicide forming process is performed. In one embodiment of the present invention, a general photoresist is used as the reverse deep n mask 28 because it can be easily removed through subsequent processing.

As shown in FIGS. 2F to 2E, the reverse deep n mask 28 has one side aligned with the center of the gate polysilicon of the transfer transistor, and the other side aligned with the device isolation layer. In the process of removing the reverse deep n mask 28, the silicide becomes uniform if the gate polysilicon 22b of the transfer transistor is damaged or a residue remains on the gate polysilicon 22b of the transfer transistor. Problems that do not form may occur.

The transfer transistor is an important device for determining the performance of the image sensor. When the silicide is uniformly formed in the gate polysilicon 22b of the transfer transistor, it is possible to ensure reliable operation of the image sensor. For this reason, in one embodiment of the present invention, a reverse deep n mask 28 is formed using a general photoresist that can be easily removed through a general photoresist removal process (PR Strip process).

As shown in FIG. 2F, when the silicide 29 is formed, silicide is not formed in the input / output circuit region, and in the pixel region, the silicide is formed on the top of the gate polysilicon 22b and on the active region except for the photodiode. 29 is formed, and silicide is formed on the gate polysilicon 22c and the active region in the peripheral circuit region.

When the present invention is applied to the CMOS image sensor, there is an advantage of preventing unwanted silicide formation in the input / output circuit region requiring high resistance, and in the pixel region, silicide is formed in the active region except for the gate polysilicon and the photodiode. There is an advantage that can prevent additional voltage drop without deterioration of light sensitivity.

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in the art.

Application of the present invention not only increases the dynamic range of the image sensor by preventing an additional voltage drop in the miniaturized CMOS image sensor, but also prevents unwanted silicide in the input / output circuit area, thereby improving device characteristics. It has an effect.

Claims (6)

A method of forming a silicide of a CMOS image sensor including a pixel region including a photodiode, an input / output circuit region, and a peripheral circuit region, Forming a gate electrode having spacers on both sidewalls on a substrate on which a device isolation film defining an active region and a field region is formed; Forming an anti-reflection film on the entire structure and performing a front surface etching to expose the gate electrode; Forming a hard mask oxide film covering only the input / output circuit region; Forming a mask covering only the photodiode; Removing the anti-reflection film existing on the active area of the peripheral circuit area and the anti-reflection film existing on the active area of the pixel area except the photodiode by performing a front surface etching; And After removing the photoresist, forming silicide Silicide forming method of the CMOS image sensor comprising a. The method of claim 1, The photodiode includes a deep n-ion implantation region, and the mask covering only the photodiode is formed using a reverse deep n-mask. The method of claim 1, Forming a hard mask oxide film covering only the input and output circuit area, Forming a hard mask oxide film on the entire structure; Forming a mask covering only the input / output circuit area; Etching the hard mask oxide layer using the mask and using an etching selectivity ratio between the anti-reflection layer and the hard mask oxide layer Silicide forming method of the CMOS image sensor further comprises. The method of claim 1, Forming an anti-reflection film on the entire structure, Forming a USG film or an HLD oxide film on the entire structure; And forming an anti-reflection film on the USG film or the HLD oxide film. The method of claim 2, And the photoresist is a general photoresist. The method of claim 2, The photoresist is characterized in that the negative photoresist, the silicide forming method of the CMOS image sensor using a Deep n- general mask.