KR100456443B1 - 집적 회로 조립 방법 - Google Patents

집적 회로 조립 방법 Download PDF

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Publication number
KR100456443B1
KR100456443B1 KR10-2001-7015293A KR20017015293A KR100456443B1 KR 100456443 B1 KR100456443 B1 KR 100456443B1 KR 20017015293 A KR20017015293 A KR 20017015293A KR 100456443 B1 KR100456443 B1 KR 100456443B1
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KR
South Korea
Prior art keywords
substrate
integrated circuit
hole
providing
underfill material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR10-2001-7015293A
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English (en)
Korean (ko)
Other versions
KR20020007424A (ko
Inventor
러멜리엠수레쉬
보드라할리나게쉬
코스텔로마이클제이.
로크문레옹
마하잔라비브이.
Original Assignee
인텔 코오퍼레이션
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Filing date
Publication date
Application filed by 인텔 코오퍼레이션 filed Critical 인텔 코오퍼레이션
Publication of KR20020007424A publication Critical patent/KR20020007424A/ko
Application granted granted Critical
Publication of KR100456443B1 publication Critical patent/KR100456443B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49163—Manufacturing circuit on or in base with sintering of base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
KR10-2001-7015293A 1999-06-11 2000-06-05 집적 회로 조립 방법 Expired - Fee Related KR100456443B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/330,373 US6490166B1 (en) 1999-06-11 1999-06-11 Integrated circuit package having a substrate vent hole
US09/330,373 1999-06-11

Publications (2)

Publication Number Publication Date
KR20020007424A KR20020007424A (ko) 2002-01-26
KR100456443B1 true KR100456443B1 (ko) 2004-11-09

Family

ID=23289477

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2001-7015293A Expired - Fee Related KR100456443B1 (ko) 1999-06-11 2000-06-05 집적 회로 조립 방법

Country Status (9)

Country Link
US (2) US6490166B1 (enExample)
EP (1) EP1186212B1 (enExample)
JP (1) JP2003501841A (enExample)
KR (1) KR100456443B1 (enExample)
AU (1) AU5790700A (enExample)
DE (1) DE60026028T2 (enExample)
HK (1) HK1042013B (enExample)
IL (2) IL146865A0 (enExample)
WO (1) WO2000078103A1 (enExample)

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JPH1154658A (ja) * 1997-07-30 1999-02-26 Hitachi Ltd 半導体装置及びその製造方法並びにフレーム構造体
US6483101B1 (en) 1999-12-08 2002-11-19 Amkor Technology, Inc. Molded image sensor package having lens holder
US6861720B1 (en) * 2001-08-29 2005-03-01 Amkor Technology, Inc. Placement template and method for placing optical dies
US6693239B2 (en) * 2001-09-06 2004-02-17 Delphi Technologies Inc. Overmolded circuit board with underfilled surface-mount component and method therefor
US6800946B2 (en) * 2002-12-23 2004-10-05 Motorola, Inc Selective underfill for flip chips and flip-chip assemblies
US7242097B2 (en) 2003-06-30 2007-07-10 Intel Corporation Electromigration barrier layers for solder joints
US20050218528A1 (en) * 2004-03-31 2005-10-06 Beatty John J Capillary underfill channel
US20060046321A1 (en) * 2004-08-27 2006-03-02 Hewlett-Packard Development Company, L.P. Underfill injection mold
US20070087481A1 (en) * 2005-10-19 2007-04-19 Himax Technologies, Inc. Underfill aiding process for a tape
US20100212939A1 (en) * 2007-10-03 2010-08-26 Fujikura Ltd. Module, circuit board, and module manufacturing method
US9105647B2 (en) * 2010-05-17 2015-08-11 Stats Chippac, Ltd. Method of forming perforated opening in bottom substrate of flipchip pop assembly to reduce bleeding of underfill material
US8522426B2 (en) * 2010-06-05 2013-09-03 Raytheon Company Vent blocking on vented ball grid arrays to provide a cleaner solution barrier
AU2013201130B2 (en) * 2012-02-29 2014-12-11 Robert Bosch (Australia) Pty Ltd Printed circuit board
KR101970667B1 (ko) 2012-07-31 2019-04-19 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
KR101934917B1 (ko) * 2012-08-06 2019-01-04 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US9331370B1 (en) 2013-03-14 2016-05-03 Altera Corporation Multilayer integrated circuit packages with localized air structures
US9917068B2 (en) 2014-03-14 2018-03-13 Taiwan Semiconductor Manufacturing Company Package substrates, packaged semiconductor devices, and methods of packaging semiconductor devices
EP3045909B1 (en) 2015-01-14 2020-11-04 Sensirion AG Sensor package
KR102437774B1 (ko) 2015-11-17 2022-08-30 삼성전자주식회사 인쇄 회로 기판
US9721812B2 (en) * 2015-11-20 2017-08-01 International Business Machines Corporation Optical device with precoated underfill
US20220028704A1 (en) * 2018-12-18 2022-01-27 Octavo Systems Llc Molded packages in a molded device
KR20210144302A (ko) 2020-05-22 2021-11-30 삼성전자주식회사 반도체 패키지 및 그의 제조 방법

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EP0805486A1 (en) * 1996-05-01 1997-11-05 Lucent Technologies Inc. Integrated circuit bonding method and apparatus

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EP0805486A1 (en) * 1996-05-01 1997-11-05 Lucent Technologies Inc. Integrated circuit bonding method and apparatus

Also Published As

Publication number Publication date
EP1186212B1 (en) 2006-02-15
JP2003501841A (ja) 2003-01-14
WO2000078103A1 (en) 2000-12-21
US6490166B1 (en) 2002-12-03
HK1042013B (en) 2006-06-02
IL146865A (en) 2007-03-08
USRE44629E1 (en) 2013-12-10
DE60026028T2 (de) 2006-08-10
KR20020007424A (ko) 2002-01-26
AU5790700A (en) 2001-01-02
EP1186212A1 (en) 2002-03-13
HK1042013A1 (en) 2002-07-26
DE60026028D1 (de) 2006-04-20
IL146865A0 (en) 2002-07-25

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