KR100453885B1 - Voltage drop circuit for testing chip, especially including floating prevention circuit to prevent erroneous operation and current consumption - Google Patents

Abstract

PURPOSE: A voltage drop circuit for testing a chip is provided to reduce current consumption during stop mode of the chip by preventing a corresponding node from floating. CONSTITUTION: A circuit for lowering a voltage for testing chips includes a voltage drop circuit, a test signal output circuit, a floating prevention circuit, and a current consumption prevention circuit. The voltage drop circuit(210) lowers a predetermined high voltage signal inputted for a test mode to a predetermined voltage level. The test signal output circuit(220) provides a test signal into a chip in response to the output of the voltage drop circuit. The floating prevention circuit(230) prevents a corresponding node from floating during normal operation of the chip. The current consumption prevention circuit(240) blocks a current flow into the circuit during a stop mode of the chip.

Description

VOLTAGE DROP CIRCUIT FOR CHIP TEST

The present invention relates to a voltage drop circuit for a chip test, and more particularly, to a voltage drop circuit for setting a semiconductor chip to a predetermined test mode by using a high voltage drop.

There is a process for testing a completed semiconductor chip in the production of semiconductor chips. In this test, the semiconductor chip is tested for normal operation. In the past, a separate pin was provided on the semiconductor chip in order to perform the test process on the semiconductor chip. Using the test pins provided separately, the semiconductor chip was set to the test mode and the corresponding test was performed. However, having a separate pin for testing like this is practically unnecessary for the end user. In addition, the provision of a separate test pin on the semiconductor chip had a problem that the corresponding production cost increases. Moreover, this has become unnecessary because of the current trend to reduce the number of pins available in semiconductor chips.

Meanwhile, as a method for overcoming such a conventional problem, a method of using a reset pin provided in a semiconductor chip as a test pin has been proposed and used. The method of using the reset pin as a test pin is a method in which the semiconductor chip enters the test mode and enables the test when a high voltage higher than the voltage level for normally performing the reset is applied to the reset pin. A test mode entry circuit is embedded in a semiconductor chip to implement a method of using the reset pin as a test pin.

1 is a circuit diagram of a conventional test mode entry circuit.

Referring to FIG. 1, the conventional test mode entry circuit may include a voltage drop unit 110 for dropping a test signal of a high voltage (eg, 12V) input through a reset terminal to a corresponding voltage level (eg, 5V). ) And a buffer 120 that provides it to the corresponding portion of the internal circuit of the semiconductor chip.

As described above, in the test mode entry circuit utilizing the high voltage drop, the output node N110 of the voltage drop unit 110 floats when there is no application of high voltage, causing current consumption and malfunction. .

More specifically, when a user uses a semiconductor chip that is found to be in normal operation after testing, the current consumption may be higher than a reference value. In this case, a problem of entering the test mode in a normal operation state has occurred.

Problems also arise in the case of a chip having a function of stopping the operation of the chip. In other words, the current consumption in the state in which the chip is stopped is about several μA, but a large current is consumed by the test mode entry circuit.

Accordingly, an object of the present invention is to solve the above-mentioned problems, and when there is no input of a high voltage, the node is prevented from being floated and the current is consumed, and the current path is stopped when the semiconductor chip is stopped. The present invention provides a voltage drop circuit for chip test that prevents current consumption generated at the time.

1 is a circuit diagram of a voltage drop circuit for a conventional chip test;

2 is a circuit diagram of a voltage drop circuit for chip testing according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

110, 210: voltage drop unit 220: test signal output unit

230: Floating prevention unit 240: Current consumption blocking unit

According to a feature of the present invention for achieving the object of the present invention as described above, the voltage drop circuit for the chip test for testing the operating state of the semiconductor chip: to set to the test mode for performing the test of the chip A voltage drop unit for dropping and outputting the input high voltage signal to a predetermined voltage level; A test signal output unit configured to provide a test signal into a chip in response to an output of the voltage drop unit; A floating prevention unit for preventing a corresponding node from floating during normal operation of the chip; And a current consumption blocking unit for cutting off the current consumption of the circuit when the chip stops operating.

In this embodiment, the voltage drop section is composed of a plurality of transistors configured in series.

The test signal output unit may include: a transistor turned on in response to the output of the voltage drop of the voltage drop unit; And a buffer for outputting the test signal when the transistor is turned on.

In one embodiment, the floating prevention unit comprises: a first transistor configured between an output terminal of the voltage drop unit and a power supply voltage terminal; And second and third transistors configured in parallel between the test signal output unit and the power supply voltage terminal.

In this embodiment, the inverter includes an inverter for inverting a signal input from the reset terminal and applying the inverted signal to the base terminals of the first and second transistors.

In this embodiment, the current consumption blocking unit includes first and second conductive transistors configured in series between power supply voltages and turned on / off in response to input of a predetermined stop signal.

According to the present invention as described above, the floating prevention is prevented by the floating prevention unit in the normal operation is normally operated, the current consumption due to the floating is also blocked. When the operation of the chip is stopped, the current consumption blocker cuts off the current consumption of the voltage drop circuit.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram of a voltage drop circuit for chip test according to an embodiment of the present invention.

As shown in FIG. 2, the voltage drop circuit for chip test according to the embodiment of the present invention includes a voltage drop unit 210 and a voltage drop unit 210 for dropping the input high voltage to a predetermined voltage level. In response to the test signal (TEST) to provide a test signal (TEST) inside the chip to adjust the turn-on (turn-on) voltage level of the circuit to determine the input high voltage level of the reset pin and the high voltage input If not, a floating prevention unit 230 to prevent the node (N210) from floating, and a current consumption blocking unit 240 for reducing the current consumption of the voltage drop circuit when the operation of the semiconductor chip is stopped. do.

Referring to FIG. 2, the voltage drop unit 210 is configured in series with transistors Q211, Q212, and Q213 for dropping the input high voltage to a predetermined voltage level. In this case, an appropriate number of transistors is used so that an appropriate output voltage appears for the input voltage. Table 1 shows an example of a change in output voltage according to a change in input voltage of the voltage drop unit 210.

Input (V) 4 5 6 7 8 9 10 11 12 13 Output (V) 0.8912 1.3780 1.9165 2.4979 3.1159 3.7657 4.4434 5.1460 5.8710 6.6165

The test signal output unit 220 includes a transistor Q221 and an inverter 221 and determines the input level of the high voltage of the reset terminal by adjusting the turn-on voltage level. The current blocking unit 240 includes first and second conductive transistors Q241 and Q242, and consumes unnecessary current in the voltage drop circuit in response to the input of the stop signal STOP when the semiconductor chip is stopped. prevent. The floating prevention unit 230 includes an inverter 232 and first to third transistors Q231, Q232, and Q233, and prevents the node N210 from floating during normal operation, thereby preventing malfunction of the corresponding chip. To cut off the current consumption.

According to the present invention as described above, in the voltage drop circuit for the conventional chip test to prevent the malfunction and current consumption due to the floating of the node, it is possible to operate normally by preventing the floating during normal operation, the current according to the floating Consumption is also cut off. In addition, there is an effect of blocking unnecessary current consumption even when the chip is stopped.

Claims (6)

In the voltage drop circuit for the chip test for testing the operating state of the semiconductor chip: A voltage drop unit 210 for dropping and outputting a predetermined high voltage signal to a predetermined voltage level to set a test mode for performing a chip test; A test signal output unit 220 providing a test signal TEST to the chip in response to the output of the voltage drop unit 210; A floating prevention unit 230 which prevents the corresponding node N210 from floating during normal operation of the chip; And A voltage drop circuit for chip test, characterized in that it comprises a current consumption blocking unit 240 for cutting off the current consumption of the circuit when the chip stops operating. The method of claim 1, The voltage drop unit 210 is a voltage drop circuit for a chip test, characterized in that consisting of a plurality of transistors (Q211, Q212, Q213) configured in series. The method of claim 1, The test signal output unit 220 includes a transistor Q221 which is turned on in response to the output of the dropped voltage of the voltage drop unit 210; And a buffer (221) for outputting the test signal (TEST) when the transistor (Q221) is turned on. The method of claim 1, The floating prevention unit 230 may include a first transistor Q231 configured between an output terminal of the voltage drop unit 210 and a power supply voltage terminal Vss; And a second and third transistor (Q232, Q233) configured in parallel between the test signal output unit (220) and a power supply voltage terminal (Vss). The method of claim 4, wherein And an inverter (232) for inverting a signal input from a reset terminal and applying it to the base terminals of the first and second transistors (Q231, Q232). The method of claim 1, The current blocking unit 240 is configured in series between the power supply voltages Vdd and Vss and is turned on / off in response to the input of a predetermined stop signal STOP. A voltage drop circuit for chip test, comprising (Q241, Q242).

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