JPH05119127A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To facilitate the setting of the size of a transistor group for decreasing voltages in a high-voltage detection circuit and to prevent the effect of the dispersion in manufacturing process on the output potential for the voltage drop transistors in an IC having the constitution, wherein one input terminal is commonly used for two input circuits having the different levels. CONSTITUTION:A first circuit 2 detects the voltage of the first level, which is imparted to an input terminal 1. A first voltage limiting circuit T1 limits the voltage from the input terminal, which is transferred to the first circuit so that the value does not become a specified value or more. A second circuit 3'' is connected to the input terminal and detects the voltage at the second level, which is higher than the first level. These circuits are provided. The second circuit has a second voltage limiting circuit 3b, which limits the output voltage from a voltage drop part 3a to the specified value or lower and inputs the value into a inverter 13. The voltage drop part 3a decreases the voltage at the second level, which is imparted to the input terminal, by the specified value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor integrated circuit (I
In particular, the present invention relates to a semiconductor integrated circuit which switches to a test mode by inputting a voltage higher than a normal input voltage during a test.

[0002]

2. Description of the Related Art In the operation test of an IC, a test mode setting signal is applied to a predetermined input terminal in order to perform a specific test more easily and in a shorter time. In order to reduce the number of input terminals of this IC, the configuration in which the normal signal input terminal and the test input terminal are used in common, that is, the input terminal commonly used in both the normal operation and the test mode is used. Those having the above have been developed, and an example thereof is shown in FIG.

In the input circuit section of the IC shown in FIG.
An input circuit 2 that detects an input signal level during normal operation and a high-voltage detection circuit 3 that receives a high-voltage test mode setting signal and generates a test signal are connected to one input terminal 1. ..

The level of the input signal during normal operation is 0.
Since it is in the range of V to 5V, the signal detection level of the input circuit 2 is a logical level "0" when the input signal is lower than 1.5V, and a logical level "1" when the input signal is 1.5V or higher.
Is set so that it can be determined. On the other hand, in the high voltage detection circuit 3, the signal detection level is set higher than the signal detection level of the input circuit 2, and a high voltage (for example, 12V) for setting the test mode is applied to the input terminal. Sometimes generate a test signal.

Therefore, the output of the high voltage detection circuit 3 is always "0" in the range where the input circuit 2 operates by switching between "1" and "0", and the test mode is set during the normal operation. It works normally. FIG. 8 shows a specific example of the input circuit unit shown in FIG.

Since the signal detection level of the input circuit 2 is low, it is usually CMOS (complementary insulated gate type).
The inverters are connected in cascade (for example, two-stage connected inverters I1 and I2), and the input signal is, for example, 1.
It is set to output a logic "0" when the voltage is lower than 5V and a logic "1" when the voltage is 1.5V or more.

The high voltage detection circuit 3 has the circuit configuration shown in the figure in order to increase the signal detection level. In the high voltage detecting circuit 3, enhancement type MOS transistors Q11 to Q14 for voltage drop are connected in series between the input terminal 1 and the ground potential node. Here, Q11 and Q12 are P-channel transistors whose substrates and sources are connected to each other and whose gates and drains are connected to each other, Q13 is a P-channel transistor whose substrates and sources are connected to each other, and Q14 is a substrate-source to each other. Is an N-channel MOS transistor connected to each other, and the gates of the transistors Q13 and Q14 are connected to the power supply potential (VC) node. The connection point (node A) of the transistors Q13 and Q14 is connected to the input terminal of the inverter I3, and the inverter I4 is provided at the subsequent stage.
Are connected.

The high voltage detection circuit 3 has an inverter I when the voltage value at the input terminal 1 exceeds the sum of the sum of the threshold voltages of the transistors Q11, Q12 and Q13 and the VC potential.
This is based on the fact that the output potentials of 3 and I4 are inverted. That is, when the potential of the input node A of the inverter I3 rises above the threshold voltage of the inverter I3, the potential of the output node B of the inverter I3 changes from logic "1" to logic "0", which causes the output of the inverter I4. The potential of the node C also changes from logic "0" to logic "1".
When the potential of the output node C of the inverter I4 becomes logic "1" in this way, the internal circuit of the IC is set to the test mode.

By the way, in recent ICs, in order to reduce the cost and improve the functions, the miniaturization and high integration of the elements are being further advanced. As the element is miniaturized in this way, the gate insulating film of the MOS transistor is thinned accordingly. This is because miniaturization shortens the channel length of the transistor, so that good operating characteristics cannot be obtained unless the gate insulating film is thinned.

When the gate insulating film of the transistor becomes thin due to the miniaturization as described above, its withstand voltage decreases, so that the input stage transistor of the input circuit 2 is destroyed when 12 V is applied to the input terminal 1 in the test mode. There is a problem that it will be done.

At present, a semiconductor device having a transistor having a gate insulating film of 20 nm has been developed and used. When 12 V is applied to the gate of such a transistor, the electric field applied to the gate insulating film is 6 MV / c
Therefore, even if the gate insulating film is not destroyed, the gate insulating film is inevitably deteriorated. In this case, a transistor whose gate insulating film has a defect due to manufacturing variations is immediately destroyed.

On the other hand, since the transistors Q11 to Q14 form a voltage drop unit for dropping the high voltage applied to the input terminal 1 by a predetermined value, even if a high voltage is applied to the input terminal 1, these inputs are input. The gate insulating film of the stage transistor is not destroyed.

That is, now, the transistors Q11, Q12, Q
When each threshold voltage of 13 is set to -1V and a high voltage signal of, for example, 12V for setting the test mode is applied to the input terminal 1, the connection point of the transistors Q12 and Q13 becomes the threshold voltage of each of the transistors Q11 and Q12. A value lower than the absolute value of the sum (1
0V). The potential difference between the source and gate of the transistor Q11 is approximately 1V, and the source and gate of the transistor Q12
The potential difference between the gates is almost 1V, and 12
Even if V is applied, the transistors Q11 and Q12 are not destroyed.

Further, since the transistor Q13 has a gate potential of VC potential (5V) and a source potential of 10V, there is no potential difference of 5V between the source and the gate. Absent.

The potential of the connection point of the transistors Q13 and Q14 (the input node A of the inverter I3) (output potential from the voltage drop transistor) depends on the ratio of the conduction resistances of the transistors Q11, Q12, Q13 and Q14. It is determined. When 12 V is applied to the input terminal 1, a current flows to the ground potential through the transistors Q11 to Q14, so that the potential at the connection point of the transistors Q12 and Q13 is 1 as described above.
The value is lower than 0V. The potential of the input node A is
Depending on the setting value of the conduction resistance of the transistor Q14, 10
It becomes a value lower than V and can be set to a value lower than 10 V by reducing the conduction resistance of the transistor Q14. With such a configuration, the high voltage detection circuit 3 is
For example, if the input signal is lower than 9V, "0" is output, and if it is 9V or higher, "1" is output.

The problem of the destruction of the transistor in the input stage of the input circuit 2 can be solved by lowering the voltage applied to the input terminal 1 in the test mode. In this case, however, the high voltage detection circuit 3 malfunctions. The problem arises.
In other words, when the level of the test mode setting signal is set low, the signal detection level of the high voltage detection circuit 3 must be set low, so that the level of the input signal becomes apparently high due to the influence of, for example, power fluctuation during normal use. In some cases, the high voltage detection circuit 3 malfunctions and is set to the test mode. Further, the signal applied to the input terminal 1 usually has an overshoot, and especially when the input rises rapidly, the overshoot is large. In this case, if the signal detection level of the high voltage detection circuit 3 is set low, overshoot may be detected and malfunction may occur.

In such a miniaturized IC, there are problems such as destruction of the input-stage transistor gate insulating film or malfunction of the high-voltage detection circuit 3. Actually, as shown in FIG. It was difficult to share one input terminal between two different circuits and to use one input terminal for both test mode setting and normal operation. In order to solve the above problems, the inventor of the present application has proposed a semiconductor integrated circuit having a circuit configuration as shown in FIG.

In the input circuit section of FIG. 9, an N-channel depletion type MOS transistor T1 is additionally connected to the input circuit section shown in FIG. 8 in the current path between the input terminal 1 and the input terminal of the input circuit 2. The gate of the transistor T1 is connected to the VC node.

In an IC having such an input circuit section, the voltage applied to the input terminal 1 is the transistor T1.
The voltage is limited by and is input to the input circuit 2. If the threshold voltage of the transistor T1 is Vth1, the input circuit 2
Is no longer applied as a voltage above the voltage determined by VC-Vth1. If VC = 5V and Vth1 = -2V are set here, VC-Vth1 = 5V-(-2V) = 7
It becomes V, and 7 V or more is not applied to the input circuit 2. Therefore, even when 12V is applied to the input terminal 1 for setting the test mode, the input of the input circuit 2 is 7V.
No more.

Also, instead of the transistor T1,
An N channel enhancement type MOS transistor can also be used. In this case, the gate of this transistor is connected to the VC node and its threshold voltage is Vth1 '.
Is set to 1V, the input voltage of the input circuit 2 becomes VC-
It is limited to Vth1 '= 5V-1V = 4V.

The gate potential of the voltage limiting transistor is not limited to VC but may be a value lower than VC. For example, two resistors connected in series between the VC node and the ground potential node may be connected. You may supply the electric potential of a point.

The voltage value input from the input terminal 1 to the gates of the P-channel MOS transistor Q1 and the N-channel MOS transistor Q2 forming the first-stage inverter I1 of the input circuit 2 is limited by the transistor T1. Transistor Q1,
Even if the gate insulating film of Q2 is thin, it does not cause dielectric breakdown.

Therefore, the voltage input to the input circuit 2 is limited to a predetermined value irrespective of the voltage value applied to the input terminal 1, thereby preventing the gate insulating films of the input first stage transistors Q1 and Q2 from being destroyed. Therefore, it is not necessary to lower the level of the high voltage signal for setting the test mode.

Further, the high voltage detection circuit 3 is directly connected to the input terminal 1, and the voltage applied to the input terminal 1 is directly input to the high voltage detection circuit 3, so that the test mode is used as described above. It is possible to set the signal detection level to a high value so as to detect only the high voltage for setting and not respond to the input signal level during normal operation.

As described above, by setting the signal detection level of the high voltage detection circuit 3 to be sufficiently higher than the signal detection level of the input circuit 2, malfunction due to the influence of power supply fluctuation or the like can be prevented and the reliability of the operation can be improved. Can be increased.

However, in the conventional high voltage detection circuit 3 shown in FIG. 8 or FIG. 9, the potential of the input node A of the inverter I3 is determined by the conduction resistance of the transistor Q14, and therefore the voltage drop transistors Q11 and Q12. , Q1
3. There is a problem that setting the size of the Q14 group becomes troublesome. There is also a problem that the potential of the input node A of the inverter I3 fluctuates due to variations in the manufacturing process.

Further, in the conventional high voltage detecting circuit 3 shown in FIG. 8 or FIG. 9, the P channel transistors Q11, Q12 and Q13 for voltage drop are formed in the separate N type well regions. The pattern area occupied by these voltage drop transistors on the IC chip becomes large. Moreover, the IC has various test modes, and in the conventional IC, two circuits having different detection levels are connected as described above in order to input a test signal for designating various test modes. There are many input terminals. From this, the pattern occupying area on the chip by the high voltage detecting circuit as described above cannot be ignored.

[0028]

As described above, in an IC constructed such that one input terminal is shared by two circuits having different detection levels, the conventional high voltage detection circuit has a voltage drop transistor group of There are problems that size setting becomes troublesome and that the output potential from the voltage drop transistor fluctuates due to variations in the manufacturing process.

Further, in the conventional IC, when the pattern occupying area on the chip due to the voltage drop transistor of the high voltage detection circuit becomes large and there are many input terminals to which the test signal is input, the high voltage detection circuit is used. There is a problem that the pattern occupation area on the chip cannot be ignored.

The present invention has been made to solve the above-mentioned problems, and a voltage drop transistor group in a high voltage detection circuit configured to share one input terminal with other circuits having different detection levels. It is an object of the present invention to provide a semiconductor integrated circuit in which the size can be easily set and the output potential from the voltage drop transistor is strong against variations in the manufacturing process.

Another object of the present invention is that one input terminal is configured to be shared by two circuits having different detection levels, and a test signal for designating a plurality of test modes is input. An object of the present invention is to provide a semiconductor integrated circuit capable of suppressing the pattern occupation area on the chip by the high voltage detection circuit even when there are a plurality of input terminals.

[0032]

According to a first aspect of the present invention, an input terminal, a first circuit for detecting a first level voltage applied to the input terminal, and a first circuit connected to the input terminal are provided.
In a semiconductor integrated circuit including a second circuit that detects a second level voltage higher than the level, the second circuit drops the second level voltage applied to the input terminal by a predetermined value. It is characterized by having a voltage drop unit and a voltage limiting unit for limiting the output voltage from the voltage drop unit to a predetermined value or less.

A second invention is the first input terminal and the first input terminal.
A first circuit for detecting a first level voltage applied to the input terminal of the first input terminal and the first circuit connected to the first input terminal.
A second circuit for detecting a second level voltage higher than the level, a second input terminal, a third circuit for detecting a first level voltage applied to the second input terminal, and A fourth circuit which is controlled by an output from the second circuit and operates in response to a signal supplied to the second input terminal when a second level voltage is applied to the first input terminal. It is characterized by having.

According to a third aspect of the invention, a plurality of the second input terminal, the third circuit and the fourth circuit of the second aspect are provided for each one of the first input terminals. Is configured to be controlled by the output of each of the plurality of fourth circuits.

[0035]

According to the first aspect of the present invention, in an IC configured such that one input terminal is commonly used by the first circuit and the second circuit having different detection levels, the second circuit for high voltage detection has the input terminal. Voltage limiting means for limiting the output voltage from the voltage drop unit for dropping the voltage of the second level given to the above by a predetermined value or less.

Therefore, since it is sufficient to consider only the variation in the threshold voltage of the transistor used in the voltage limiting means, there is a sufficient margin for the variation in the manufacturing process, and the transistor used in the voltage drop section. The size of the group can be easily set.

The second and third inventions are configured so that one input terminal is shared by the first circuit and the second circuit having different detection levels, and a test for designating a plurality of test modes. In an IC having a plurality of input terminals to which a signal is input, a test mode control of a normal voltage level connected to another input terminal by the output of the second circuit for high voltage detection connected to one input terminal And controls a fourth circuit for.

Therefore, one second circuit for high voltage detection is provided for a plurality of input terminals for performing a plurality of test modes.
It is sufficient to provide only one, and it becomes possible to suppress the pattern occupation area on the chip by the second circuit for high voltage detection. In addition, since the fourth circuit for controlling the test mode can also be configured by a circuit equivalent to the normal input circuit, it is possible to reduce the pattern occupying area. From these things, it becomes possible to realize an inexpensive IC with a small chip size.

[0039]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows an input circuit section of an IC according to the first embodiment of the present invention.

This input circuit unit is different from the input circuit unit described above with reference to FIG. 9 in that a voltage limiting unit 3b is added to the high voltage detection circuit 3 ", and other parts are the same. The same reference numerals as in FIG. 9 are attached.

That is, the input circuit section of the IC shown in FIG. 1 has an input terminal 1, a first input circuit 2 for detecting a first level voltage applied to the input terminal 1, and the first input circuit. A first voltage limiting unit (for example, an N-channel depletion type MOS transistor T1) for limiting the voltage transmitted from the input terminal 1 to a predetermined value or more, and is connected to the input terminal 1. A second input circuit (high voltage detection circuit) 3 ″ for detecting a second level voltage higher than the first level.

The high voltage detection circuit 3 "has a voltage drop unit 3a for dropping the voltage of the second level applied to the input terminal 1 by a predetermined value, and the output voltage from the voltage drop unit 3a is a predetermined value or less. Second voltage limiter 3b for limiting
And an inverter I3 to which the output voltage from the voltage drop unit 3a whose voltage is limited by the second voltage limiting unit 3b is input, and an inverter I4 connected to the latter stage.

The voltage limiting section 3b of the high voltage detecting circuit 3 "
As an example, as shown in the figure, an N-channel enhancement type MOS transistor T2 is connected between the VC node and the input node A of the inverter I3, its gate is connected to the input node A, and its substrate is grounded. It is connected to the potential node.

In such an input circuit section of FIG. 1, if the conduction resistance of the transistor T2 is set to be sufficiently smaller than the conduction resistances of the transistors Q11 to Q14 of the high voltage detection circuit 3 ", the high voltage at the input terminal 1 is obtained. When a voltage is applied, the potential of the input node A is limited to VC + Vth2 (Vth2 is the threshold voltage of the transistor T2).

According to the first embodiment as described above, in the IC configured so that one input terminal 1 is shared by two circuits having different detection levels, the high voltage detection circuit 3 ".
Has a voltage limiting section 3b for limiting the output voltage from the voltage drop section 3a for dropping the second level voltage applied to the input terminal 1 by a predetermined value to a predetermined value or less and inputting it to the inverter I3. is doing.

Therefore, the transistor T of the voltage limiting section 3b is
Since it is sufficient to consider only the variation of the threshold voltage Vth2 of 2, the output potential of the voltage drop unit 3a has a sufficient margin with respect to the variation of the manufacturing process, and the voltage drop unit 3a
It becomes easy to set the sizes of the transistors Q11 to Q14. FIG. 2 shows a modification of the input circuit section of the IC of FIG.

This input circuit unit is different from the input circuit unit described above with reference to FIG. 1 in that the voltage limiting unit 3b of the high voltage detection circuit 3 ″ is different and the other parts are the same, and therefore the same reference numerals as in FIG. This voltage limiting unit is, as shown in the figure,
An arbitrary number (three in this example) of N-channel enhancement type MOS transistors T3 ... Are connected in series between the input node A of the inverter I3 and the ground potential node. The drains and gates of the transistors T3 ... Are connected to each other and their substrates are connected to the ground potential node.

In the input circuit unit of FIG. 2, when a high voltage of 12 V is applied to the input terminal 1, the input node A
Is the threshold voltage Vth3 of each of the three transistors T3 ...
Is limited to the total value of. Therefore, the transistor T3
Since it suffices to consider only the variation in the threshold voltage Vth3 of ..., The output potential from the voltage drop transistors Q11 to Q14 has a sufficient margin with respect to the variation in the manufacturing process, and the size of the voltage drop transistors Q11 to Q14 is large. Setting becomes easy. FIG. 3 shows an input circuit section of an IC according to the second embodiment of the present invention.

This input circuit section is constructed so that one input terminal is shared by two circuits having different detection levels.
Further, the present invention is applied to an IC having a plurality of input terminals to which test signals for designating a plurality of test modes are input.

This input circuit section is different from the input circuit section described above with reference to FIG. 8 in that the second input terminal 12 and the third circuit 13 connected to the second input terminal 12 respectively.
8 and the fourth circuit 14 is added, and the fourth circuit 14 is configured to be controlled by the output of the high voltage detection circuit 3.
The same symbols as in the inside are attached.

That is, 1 is the first input terminal, and 2 is the first input terminal.
Is a first circuit for detecting the voltage of the first level applied to the input terminal 1 of, and includes CMOS inverters I1 and I2 connected in two stages. Reference numeral 3 is a second circuit (high voltage detection circuit) which is connected to the first input terminal 1 and detects a voltage of a second level higher than the first level, and is connected to the voltage drop unit 3a and three stages. CMOS inverters I3 to I5
including. Reference numeral 12 is a second input terminal, and reference numeral 13 is a third input terminal for detecting a first level voltage applied to the second input terminal 12.
The same circuit as the first circuit 1 includes two-stage connected CMOS inverters I31 and I32. 14 is controlled by the output of the high voltage detection circuit 3 (for example, the output signal P of the inverter I4), and the first input terminal 1
Is a fourth circuit (test mode control circuit) which operates in response to a signal supplied to the second input terminal 12 when a second level voltage is applied to the second circuit. The test mode control circuit 14 has P-channel transistors Q23 and N23 each having a gate connected to the second input terminal 12 and supplied with a power supply potential VC to substantially function as an inverter in the first stage.
A P-channel which is connected between the channel transistor Q24 and the VC node and the output terminal of the first-stage inverter I21 (the drain interconnection point of the transistors Q23 and Q24), and whose gate is supplied with the output signal P of the high voltage detection circuit 3. The transistor Q21 and the N-channel transistor Q24
Is connected between the source and the ground potential node, and the output signal P from the high voltage detection circuit 3 is applied to the gate N.
The circuit I21 is composed of a channel transistor Q22, and the CMOS inverters I22 and I23 are connected in two stages after the first stage circuit I21.

In such an input circuit section of FIG. 3, when a high voltage is applied to the first input terminal 1 and the test mode is set, the output signal P of the high voltage detection circuit 3 becomes a logic "1". Become. As a result, the test mode control circuit 14
, The transistor Q22 of the first stage circuit I21 is turned on,
The transistor 21 is turned off and the circuit I21 is ready for operation. Therefore, the test mode control circuit 14 operates in response to the signal supplied to the second input terminal 12, and its output signal D can be used as a signal for setting the IC in a predetermined test mode. .. On the other hand, during normal operation, the output signal P of the high voltage detection circuit 3 is "0".
become. As a result, in the test mode control circuit 14, the transistor Q22 of the circuit I21 is turned off, the transistor Q21 is turned on, and the circuit I21 is in the operation standby state, so that its current consumption becomes zero.

According to the IC of the second embodiment as described above, one input terminal is configured to be shared by two circuits having different detection levels, and a test signal for designating a plurality of test modes is provided. Even if there are a plurality of input terminals to which is input, a test for inputting a test signal of a normal voltage level connected to another input terminal 12 by the output of the high voltage detection circuit 3 connected to one input terminal 1 It becomes possible to control the mode control circuit 14.

Therefore, only one high voltage detection circuit 3 needs to be provided for a plurality of input terminals for performing a plurality of test modes, and the pattern occupation area on the chip by the high voltage detection circuit 3 can be suppressed. It will be possible. Moreover, since the test mode control circuit 14 can also be configured by a circuit equivalent to the normal input circuits 2 and 13, the pattern occupying area can be reduced. From these things, it becomes possible to realize an inexpensive IC with a small chip size. FIG. 4 shows a modification of the input circuit unit of the IC of FIG. This input circuit unit is different from the input circuit unit described above with reference to FIG. 3 in the third circuit 13 ″, and is otherwise the same, and is therefore denoted by the same reference numeral as in FIG. 3.

In the third circuit 13 ", a P-channel transistor Q31 and an N-channel transistor Q32 are added to the third circuit 13 in FIG.
The channel transistor Q31 is connected between the VC node and the output end of the first-stage inverter I31 (drain interconnection point of the P-channel transistor Q33 and the N-channel transistor Q34), and the signal P of the high voltage detection circuit 3 is connected to its gate. An inverted output signal / P (the output signal of the inverter I5) which has been inverted is given. The N-channel transistor Q32 is connected between the source of the N-channel transistor Q34 of the first-stage inverter I31 and the ground potential node, and the inverted output signal / P is applied to its gate.

In such an input circuit section of FIG. 4, when a high voltage is applied to the first input terminal 1 and the test mode is set, the inverted output signal / P of the high voltage detection circuit 3 has a logic "0". "become. As a result, in the third circuit 13 ″, the transistor Q32 of the first-stage inverter I31 is turned off,
Since the transistor Q31 is turned on and the first-stage inverter I31 is in the operation standby state, its current consumption becomes zero. On the other hand, in the normal operation, the inverted output signal / P of the high voltage detection circuit 3 becomes "1". As a result, in the third circuit 13 ″, the transistor Q of the first-stage inverter I31 is
32 is turned on, the transistor Q31 is turned off, and the first-stage inverter I31 becomes operable. Therefore, the third circuit 1
3 "operates in response to a signal supplied to the second input terminal 12. FIG. 5 shows an input circuit portion of an IC according to the third embodiment of the present invention.

This input circuit section is different from the second embodiment shown in FIG. 3 in that a plurality of test signals for designating a plurality of test modes are input to one first input terminal. The second input terminals 121, 122 ... Are provided, and the third input circuits 131, 132 ... And the fourth circuit (test mode control circuit) are provided corresponding to the plurality of second input terminals 121, 122. ) 141, 142, ..., And a plurality of fourth circuits 141, 142 ... Are respectively controlled by the output from the second circuit (high voltage detection circuit) 3, Since the others are the same, the same reference numerals as those in FIG. 3 are attached.

According to the IC of the third embodiment, the same effect as that of the second embodiment described above can be obtained.
When a high voltage is applied to the first input terminal 1 to set the test mode, the test mode control circuits 141, 142 ...
Operates correspondingly to the signals supplied to the second input terminals 121, 122, ...
Various test modes can be executed by combining the logic levels of 2 ... FIG. 6 shows an input circuit section of an IC according to the fourth embodiment of the present invention.

This input circuit unit is different from the input circuit unit shown in FIG. 3 or FIG. 5 in the fourth circuit 14 ″ and is otherwise the same, and is therefore assigned the same reference numeral as in FIG. ..
The fourth circuit 14 ″ has a switch circuit SW whose one end side is connected to the output side of the third circuit 13 and a fourth circuit 14 ″ in FIG. 3 or FIG. 5 which is connected to the other end side of the switch circuit SW. The circuit 14 or the fifth circuit 15 having the same configuration as the first circuit 2. In this case, the output from the high voltage detection circuit 3 controls the fifth circuit 15 and turns on the switch circuit SW. It is configured to be controlled to be turned on / off.

As a result, the second signal is applied to the first input terminal 1.
When the output signal of the high voltage detection circuit 3 is activated when the level voltage is applied, the switch circuit SW is turned on and the fifth circuit 15 operates in response to the output signal of the third circuit 13. As a result, substantially the same operation as the operation of the input circuit section shown in FIG. 3 or 5 is performed. Therefore, according to the IC of the fourth embodiment as described above, the same effects as those of the second and third embodiments described above can be obtained.

The present invention is not limited to the above embodiments, but the high voltage detection circuit 3 shown in FIGS.
In addition, as shown in FIG. 1 or 2, voltage limiting means (for example, transistors T2, T3 ...) For limiting the output voltage from the voltage drop unit 3a to a predetermined value or less may be added. Further, voltage limiting means (for example, the transistor T1) for limiting the voltage transmitted from the first input terminal 1 to the first circuit 2 so as not to exceed a predetermined value may be provided.

[0062]

As described above, according to the present invention, in an IC configured to share one input terminal with other circuits having different detection levels, a voltage drop transistor group in a circuit for high voltage detection. Can be easily set and the output potential from the voltage drop transistor can be made strong against variations in the manufacturing process.

Further, according to the present invention, one input terminal is configured to be shared by two circuits having different detection levels, and an input terminal to which a test signal for designating a plurality of test modes is input. In a plurality of ICs having a plurality of lines, it is possible to suppress the pattern occupying area on the chip by the circuit for high voltage detection.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an input circuit section of an IC according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a modified example of FIG.

FIG. 3 is a circuit diagram showing an input circuit unit of an IC according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a modified example of FIG.

FIG. 5 is a circuit diagram showing an input circuit section of an IC according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing an input circuit section of an IC according to a fourth embodiment of the present invention.

FIG. 7 is a block diagram showing an example of an input circuit unit of an IC.

8 is a circuit diagram showing a conventional example of the input circuit unit in FIG.

9 is a circuit diagram showing an example of a conventional improvement of the input circuit unit of FIG.

[Explanation of symbols]

1 ... Input terminal (first input terminal), 2 ... Input circuit (first
Circuit, 3, 3 "... High voltage detection circuit (second circuit),
3a ... voltage drop unit, 3b ... voltage limiting unit (second voltage limiting unit), 12, 121, 122 ... second input terminal, 1
3, 13 ", 131, 132 ... Third circuit, 14, 1
4 ″, 141, 142 ... Test mode control circuit (fourth circuit), 15 ... Fifth circuit, SW ... Switch circuit, T1
... Voltage limiting transistor (first voltage limiting means), T
2, T3 ... Voltage limiting transistors (second voltage limiting means), I1 to I5, I21 to I23, I31, I32 ... Inverter, Q11 to Q14, Q21 to Q24, Q31 to Q34 ... Transistors.

Claims (5)

[Claims] 1. An input terminal, a first circuit for detecting a first level voltage applied to the input terminal, and a second level voltage connected to the input terminal and higher than the first level. And a second circuit for reducing the voltage of the second level applied to the input terminal by a predetermined value and an output voltage from the voltage decreasing section. And a voltage limiting unit for limiting the value to a value or less. 2. A first input terminal, a first circuit for detecting a first level voltage applied to the first input terminal, a first circuit connected to the first input terminal, A second circuit for detecting a higher second level voltage, a second input terminal, a third circuit for detecting a first level voltage applied to the second input terminal, and the second circuit. Controlled by an output from a circuit, the first
A fourth operation circuit that operates in response to a signal supplied to the second input terminal when a second level voltage is applied to the input terminal of
And a semiconductor integrated circuit. 3. The semiconductor integrated circuit according to claim 2, wherein a plurality of the second input terminals, the third circuit and the fourth circuit are provided for each one of the first input terminals, A semiconductor integrated circuit in which a plurality of fourth circuits are respectively controlled by the output from the second circuit. 4. The semiconductor integrated circuit according to claim 2, wherein the second circuit drops the voltage of the second level applied to the first input terminal by a predetermined value. A semiconductor integrated circuit comprising: a voltage limiting unit for limiting the output voltage from the voltage drop unit to a predetermined value or less; and an inverter to which the output voltage from the voltage drop unit is input. 5. The semiconductor integrated circuit according to claim 1, wherein a voltage transmitted from the first input terminal to the first circuit is limited so as not to exceed a predetermined value. A semiconductor integrated circuit further comprising voltage limiting means for controlling the operation.