KR100450678B1 - Semiconductor memory device comprising two-story capacitor bottom electrode and method of manufacturing the same - Google Patents

Abstract

Disclosed are a semiconductor memory device including a capacitor lower electrode having a two-layer structure, and a manufacturing method thereof. The semiconductor memory device according to the present invention includes a capacitor lower electrode composed of a lower storage electrode and an upper storage electrode. The lower storage electrode is formed of a cylindrical structure, and the upper storage electrode is positioned on a sidewall of the lower storage electrode. It consists of two cylindrical structures. The lower portion of the upper storage electrode is open. In addition, the method of manufacturing a semiconductor memory device according to the present invention includes separating a node to form a lower storage electrode, and then forming a recess and removing a predetermined portion of a mold oxide film and a buffer oxide film around the recess. The manufacturing process then proceeds in order to form the upper storage electrode on the sidewalls of the lower storage electrode. According to the present invention, since the effective area can be increased without increasing the height of the capacitor lower electrode, it is possible to manufacture a semiconductor memory device having a high capacitance.

Description

Semiconductor memory device comprising two-story capacitor bottom electrode and method of manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a semiconductor memory device including a capacitor lower electrode having a two-layer structure and a method of manufacturing the same.

As the integration of semiconductor memory devices is advanced, design rules continue to decrease, resulting in a number of challenges. Reducing design rules has made process conditions more demanding and has also accelerated the miniaturization of individual devices. In particular, in the case of DRAM, manufacturing a capacitor having a large capacity (C) required for the device is also a major issue.

In order to solve the above problems, various solutions have been proposed and presently presented. As can be seen from Equation 1 below, a method of increasing the capacitance of a capacitor is first, a method of increasing the effective area of a capacitor, a method of thinning a dielectric film, and a third method of using a dielectric material having a high dielectric constant. It can be largely classified into a method such as.

(ε is the dielectric constant of the dielectric, A is the effective area and t is the thickness of the dielectric film)

Among these methods, the effective area of the capacitor is increased by making the capacitor electrode three-dimensional and increasing its surface area, and by increasing the surface area per unit plane area. A typical example of the latter is a method of forming a hemi-spherical grain (HSG) film on the surface of an electrode. The former method may be divided into a stacked type and a trenched type according to the position where the capacitor electrode is formed.

Stacked capacitors may be classified into a cylinder type, a fin type, or a box type according to the shape of the capacitor electrode. Among them, the cylindrical capacitor can be used not only inside the capacitor lower electrode but also outside thereof, and thus is widely used as a structure suitable for highly integrated memory devices. The present invention intends to increase the effective area of a capacitor by improving it by using such a cylindrical capacitor as a basic structure.

First, a semiconductor memory device including a common cylindrical capacitor lower electrode and a method of manufacturing the same will be described with reference to FIGS. 1 and 2.

As illustrated in FIGS. 1 and 2, an interlayer insulating layer 112 is deposited on the semiconductor substrate 110 including a semiconductor device (not shown) such as a MOS transistor. A capacitor lower electrode contact 114 (hereinafter referred to as a "contact") is formed in the interlayer insulating film 112. The contact 114 electrically connects the source region (not shown) of the MOS transistor formed below and the capacitor lower electrode to be formed in a subsequent process.

Capacitor lower electrodes 118a and 118b are formed in a predetermined portion above the contact 114 and the interlayer insulating film 112. The capacitor lower electrodes 118a and 118b are composed of a bottom surface 118b electrically connected to the contact 114 and a sidewall 118a made vertically high with a constant thickness at the edge of the bottom surface 118b. . The planar shape of the capacitor lower electrodes 118a and 118b, that is, the shape of the bottom surface 118b surrounded by the side wall 118a, may be circular or elliptical, or may be polygonal, such as rectangular. The space between the side walls 118a is empty and is open upwards. When the dielectric film (not shown) and the capacitor upper electrode (not shown) are sequentially formed on the outer and inner surfaces of the sidewall 118a, that is, the inner and inner walls and the bottom surface 118b, the capacitor included in the semiconductor memory device is completed. do.

A method of manufacturing the capacitor lower electrodes 118a and 118b in the form of a cylinder will be briefly described as follows.

First, an etch stop layer (not shown) and a mold oxide layer (not shown) are sequentially deposited on the interlayer insulating layer 112 including the contact 114 therein. The mold oxide film is formed to a thickness of, for example, about 15000 kPa. In addition, when the mold oxide layer and the etch stop layer are selectively etched using photolithography and etching processes, a region in which the capacitor lower electrode is to be formed is defined. The contact 114 is exposed in the region where the capacitor lower electrode is to be formed. Then, a conductive film (not shown) is uniformly deposited on the sidewalls and top of the limited region and the mold oxide film, and a buffer insulating film (not shown) is deposited thereon.

Next, the buffer insulating film and the conductive film are etched until the surface of the mold oxide film is exposed to separate nodes of the conductive film. In the etching process, chemical mechanical polishing (hereinafter, referred to as 'CMP') or dry etch back may be used. Then, when the remaining buffer insulating film and the mold oxide film are removed using a wet etch method or the like, cylindrical capacitor capacitor electrodes 118a and 118b are formed.

However, the capacitor including the above-described capacitor-type capacitor lower electrodes 118a and 118b is accelerated in miniaturization of the device, so that the area of the bottom surface 118b continues to decrease, so that the height of the side wall 118a is not increased. You do not have enough capacity. Infinitely increasing the height of the side wall 118a to increase the capacity is limited when considering the overall arrangement of the elements formed on the upper and lower portions. Furthermore, if the height of the sidewall 118a is too high, the ratio of the height 118a to the width of the bottom surface 118b becomes too large, thereby increasing the possibility that a failure of the semiconductor memory device occurs due to the capacitor lower electrode falling sideways. Therefore, there is a need for a capacitor having a structure that can increase its effective area without further increasing the height of the capacitor lower electrode.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor memory device including a capacitor lower electrode made of a structure capable of increasing capacitance by increasing an effective area of a capacitor without increasing the height of the capacitor lower electrode. .

Another object of the present invention is to provide a method of manufacturing a semiconductor memory device according to the present invention.

1 is a schematic plan view of a semiconductor memory device including a capacitor lower electrode in a general cylindrical shape,

FIG. 2 is a schematic cross-sectional view taken along lines XX 'and YY' of the semiconductor memory device of FIG. 1;

3 is a schematic plan view of a semiconductor memory device including a capacitor lower electrode having a two-layer structure according to the present invention;

4 is a schematic cross-sectional view taken along lines XX 'and YY' of the semiconductor memory device of FIG. 3.

5 to 9 are schematic cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to the present invention.

(Explanation of symbols for the main parts of the drawing)

114, 214: Capacitor bottom electrode contact

216: mold oxide film

118a, 118b: sidewalls and bottom of the capacitor lower electrode

218a, 218b: sidewalls, bottom of lower storage electrodes

220: first buffer insulating film

222a, 222b, and 222c: first sidewall, second sidewall, bottom of the upper storage electrode

224: second buffer insulating film

The semiconductor memory device according to the present invention for achieving the above technical problem includes a capacitor lower electrode composed of a two-layer structure of the lower storage electrode and the upper storage electrode, while the lower storage electrode is a single cylindrical type (single cylindrical type) The upper storage electrode is a dual cylindrical type composed of band-shaped bottoms and first and second sidewalls of different sizes, the bottom side being positioned on the sidewalls of the lower storage electrode and having a first sidewall and a second sidewall. It is formed only between and has an open structure which is not formed between 2nd side wall.

The capacitor lower electrode may be made of polysilicon or metal material, and the height of the upper storage electrode is preferably in the range of 10% to 90% of the total capacitor lower electrode height. The thickness of the lower storage electrode is in the range of about 100 kPa to 500 kPa, and the thickness of the upper storage electrode is in the range of about 100 kPa to 400 kPa.

In addition, the semiconductor memory device according to the present invention may have a polygonal shape, an oval shape, or a circular shape in which the lower and / or upper storage electrodes have a planar shape, and a dielectric film that is functionally adjacent to the capacitor lower electrode and a functional layer adjacent to the dielectric film. The capacitor may further include a capacitor upper electrode.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor memory device, after depositing a mold oxide film on a semiconductor substrate and patterning the mold oxide film to define a lower storage electrode formation region. The lower storage electrode is formed. And forming an upper storage electrode on the lower storage electrode, wherein the upper storage electrode is a dual cylindrical type composed of a band-shaped bottom surface and first and second sidewalls having different sizes. The bottom surface is open on the sidewalls of the lower storage electrode and is formed only between the first sidewall and the second sidewall and not between the second sidewall.

The forming of the lower storage electrode may be performed by uniformly depositing a first conductor layer on the sidewalls and the upper portions of the lower storage electrode forming region and the mold oxide layer, and depositing a first buffer insulating layer thereon. Etching the conductor film to separate the nodes of the first conductor film, and further etching the first conductor film to form a recess. The etching may be performed using a dry etch back method, and the etching and recessing of the first conductor layer may be continuously performed in an in-situ process. have. The first conductor film may be a material having an excellent etching selectivity with respect to the mold oxide film and the first buffer insulating film.

In the forming of the upper storage electrode, the mold oxide film and the first buffer insulating film next to the recess are etched to define a double cylinder type upper storage electrode forming region, and then the second conductor film is uniformly disposed on the entire surface. And deposit a second buffer insulating film thereon. Next, the method may include removing the mold oxide layer, the first buffer insulating layer, and the second buffer insulating layer after the nodes of the second conductive layer are separated to form the upper storage electrode. The thicknesses of the mold oxide film and the first buffer insulating film to be etched are preferably in the range of 100 kV to 500 kV, respectively.

In the method of manufacturing a semiconductor memory device according to the present invention, after the upper storage electrode is formed, forming a dielectric film that is functionally disposed adjacent to the lower capacitor electrode, and the upper part of the capacitor that is functionally adjacent to the dielectric film. The method may further include forming an electrode.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to enable the technical spirit of the present invention to be thoroughly and completely disclosed, and to fully convey the spirit of the present invention to those skilled in the art. In the drawings, the thicknesses of layer regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout the specification.

(Example 1)

3 is a schematic plan view of a semiconductor memory device including a cylindrical capacitor lower electrode having a two-layer structure according to the present invention, and FIG. 4 is cut along the lines XX 'and YY' of the semiconductor memory device of FIG. One schematic cross section.

3 and 4, an interlayer insulating layer 212 is formed on a semiconductor substrate 210 including a semiconductor device (not shown) such as a MOS transistor. The contacts 214 are formed and arranged inside the interlayer insulating film 212. The contact 214 electrically connects the source region (not shown) of the MOS transistor formed below and the capacitor lower electrode to be formed in a subsequent process. Capacitor lower electrodes 218a, 218b, 222a, 222b, and 222c are formed on the contact 214 and the interlayer insulating layer 212. However, the capacitor lower electrodes 218a, 218b, 222a, 222b, and 222c have a two-layer structure including lower storage electrodes 218a and 218b and upper storage electrodes 222a, 222b, and 222c. This is a structural feature of the semiconductor memory device according to the present invention.

Lower storage electrodes 218a and 218b are the same as conventional capacitor lower electrodes 118a and 118b. In more detail, the lower storage electrodes 218a and 218b are formed of a bottom surface 218b electrically connected to the contact 214 and a sidewall 218a formed perpendicular to an edge of the bottom surface 218b. That is, the side wall 218a surrounds the bottom surface 218b, and there is only one side wall 218a of the lower storage electrode (to be distinguished from the upper storage electrode, it is referred to herein as a "single cylindrical type"). To call). The planar shape of the lower storage electrodes 218a and 218b may be circular, elliptical, or polygonal, such as rectangular.

The height of the sidewall 218a is preferably lower than the height of the sidewall 118a of the capacitor lower electrode according to the prior art. This is to ensure space for forming the upper storage electrodes 222a, 222b and 222c on the sidewall 218a of the lower storage electrode without increasing the overall height of the capacitor lower electrode. The thicknesses of the lower storage electrodes 218a and 218b are determined in consideration of design rules, process variables, and structural stability, and are preferably within the range of 100 kV to 500 kV. The lower storage electrodes 218a and 218b are formed of polysilicon or metal material.

The upper storage electrodes 222a, 222b, and 222c include a bottom surface 222c and two sidewalls 222a and 222b, that is, a cylindrical first sidewall 222a and a second sidewall 222b. The upper storage electrodes 222a, 222b, and 222c are formed on the sidewall 218a of the lower storage electrode. More specifically, the bottom surface 222c of the upper storage electrode is formed on the sidewall 218a. The bottom surface 222c is a portion electrically connected to the side wall 218a. The shape of the bottom surface 222c is a band shape having a predetermined thickness and width. The planar contour of the base 222c may be circular or oval or polygonal in shape, such as a rectangle.

Sidewalls 222a and 222b having a predetermined thickness are formed perpendicular to both edges of the bottom surface 222c. There is a bottom surface 222c only between the first sidewall 222a and the second sidewall 222b. In other words, the upper storage electrodes 222a, 222b and 222c are stacked in two cylinder-type structures (the plane size of the first sidewall is larger than the plane size of the lower storage electrode and smaller in the case of the second sidewall). (Herein referred to as "dual cylindrical type"). However, the bottom surface is not formed in the space between the second side walls 222b.

The height of the first and second sidewalls 222a and 222b may be such that the height of the sidewall 118a of the lower storage electrode is subtracted from the height of the sidewall 118a of the capacitor lower electrode according to the related art. In this case, the overall height of the capacitor lower electrode is the same as that of the conventional capacitor lower electrode. However, the heights of the first and second sidewalls 222a and 222b may be lower than this.

The thicknesses of the upper storage electrodes 222a, 222b, and 222c are also determined in consideration of design rules, process variables, and structural stability, and are preferably within the range of 100 kV to 500 kV. The upper storage electrodes 222a, 222b, and 222c are formed of polysilicon or metal material.

The cross-sectional structure of such capacitor lower electrodes 218a, 218b, 222a, 222b and 222c is schematically illustrated in FIG. Referring to FIG. 4, cup-shaped lower storage electrodes 218a and 218b connected to the contact 214 are formed on the interlayer insulating layer 212. The cup-shaped upper storage electrodes 222a, 222b, and 222c are formed one by one on the sidewall 218a of the lower storage electrode. Although the cross-sectional structure appears to have a separate structure formed on the sidewall 218a of the lower storage electrode, as described above, the bottom surface 222c of the upper storage electrode is band-shaped, and the first sidewall 222a and the second sidewall ( 222b are each connected to each other.

The height ht occupied by the upper storage electrodes 222a, 222b, and 222c in the height H of the entire capacitor lower electrode is preferably in the range of about 10% to about 90%. The height ht of the upper storage electrode is determined in consideration of the capacitance value to be obtained, structural stability of the capacitor, manufacturing process, and the like. In the drawing, the height ht of the upper storage electrodes 222a, 222b, and 222c becomes about 60% of the height of the entire capacitor lower electrode H. As shown in FIG.

Next, a change in capacitance with respect to the conventional capacitor will be described by taking an example in which the height ht of the upper storage electrode occupies about 50% of the height H of the entire capacitor lower electrode. When the heights H of the entire capacitor lower electrodes are equal to each other, it is calculated that the effective area increases by about 35% or more in the above example compared with the general cylindrical capacitor lower electrodes shown in FIGS. 1 and 2. This is because the sidewalls 222a and 222b of the upper storage electrode are divided into several branches, such as petals of flowers, to increase the overall surface area. Thus, according to the above example, it is possible to manufacture a capacitor having a capacity of about 35% or more higher than that of a conventional capacitor.

In order to manufacture a capacitor having a larger capacity, it is necessary to further increase the ratio of the height ht of the upper storage electrode. But there are certain limits to this. Factors limiting the height of the upper storage electrode include structural stability and the process of manufacturing the same.

In addition, according to the present embodiment, it is also possible to manufacture a capacitor having the same capacity as a conventional capacitor. In this case, the total height H may be made smaller than the conventional one. Considering the increase amount of the effective area according to the present embodiment, the total height can be reduced to about two thirds of the conventional ones. When the overall height H is reduced, there is no increase in capacitance, but it is possible to significantly reduce the possibility that the lower electrode of the capacitor will fall sideways.

(Example 2)

5 to 9 are schematic cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to the present invention. And the final result is shown in FIG. Hereinafter, an embodiment of a method of manufacturing a semiconductor memory device according to the present invention will be described with reference to these drawings.

First, referring to FIG. 5, a process of depositing an interlayer insulating film 212 on a semiconductor substrate 210 on which devices such as a MOS transistor (not shown) are formed, and forming a contact 214 thereon, is performed using a conventional manufacturing method. The same goes for. Next, an etch stop layer (not shown) is deposited on the interlayer insulating layer 212 and the contact 214 using a silicon nitride layer, and the like, and a mold oxide layer 216 is deposited thereon. The mold oxide film 216 is formed of PETEOS or the like. In addition, the mold oxide layer 216 is deposited thickly in consideration of the overall height of the capacitor lower electrode to be formed, for example, to a thickness of about 15000 Å. However, in some cases, it is possible to form the thickness to about two thirds smaller than before.

Next, the mold oxide layer 216 and the etch stop layer are sequentially etched using photolithography and etching processes to define regions in which the storage lower electrodes 218a and 218b are to be formed. The contact 214 is exposed in an area where the storage lower electrode is to be formed. Next, the first conductor film 218 to be used as the storage lower electrode is uniformly deposited. The thickness of the first conductor film 218 is preferably deposited to a thickness of about 100 kPa to about 500 kPa. The first conductor film 218 is typically formed of polysilicon, but may be formed of a metal material. When using metal materials it is generally possible to deposit thinner than when using polysilicon.

Referring to FIG. 6, a first buffer insulating layer 220 is deposited on the first conductor layer 218. As the first buffer insulating film 220, a material having an excellent etching selectivity with respect to the first conductor film 218, such as a silicon oxide film, is preferably used. Next, the first buffer insulating layer 220 and the first conductor layer 218 are etched to separate the nodes of the first conductor layer 218. In order to separate the node, a method such as chemical mechanical polishing (CMP) or dry etch back (dry etch back) is used.

When the CMP method is used, the node-separated first conductor film 218 is etched more than the mold oxide film 216 or the first buffer insulating film 220, so that a recess is not formed. However, when the node is separated using the dry etch back method, the first conductor layer 220 is etched more deeply to cause recesses. The formation of the recess is possible when the material used as the first conductor film has excellent etching selectivity with respect to the material used as the buffer insulating film and the mold oxide film.

As such, when the high etching selectivity between materials is used, the lower storage electrode 218a of the capacitor lower electrode of the two-layer capacitor is formed in a process of separating the nodes of the first conductor layer 218 and in-situ. You may advance the process of forming. When manufacturing a capacitor lower electrode having a two-layer structure as in this embodiment, it is necessary to further etch the first conductor film 218 in order to secure a space for making the upper storage electrode. Therefore, the first conductor film 218 must be etched deeper than the mold oxide film 216 and the buffer insulating film 220.

In the case of node separation using the CMP method, since the portion to be etched is planarized, only the first conductor film 218 is more etched to prevent recesses. In order to form a recess after the node is separated by the CMP method, a process for etching only the first conductor layer 218 is further required.

On the other hand, when the dry etch back method is used, the difference in the etching rate and the amount of etching may be used when the etching selectivity between materials is excellent. In this case, an additional process is not required to further etch the first conductor film 218 to form a recess between the mold oxide film 216 and the first buffer insulating film 220. However, even when the dry etch back method is used, when the first conductor film 218 needs to be etched more or needs to be etched faster, the process of selectively etching only the first conductor film 218 is additionally performed. You can also use more.

In addition, the height ht of the first conductor layer etched and removed, that is, the height of the recess, may be about 10% to about 90% of the height of the entire lower electrode capacitor. The height of the recess is the height of the upper storage electrode.

The lower storage electrodes 218a and 218b thus made are of a single cylinder type. That is, it consists of the bottom surface 218b connected with the contact 214, and the one side wall 218a perpendicular | vertical to the edge of this bottom surface. The buffer insulating film 220 remains inside the sidewall 218a and the mold oxide film 216 remains outside. The height of the buffer insulating film 220 and the mold oxide film 216 is higher than the height of the sidewall 218a.

Referring to FIG. 7, the mold oxide film 216 and the first buffer insulating layer 220 formed around the space where the removed first conductor film, that is, the recess is formed, are etched. The vacancy where the recess is formed by etching is wider. The mold oxide film 216 and the first buffer insulating film 220 are preferably etched at about 100 kPa to 500 kPa, respectively. The etching process may be any of dry etching and wet etching. Whether the etching method is a dry etching method or a wet etching method, the sidewalls 218a of the lower storage electrode are hardly etched because they have excellent etching selectivity with respect to the mold oxide layer 216 and the buffer insulating layer 220.

In addition, a first buffer insulating layer 220a having a predetermined thickness remains inside the sidewall 218a of the lower storage electrode. The remaining first buffer insulating layer 220a defines a region in which the second sidewall 220b of the upper storage electrode is to be formed. The mold oxide film 216a is also left outside the sidewall 218a of the lower storage electrode. The mold oxide film 216a defines an area in which the first sidewall 220a of the upper storage electrode is to be formed. As a result, the upper storage electrode 220a is formed by the remaining mold oxide film 216a and the first buffer insulating film 220a. , The areas where 220b and 220c are to be formed are defined.

Next, referring to FIG. 8, the second conductor layer 222 is uniformly deposited on the resultant product, that is, the mold oxide layer 216a, the upper and sidewalls of the buffer insulating layer 220a, and the lower storage electrode sidewall 218a. do. The second conductor film 222 is formed of polysilicon or a metal material similarly to the first conductor film. The thickness of the second conductor film 222 is preferably in the range of about 100 kPa to 400 kPa. Next, a thick second buffer insulating film 224 is deposited on the second conductor film 222. The second buffer insulating film 224 also uses a silicon oxide film such as PETEOS as the first buffer insulating film.

Referring to FIG. 9, the second buffer insulating layer 224 and the second conductor layer 222 are etched to separate nodes of the second conductor layer 222. The node separation process uses a method such as CMP method or dry etch back. When the node is separated, upper storage electrodes 222a, 222b and 222c are made as shown.

The upper storage electrodes 222a, 222b and 222c are of double cylinder type. That is, it is composed of a bottom surface 222c and two sidewalls, that is, a first sidewall 222a and a second sidewall 222b. The bottom surface 222c is formed on the sidewall 218a of the lower storage electrode, and is formed only in the space between the first sidewall 222a and the second sidewall 222b and is not formed in the space between the second sidewall. This is because the first buffer insulating film 220a remains in the space as described above. The first sidewall and the second sidewall are vertically formed at both edges of the bottom surface 222c. The plane size of the first sidewall 222a is larger than the plane size of the lower storage electrode sidewall 218a, but the plane size of the second sidewall 222b is smaller than the plane size of the lower storage electrode sidewall 218a.

Next, the mold oxide film 216a, the first buffer insulating film 220a, and the second buffer insulating film 224a that are remaining using the wet etching process may be completely removed. Then, a semiconductor memory device including a capacitor lower electrode having a two-layer structure including lower storage electrodes 218a and 218b and upper storage electrodes 222a, 222b, and 222c as illustrated in FIG. 4 is formed.

According to this embodiment, when the total height of the capacitor lower electrode is the same as before, the capacitor lower electrode having a much larger effective area than before can be manufactured. There is also stability of the process because it uses existing proven processes to manufacture it. In particular, the process of further etching the first conductor film to form a recess may be continuously performed in-situ with the node separation process of the first conductor film.

According to the semiconductor memory device of the present invention, the capacitor lower electrode has a two-layer structure consisting of a lower storage electrode and an upper storage electrode, and the lower storage electrode is a single cylinder type, but the upper storage electrode is a double cylinder type. Since the upper storage electrode of the double cylinder type includes two side walls, its effective area is wider than that of the entire single cylinder type. Thus, it is possible to increase the capacitance of the capacitor without increasing the overall height of the capacitor lower electrode. In addition, reducing the height of the entire lower electrode capacitor can ensure the same capacity of the capacitor. In this case, the phenomenon that the capacitor lower electrode falls sideways can also be suppressed.

In addition, according to the method of manufacturing a semiconductor memory device of the present invention, the manufacturing method is stable and simple because the existing proven process can be used for the process of forming the capacitor lower electrode.

Claims (19)

A semiconductor memory device comprising a capacitor lower electrode formed of a two-layer structure of a lower storage electrode and an upper storage electrode. The lower storage electrode is a single cylindrical type composed of a first bottom surface and one side wall, The upper storage electrode is a dual cylindrical type having first and second sidewalls having different sizes from a second bottom surface, wherein the first sidewall is located outside the sidewall of the lower storage electrode, and the second sidewall is The second bottom surface is positioned on the sidewall of the lower storage electrode, and the second bottom surface is formed between the first sidewall and the second sidewall, but between the second sidewall. A semiconductor memory device, which is not formed but is open. The semiconductor memory device of claim 1, wherein the capacitor lower electrode is made of polysilicon and / or a metallic material. The semiconductor memory device of claim 1, wherein a height of the upper storage electrode is in a range of 10% to 90% of a total height of the capacitor lower electrode. The semiconductor memory device of claim 1, wherein a thickness of the lower storage electrode is in a range of about 100 GPa to 500 GPa. The semiconductor memory device of claim 1, wherein the upper storage electrode has a thickness in a range of about 100 GPa to 400 GPa. The semiconductor memory device of claim 1, wherein the planar shape of the lower and upper storage electrodes is polygonal, elliptical, or circular. The method of claim 1, A dielectric film disposed functionally adjacent to the capacitor lower electrode; And And a capacitor upper electrode disposed functionally adjacent to the dielectric film. In the method of manufacturing a semiconductor memory device comprising a lower electrode of a capacitor consisting of a lower storage electrode and an upper storage electrode, (a) depositing a mold oxide film on the semiconductor substrate; patterning the mold oxide layer to define a lower storage electrode formation region; (c) forming the lower storage electrode having a single cylinder shape having a first bottom surface and one sidewall in the lower storage electrode forming region; And (d) forming the upper storage electrode on the lower storage electrode, wherein the upper storage electrode is of a dual cylindrical type composed of first and second sidewalls having different sizes from a second bottom surface; A first sidewall is located outside the sidewall of the lower storage electrode and the second sidewall is located inside the sidewall of the lower storage electrode, the second bottom is located on the sidewall of the lower storage electrode and the second bottom surface is the And forming an upper storage electrode which is formed between the first sidewall and the second sidewall but is not formed between the second sidewall and is open. The method of claim 8, wherein step (c) (c1) depositing a first conductor film on the storage lower electrode forming region and on the mold oxide layer consistently; (c2) depositing a first buffer insulating film on the first conductor film; (c3) etching the first buffer insulating film and the first conductor film to separate nodes of the first conductor film; And and (c4) further etching the first conductor layer to form a recess and to form the lower storage electrode of a single cylinder type composed of a first bottom surface and one sidewall. Method of manufacturing the device. 10. The method of claim 9, wherein etching in the steps (c3) and (c4) is performed by using a dry etch back method. The method of claim 10, wherein the step (c3) and the step (c4) are performed in an in-situ process. 12. The method of claim 11, wherein the first conductor film is a material having an excellent etching selectivity with respect to the mold oxide film and the first buffer insulating film. The method of claim 9, wherein step (d) (d1) etching the mold oxide film and the first buffer insulating film deposited next to the recess to define a double cylinder type upper storage electrode forming region; (d2) uniformly depositing a second conductor film on the upper storage electrode forming region, the mold oxide film, and the buffer oxide film; (d3) depositing a second buffer insulating film on the second conductor film; (d4) forming the upper storage electrode by etching the second buffer insulating layer and the second conductive layer; And and (d5) removing the remaining mold oxide film, the first buffer insulating film, and the second buffer insulating film. The method of claim 13, wherein the thicknesses of the mold oxide film and the first buffer insulating film etched in the step (d1) are in the range of 100 kV to 500 kV, respectively. The method of claim 8, wherein the height of the upper storage electrode is in a range of 10% to 90% of the total height of the capacitor lower electrode. The method of claim 8, wherein a thickness of the lower storage electrode is in a range of about 100 GPa to 500 GPa. The method of claim 8, wherein the thickness of the upper storage electrode is in a range of about 100 GPa to 400 GPa. The method of claim 8, wherein the planar shape of the lower and upper storage electrodes is polygonal, elliptical, or circular. The method according to claim 8 or 13, wherein after step (d) (e) forming a dielectric film disposed functionally adjacent to the lower capacitor electrode; And and (f) forming a capacitor upper electrode disposed functionally adjacent to the dielectric film.