CN115312465A - Preparation method of semiconductor structure and semiconductor structure - Google Patents
Preparation method of semiconductor structure and semiconductor structure Download PDFInfo
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- CN115312465A CN115312465A CN202210975666.3A CN202210975666A CN115312465A CN 115312465 A CN115312465 A CN 115312465A CN 202210975666 A CN202210975666 A CN 202210975666A CN 115312465 A CN115312465 A CN 115312465A
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- 238000002360 preparation method Methods 0.000 title abstract description 6
- 239000003990 capacitor Substances 0.000 claims abstract description 100
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- 238000000034 method Methods 0.000 claims abstract description 56
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- 239000012212 insulator Substances 0.000 description 4
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- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
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- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium(II) oxide Chemical compound [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The embodiment of the disclosure provides a preparation method of a semiconductor structure and the semiconductor structure, wherein the method comprises the following steps: providing a substrate, wherein a support structure is formed on the substrate; forming a plurality of capacitive vias in the support structure; forming a lower electrode in the capacitor hole, wherein the lower electrode covers the side wall and the bottom of the capacitor hole; forming a first dielectric layer, wherein the first dielectric layer covers the surface of the lower electrode; forming a first upper electrode, wherein the first upper electrode covers the surface of the first dielectric layer; removing part of the support structure positioned between the capacitor holes to form an accommodating cavity, wherein at least part of the lower electrode is exposed out of the accommodating cavity, and the remained support structure is positioned on part of the side wall of the lower electrode; forming a second dielectric layer, wherein the second dielectric layer covers the side wall and the bottom of the accommodating cavity; and forming a second upper electrode, wherein the second upper electrode covers the second dielectric layer and the upper surface of the first upper electrode.
Description
Technical Field
The present disclosure relates to the field of semiconductor manufacturing, and in particular, to a method for manufacturing a semiconductor structure and the semiconductor structure.
Background
As the size of semiconductor devices becomes smaller and smaller with the development and progress of technology, the semiconductor devices are continuously developed toward miniaturization and high integration. A Dynamic Random Access Memory (DRAM) is widely used as a semiconductor device for writing and reading data randomly at a high speed in a data storage device or apparatus.
The DRAM structure usually uses a capacitor to store information, and although the manufacturing process is mature, in actual operation, the capacitor structure still has many problems to be improved.
Disclosure of Invention
The embodiment of the disclosure provides a preparation method of a semiconductor structure, which comprises the following steps:
providing a substrate, wherein a support structure is formed on the substrate;
forming a plurality of capacitive vias within the support structure;
forming a lower electrode in the capacitor hole, wherein the lower electrode covers the side wall and the bottom of the capacitor hole;
forming a first dielectric layer, wherein the first dielectric layer covers the surface of the lower electrode;
forming a first upper electrode, wherein the first upper electrode covers the surface of the first dielectric layer;
removing a part of the support structure positioned between the capacitor holes to form a containing cavity, wherein at least a part of the lower electrode is exposed out of the containing cavity, and the remained support structure is positioned on a part of the side wall of the lower electrode;
forming a second dielectric layer, wherein the second dielectric layer covers the side wall and the bottom of the accommodating cavity;
and forming a second upper electrode, wherein the second upper electrode covers the second dielectric layer and the upper surface of the first upper electrode.
In some embodiments, the first dielectric layer and the second dielectric layer are different materials and/or different sizes.
In some embodiments, the dielectric constant of the material of the first dielectric layer is equal to or less than 3.9, and the dielectric constant of the second dielectric layer is greater than 3.9.
In some embodiments, the width of the second dielectric layer is greater than or equal to the width of the first dielectric layer in a direction parallel to the substrate, and/or,
and in the direction vertical to the substrate, the height of the second dielectric layer is greater than or equal to that of the first dielectric layer.
In some embodiments, the opening dimension of the capacitive aperture is equal to or less than 25nm in a direction parallel to the substrate.
In some embodiments, forming a lower electrode within the capacitive aperture comprises:
depositing an electrode material covering the sidewalls and bottom of the capacitive hole and covering the upper surface of the support structure;
and performing an etching process to remove the electrode material on the upper surface of the support structure, wherein the electrode material remained on the side wall and the bottom of the capacitor hole forms a lower electrode.
In some embodiments, removing portions of the support structure between the capacitor holes to form a receiving cavity comprises:
forming a mask layer on the first upper electrode, wherein the mask layer comprises an etching window, and the orthographic projection of the etching window on the substrate is overlapped with the orthographic projection of part of the supporting structure on the substrate;
and etching the first upper electrode, the first dielectric layer and the support structure exposed by the etching window to form the accommodating cavity, wherein at least part of the lower electrode is exposed by the accommodating cavity, and the part of the side wall of the lower electrode is covered by the support structure which is not etched.
In some embodiments, forming a second dielectric layer comprises:
depositing a dielectric material, wherein the dielectric material covers the side wall and the bottom of the accommodating cavity and covers the upper surface of the first upper electrode;
and performing an etching process to remove the part of the dielectric material covering the upper surface of the first upper electrode, wherein the retained dielectric material layer forms a second dielectric layer.
The disclosed embodiment also provides a semiconductor structure, including:
the device comprises a substrate and a support structure positioned on the substrate, wherein a plurality of capacitance holes are formed in the support structure;
a lower electrode discretely disposed in the plurality of capacitor holes, the support structure being located on a portion of a sidewall of the lower electrode;
the first dielectric layer covers the surface of the lower electrode;
a first upper electrode covering the first dielectric layer;
the second dielectric layer at least covers part of the side wall of the lower electrode;
and the second upper electrode covers the second dielectric layer and the upper surface of the first upper electrode.
In some embodiments, the first dielectric layer and the second dielectric layer are different materials and/or different sizes.
In some embodiments, the dielectric constant of the first dielectric layer is equal to or less than 3.9, and the dielectric constant of the second dielectric layer is greater than 3.9.
In some embodiments, the width of the second dielectric layer is greater than or equal to the width of the first dielectric layer in a direction parallel to the substrate, and/or,
and in the direction vertical to the substrate, the height of the second dielectric layer is greater than or equal to that of the first dielectric layer.
In some embodiments, the opening dimension of the capacitive aperture is equal to or less than 25nm in a direction parallel to the substrate.
In some embodiments, the first dielectric layer covers side, bottom and top surfaces of the lower electrode and covers an upper surface of the support structure.
In some embodiments, the semiconductor structure further comprises a node contact plug located between the lower electrode and the substrate.
The embodiment of the disclosure provides a preparation method of a semiconductor structure and the semiconductor structure, wherein the method comprises the following steps: providing a substrate, wherein a support structure is formed on the substrate; forming a plurality of capacitive vias within the support structure; forming a lower electrode in the capacitor hole, wherein the lower electrode covers the side wall and the bottom of the capacitor hole; forming a first dielectric layer, wherein the first dielectric layer covers the surface of the lower electrode; forming a first upper electrode, wherein the first upper electrode covers the surface of the first dielectric layer; removing a part of the support structure positioned between the capacitor holes to form a containing cavity, wherein at least a part of the lower electrode is exposed out of the containing cavity, and the remained support structure is positioned on a part of the side wall of the lower electrode; forming a second dielectric layer, wherein the second dielectric layer covers the side wall and the bottom of the accommodating cavity; and forming a second upper electrode, wherein the second upper electrode covers the second dielectric layer and the upper surface of the first upper electrode. So, not only formed a sub-capacitor structure that is used for saving electric charge in the space that the electric capacity hole was injectd, and also formed another sub-capacitor structure that is used for saving electric charge in the space that forms after getting rid of partial bearing structure, two sub-capacitances are independent each other, and mutually support constitutes the capacitor structure jointly again, improve the space utilization of capacitor structure, show the surface area that has increased the capacitor structure to increase the storage capacity of capacitor structure to electric charge, increased the electric capacity of capacitor structure promptly. In addition, in the embodiment of the disclosure, the first dielectric layer and the second dielectric layer located inside and outside the lower electrode are formed in two steps, and the materials and the sizes of the two layers can be adjusted according to the actual situation, so that the limitation of the space size change on the finally formed semiconductor structure, namely the capacitor structure, is effectively avoided, and even under the condition of extreme size, the semiconductor structure can obtain higher capacitance under the condition of obtaining higher integration level.
The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the disclosure will be apparent from the description and drawings, and from the claims.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a flow chart diagram of a method for fabricating a semiconductor structure provided by an embodiment of the present disclosure;
fig. 2 to fig. 13 are process flow diagrams of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
fig. 14 is a schematic cross-sectional top view of the semiconductor structure provided in the embodiment of the disclosure along the direction A1-A2 in fig. 13.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without one or more of these specific details. In other instances, well-known features of the art have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.
In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" \8230; \8230 ";," - \8230;, "\8230"; "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to, or coupled to the other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "8230," "over," "with," "8230," "directly adjacent," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. And the discussion of a second element, component, region, layer or section does not necessarily imply that the first element, component, region, layer or section is necessarily present in the disclosure.
Spatial relationship terms such as "at 8230," "below," "at 8230," "below," "at 8230," "above," and the like may be used herein for convenience of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "at 8230; \8230; below" and "at 8230; \8230; below" may include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Generally, in an actual process, in order to improve the integration degree, the size of the capacitor hole is usually compressed, which causes the diameter of the capacitor hole to be greatly reduced. When the dielectric layers formed in the inner and outer spaces of the capacitor hole still adopt the same material and the same thickness, there is not enough space in the inner space of the capacitor hole to accommodate the dielectric layer and the upper electrode to be formed. In order to deal with the situation, an operator selects to fill all the electrode materials in the space defined by the capacitor hole, then expose the outer side wall of the electrode materials through an etching process, and then sequentially form a dielectric layer and the electrode materials on the side wall to form a capacitor structure. The method is suitable for the trend of the continuous shrinkage of the capacitor hole, but the capacitor structure formed in the inner space of the capacitor hole is sacrificed, so that the capacitance is reduced.
Therefore, how to obtain a semiconductor structure with larger capacitance while reducing the size of the capacitor hole becomes an unsolved problem.
Based on this, the following technical scheme of the embodiment of the disclosure is proposed:
the embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, as shown in fig. 1, the method includes the following steps:
step S101: providing a substrate, wherein a support structure is formed on the substrate;
step S102: forming a plurality of capacitor holes in the support structure;
step S103: forming a lower electrode in the capacitor hole, wherein the lower electrode covers the side wall and the bottom of the capacitor hole;
step S104: forming a first dielectric layer, wherein the first dielectric layer covers the surface of the lower electrode;
step S105: forming a first upper electrode, wherein the first upper electrode covers the surface of the first dielectric layer;
step S106: removing part of the support structure positioned between the capacitor holes to form an accommodating cavity, wherein at least part of the lower electrode is exposed out of the accommodating cavity, and the remained support structure is positioned on part of the side wall of the lower electrode;
step S107: forming a second dielectric layer, wherein the second dielectric layer covers the side wall and the bottom of the accommodating cavity;
step S108: and forming a second upper electrode, wherein the second upper electrode covers the second dielectric layer and the upper surface of the first upper electrode.
In the embodiment of the disclosure, not only is one sub-capacitor for storing charges formed in the space defined by the capacitor hole, but also another sub-capacitor for storing charges is formed in the space formed after part of the supporting structure is removed, the two sub-capacitors are independent from each other and mutually matched to form a capacitor structure, the space utilization rate of the capacitor structure is improved, the surface area of the capacitor structure is remarkably increased, the storage capacity of the capacitor structure to charges is increased, and the capacitance of the capacitor structure is increased. In addition, in the embodiment of the disclosure, the first dielectric layer and the second dielectric layer located inside and outside the lower electrode are formed in two steps, and the materials and the sizes of the two layers can be adjusted according to the actual situation, so that the limitation of the space size change on the finally formed semiconductor structure, namely the capacitor structure, is effectively avoided, and even under the condition of extreme size, the semiconductor structure can obtain higher capacitance under the condition of obtaining higher integration level.
In order to make the aforementioned objects, features and advantages of the present disclosure more comprehensible, embodiments accompanying the present disclosure are described in detail below. In describing the embodiments of the present disclosure in detail, the drawings are not to be taken as a general scale, and are for illustrative purposes only, and should not be taken as limiting the scope of the present disclosure.
Fig. 1 is a flow chart diagram of a method of fabricating a semiconductor structure provided by an embodiment of the present disclosure; fig. 2 to 13 are process flow diagrams of methods of fabricating semiconductor structures according to embodiments of the present disclosure; fig. 14 is a schematic cross-sectional top view of a semiconductor structure provided in an embodiment of the disclosure along the direction A1-A2 in fig. 13.
The following describes a method for fabricating a semiconductor structure according to an embodiment of the present disclosure in further detail with reference to the accompanying drawings.
First, step S101 is performed, as shown in fig. 2, providing a substrate 10, on which a support structure 11 is formed on the substrate 10.
Here, the material of the substrate may be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or the like, but is not limited thereto, and the substrate may be a silicon substrate on the surface of an insulator, a germanium substrate on the surface of an insulator, or the like. In some embodiments, the substrate may be a silicon substrate.
In a practical process, before forming the support structure 11 on the substrate 10, the method further comprises:
forming an insulating layer 12 on the substrate;
etching the insulating layer 12 to form a plurality of discrete openings (not identified in the figure) in the insulating layer 12;
a plurality of discrete node contact plugs 14 are formed in the openings (not identified).
Alternatively, the material for forming the node contact plug may include, but is not limited to, one or a combination of polysilicon, metal silicide, conductive metal nitride, and the like. Specifically, the metal silicide may be, but is not limited to, cobalt silicide (CoSix) and the like; the conductive metal may include, but is not limited to, tungsten (W), etc.; the conductive metal nitride may include, but is not limited to, titanium nitride (TiN) and the like.
With continued reference to fig. 2, in some embodiments, after forming the node contact plugs 14, the support junctions 11 are formed, including:
providing a substrate 10;
forming a sacrificial layer 15 on the substrate 10, the sacrificial layer 15 covering the surfaces of the insulating layer 12 and the node contact plugs 14;
forming a first support layer 111 on the sacrificial layer 15, the first support layer 111 covering the surface of the sacrificial layer;
forming a sacrificial layer 15 on the first support layer 111, the sacrificial layer 15 covering the surface of the first support layer 111;
forming a second support layer 112 on the sacrificial layer 15, the second support layer 112 covering the surface of the sacrificial layer 15;
wherein the first support layer 111 and the second support layer 112 constitute the support structure 11.
In practical processes, the material forming the sacrificial layer may include, but is not limited to, siO treated with an organic solution (PGS, BPSG, TEOS or HDP) 2 Etc.; the material forming the first and second support layers may include, but is not limited to, si 3 N 4 Or SiCN, etc.
Next, step S102 is performed, as shown in fig. 3, to form a plurality of capacitor holes H1 in the supporting structure 11.
Here, the capacitor hole H1 exposes the node contact plug 14, and when other conductive structures, such as a lower electrode, are subsequently formed in the capacitor hole H1, the node contact plug 14 may be used to electrically connect the conductive structures in the capacitor hole with other structures, such as a transistor structure.
In some specific embodiments, the opening size of the capacitor hole H1 in the direction parallel to the substrate may be less than or equal to 25nm, such as 20nm and 15nm, so as to meet the requirement that the process size of a memory device, such as a DRAM device, gradually approaches to the limit, and improve the device integration level.
In an actual process, an etching process may be used to form the capacitor hole, specifically, at least one of a dry etching process or a wet etching process or a combination thereof.
Next, step S103 is performed, as shown in fig. 5, a lower electrode is formed in the capacitor hole, and the lower electrode covers the sidewall and the bottom of the capacitor hole.
In some specific embodiments, as shown in fig. 4 and 5, the lower electrode 13 is formed inside the capacitor hole H1, and includes:
depositing an electrode material 13a, wherein the electrode material 13a covers the side wall and the bottom of the capacitor hole H1 and covers the upper surface of the support structure 11;
an etching process is performed to remove the electrode material 13a on the upper surface of the support structure 11, and the electrode material 13a remaining on the sidewall and bottom of the capacitor hole H1 constitutes the lower electrode 13.
In some embodiments, the material of the lower electrode may include one or more conductive materials, such as doped semiconductors, conductive metal nitrides, metals, metal silicides, conductive oxides, or combinations thereof, e.g., one or a combination of polysilicon, titanium nitride, tantalum nitride, tungsten, and the like.
Here, the material of the lower electrode may include, but is not limited to, titanium nitride, etc.
Next, step S104 is performed, as shown in fig. 6, a first dielectric layer L1 is formed, and the first dielectric layer L1 covers the surface of the lower electrode 13.
With continued reference to fig. 6, it can be seen that the first dielectric layer L1 covers the side, bottom and top surfaces of the lower electrode 13 and covers the upper surface of the support structure between adjacent capacitor holes H1.
Here, the material of the first dielectric layer includes a low dielectric constant material, such as at least one of silicon carbide, silicon carbonitride (SiCN), silicon oxycarbide (SiCO), silicon oxide, and the like, or a combination thereof.
Then, step S105 is performed, as shown in fig. 7, to form a first upper electrode 161, wherein the first upper electrode 161 covers the surface of the first dielectric layer L1.
Alternatively, the material of the first upper electrode may be the same as or different from that of the lower electrode, and is not limited herein.
Next, step S106 is performed, as shown in fig. 10, a portion of the supporting structure 11 located between the capacitor holes H1 is removed to form a receiving cavity H2, the receiving cavity H2 exposes at least a portion of the lower electrode 13, and the remaining supporting structure 11 is located on a portion of the sidewall of the lower electrode 13.
In the embodiment of the present disclosure, the size of the accommodating cavity H2 may be greater than or equal to the size of the capacitor hole H1 in the manufacturing process, and may be, for example, 30nm, 50nm, and the like.
In some specific embodiments, it is worth explaining, while the size of the accommodating cavity H2 is gradually reduced to the limit by continuously reducing the size of the capacitor hole H1 to adapt to the process size of the semiconductor memory device, the size of the accommodating cavity H2 can be ensured to be free from influence, in the embodiments of the present disclosure, a complete capacitor is formed in the capacitor hole H1, then the accommodating cavity H2 is formed, and another capacitor is formed by an independent process, so that the sizes of the capacitor hole H1 and the accommodating cavity H2 can be adapted to control and adjust the performance (e.g., capacitance value, electrical performance) of the two capacitors, for example, different dielectric layer materials are selectively deposited, and different dielectric layer sizes are selected, thereby realizing the balance between the capacitance and the electrical performance of the final capacitor structure.
In some embodiments, as shown in fig. 8 to 10, removing a portion of the support structure 11 located between the capacitor holes H1 to form a receiving cavity H2 includes:
forming a mask layer M on the first upper electrode 161, wherein the mask layer M comprises an etching window H3, and the orthographic projection of the etching window H3 on the substrate 10 is overlapped with the orthographic projection of part of the support structure 11 on the substrate 10;
the first upper electrode 161, the first dielectric layer L1 and the support structure 11 exposed by the etching window H3 are etched to form a receiving cavity H2, the receiving cavity H2 at least exposes a portion of the lower electrode 13, and the support structure 11 not etched covers a portion of the sidewall of the lower electrode 13.
Here, after etching part of the support structure, part of the outer sidewall of the lower electrode is exposed, and the remaining support structure is also located on the outer sidewall of the lower electrode.
In an actual process, as shown in fig. 9 and 10, after etching the first upper electrode 161, the first dielectric layer L1 and the support structure 11 exposed by the etching window H3, an initial accommodating cavity H2' may be obtained; next, the housing cavity H2 may be obtained by a step of removing the sacrificial layer 15 located around the initial housing cavity H2'.
In an actual process, the accommodating cavity may be formed by an etching process, such as at least one of a dry etching process or a wet etching process or a combination thereof.
Next, continuing to step S107, as shown in fig. 12, a second dielectric layer L2 is formed, and the second dielectric layer L2 covers the sidewalls and the bottom of the accommodating chamber H2.
In some embodiments, as shown in fig. 11 and 12, forming the second dielectric layer L2 includes:
depositing a dielectric material L2a, wherein the dielectric material L2a covers the side wall and the bottom of the accommodating cavity H2 and covers the upper surface of the first upper electrode 161;
and performing an etching process to remove the portion of the dielectric material L2a covering the upper surface of the first upper electrode 161, wherein the remaining dielectric material L2a constitutes the second dielectric layer L2.
In some embodiments, the height of the second dielectric layer is greater than or equal to the height of the first dielectric layer in a direction perpendicular to the substrate, for example, the upper surface of the second dielectric layer L2 is higher than the upper surface of the first dielectric layer L1.
It can be understood that, unlike the conventional process in which the first dielectric layer and the second dielectric layer are formed in a single structure and in the same process step, when the first dielectric layer and the second dielectric layer are formed in different process steps, it is easy to cause a short circuit in the position where the first dielectric layer and the second dielectric layer are joined due to the fact that the joining is not tight enough, so that the lower electrode and the subsequently formed upper electrode are directly and electrically connected.
Therefore, in the embodiment of the present disclosure, after the second dielectric layer covering the sidewall and the bottom of the accommodating cavity and covering the upper surface of the first upper electrode is formed, the second dielectric layer having a higher height than the first dielectric layer is obtained by removing only the second dielectric layer on the upper surface of the first upper electrode without continuously etching the second dielectric layer near the top surface of the accommodating cavity.
Here, the second dielectric layer includes a high dielectric constant material, and in particular, the material of the second dielectric layer may include, but is not limited to, aluminum oxide (Al) 2 O 3 ) Tantalum oxide (Ta) 2 O 3 ) Titanium oxide (TiO) 2 ) Yttrium oxide (Y) 2 O 3 ) Zirconium oxide (ZrO) 2 ) Zirconium silicon oxide (ZrSixOy), hafnium oxide (HfO) 2 ) Hafnium silicon oxide (HfSixOy), hafnium silicon oxynitride (HfSiON), hafnium zirconate (HfZrO) 4 ) Lanthanum oxide (La) 2 O 3 ) Lanthanum aluminum oxide (LaAlxOy), lanthanum hafnium oxide (LaHfxOy), hafnium aluminum oxide (HfAlxOy) and/or praseodymium oxide (Pr) 2 O 3 ) And the like, or combinations thereof.
It can be understood that, since the first dielectric layer L1 and the second dielectric layer L2 are formed in two different process steps, the first dielectric layer L1 and the second dielectric layer L2 may have different materials and different sizes according to different specific situations in actual operation.
For example, in some embodiments, as the process dimension tends to be limited, the capacitor hole H1 tends to have a smaller dimension than the accommodating cavity H2, the dielectric constant of the first dielectric layer is, for example, 3.9 or less, such as silicon dioxide, and the dielectric constant of the second dielectric layer is greater than 3.9, such as hafnium oxide. It can be understood that the shrinking dimensions tend to result in a significant reduction in the size of the capacitor hole, which may lead to an increase in leakage current and affect the performance of the semiconductor structure if a high-k material is formed therein. Therefore, it is preferable to use a low dielectric constant material for the first dielectric layer to ensure electrical performance. At this time, since the second dielectric layer is located in the space formed after the support structure is etched, the second dielectric layer is formed in the space having a larger surface area than the first dielectric layer, and when a high dielectric constant material is used, leakage current is not easily generated, and thus, the second dielectric layer can use the high dielectric constant material to increase capacitance.
In some embodiments, the width of the second dielectric layer is greater than or equal to the width of the first dielectric layer in a direction parallel to the substrate.
In this way, by setting the first dielectric layer and the second dielectric layer to have different widths, for example, the width of the first dielectric layer is smaller than that of the second dielectric layer, the requirement of a structure for storing charges in both spaces can be obtained under the condition of size reduction or limit size, so as to improve the capacitance of the finally formed semiconductor structure.
It is not limited to this, and it can be understood that, in some other embodiments, the width of the first dielectric layer may also be equal to or greater than the width of the second dielectric layer, and may be flexibly adjusted according to the actual situation.
Finally, step S108 is performed, as shown in fig. 13 and 14, a second upper electrode 162 is formed, and the second upper electrode 162 covers the second dielectric layer L2 and the upper surface of the first upper electrode 161.
Here, the second upper electrode 162 and the first upper electrode 161 together constitute the upper electrode 16. The materials of the second upper electrode 162 and the first upper electrode 161 may be the same or different, and in some specific embodiments, the materials of the second upper electrode 162 and the first upper electrode 161 include, but are not limited to, titanium nitride, and the like.
Thus, the structures for storing charge are formed in both the space defined by the capacitor holes and the space formed after etching the support structure.
Here, the lower electrode 13, the first dielectric layer L1, and the first upper electrode 161 form one sub-capacitor, the lower electrode 13, the second dielectric layer L2, and the second upper electrode 162 form another sub-capacitor, and the two sub-capacitors share the lower electrode and form a capacitor structure C.
In summary, it can be seen that, in the embodiment of the disclosure, since the first dielectric layer and the second dielectric layer are respectively formed in two different steps, the size and the material of the first dielectric layer located in the space defined by the capacitor hole can be flexibly selected and adjusted according to actual situations, so that a structure for storing charges can be finally formed in the space defined by the capacitor hole. And the material and the thickness of the second dielectric layer in the space formed after the partial support structure is removed are not limited by the size of the capacitor hole and the size of the space, and the second dielectric layer can be normally formed and even can be adjusted according to actual conditions. Compared with the conventional technology, the embodiment of the disclosure can significantly improve the flexibility of the formation process of the semiconductor structure, and can effectively improve the capacitance of the semiconductor structure under the limit size.
The embodiment of the present disclosure also provides a semiconductor structure, as shown in fig. 13 and 14, including:
the capacitor comprises a substrate 10 and a support structure 11 positioned on the substrate 10, wherein the support structure is provided with a plurality of capacitor holes H1;
the lower electrode 13 is separately arranged in the plurality of capacitor holes H1, and the support structure 11 is positioned on part of the side wall of the lower electrode 13;
the first dielectric layer L1, the first dielectric layer L1 covers the surface of the bottom electrode 13;
a first upper electrode 161, the first upper electrode 161 covering the first dielectric layer L1;
the second dielectric layer L2, the second dielectric layer L2 covers at least some sidewalls of the bottom electrode 13;
and a second upper electrode 162, the second upper electrode 162 covering the upper surfaces of the second dielectric layer L2 and the first upper electrode 161.
In some specific embodiments, the opening size of the capacitor hole H1 in the direction parallel to the substrate may be less than or equal to 25nm, such as 20nm and 15nm, so as to meet the requirement that the process size of a memory device, such as a DRAM device, gradually approaches to the limit, and improve the device integration level.
Here, the lower electrode 13, the first dielectric layer L1, and the first upper electrode 161 form one sub-capacitor, the lower electrode 13, the second dielectric layer L2, and the second upper electrode 162 form another sub-capacitor, and the two sub-capacitors share the lower electrode and form a capacitor structure C together.
That is to say, the embodiment of the present disclosure provides the capacitor structures in the space defined by the capacitor holes and the space formed after the support structure is etched, so that the capacitance of the semiconductor structure can be effectively improved.
In actual process, the material of the substrate may be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or the like, but is not limited thereto, and the substrate may also be a silicon substrate on the surface of an insulator, a germanium substrate on the surface of an insulator, or the like. In some embodiments, the substrate may be a silicon substrate.
Alternatively, the material of the lower electrode 13 may include one or more conductive materials, such as doped semiconductors, conductive metal nitrides, metals, metal silicides, conductive oxides or combinations thereof, for example, one or a combination of polysilicon, titanium nitride, tantalum nitride, tungsten, and the like. In some embodiments, the material of the bottom electrode 13 includes, but is not limited to, titanium nitride, etc.
It is understood that the material of the second upper electrode 162 and the first upper electrode 161 may be the same or different, and in some specific embodiments, the material of the second upper electrode 162 and the first upper electrode 161 includes, but is not limited to, titanium nitride, etc.
With continued reference to fig. 13, it can be seen that the first dielectric layer L1 covers the side, bottom and top surfaces of the lower electrode 13 and covers the upper surface of the support structure 11.
In some embodiments, the height of the second dielectric layer is greater than or equal to the height of the first dielectric layer in the direction perpendicular to the substrate, for example, the upper surface of the second dielectric layer L2 is higher than the upper surface of the first dielectric layer L1.
It can be understood that, unlike the conventional structure in which the first dielectric layer and the second dielectric layer are an integral structure and are formed in the same step, the two dielectric layers in the embodiment of the present disclosure are two separately disposed portions, one portion is the first dielectric layer located on the side surface, the bottom surface, and the upper surface of the lower electrode, and the other portion is the second dielectric layer located on the outer sidewall of the lower electrode portion, and there is a joint between the two at the sidewall position where the first dielectric layer is located on the upper surface portion of the lower electrode.
In addition, in the actual process, the upper surface of the second dielectric layer is higher than the upper surface of the first dielectric layer, so that the etching time for forming the second dielectric layer can be effectively reduced, and the process is simplified.
Since the first dielectric layer L1 and the second dielectric layer L2 have mutual independence in the embodiments of the present disclosure, it can be understood that, in some embodiments, the first dielectric layer L1 and the second dielectric layer L2 are different in material and/or different in size.
In an actual process, the dielectric constant of the first dielectric layer L1 is less than or equal to 3.9, and the dielectric constant of the second dielectric layer is greater than 3.9.
Optionally, in some embodiments, the material of the first dielectric layer includes, but is not limited to, at least one of silicon carbide, silicon carbonitride (SiCN), silicon oxycarbide (SiCO), silicon oxide, and the like, or a combination thereof; the material of the second dielectric layer may include, but is not limited to, aluminum oxide (Al) 2 O 3 ) Tantalum oxide (Ta) 2 O 3 ) Titanium oxide (TiO) 2 ) Yttrium oxide (Y) 2 O 3 ) Zirconium oxide (ZrO) 2 ) Zirconium silicon oxide (ZrSixOy), hafnium oxide (HfO) 2 ) Hafnium silicon oxide (HfSixOy), hafnium silicon oxynitride (HfSiON), hafnium zirconate (HfZrO) 4 ) Lanthanum oxide (La) 2 O 3 ) Lanthanum aluminum oxide (LaAlxOy), lanthanum hafnium oxide (LaHfxOy), hafnium aluminum oxide (HfAlxOy) and/or praseodymium oxide (Pr) 2 O 3 ) And the like, or combinations thereof.
Here, it can be understood that, due to the size shrinkage, the size of the capacitor hole is easily reduced, and if the first dielectric layer disposed therein is a high-k material, the leakage current is easily increased, which affects the performance of the semiconductor structure. Therefore, it is preferable to use a low dielectric constant material for the first dielectric layer. At this time, since the second dielectric layer is located in the space formed after the support structure is etched, compared with the first dielectric layer, the second dielectric layer is disposed in the space having a larger surface area, and when a high dielectric constant material is used, leakage current is not easily generated, and therefore, the second dielectric layer can be made of the high dielectric constant material to increase capacitance.
Optionally, in some embodiments, in a direction parallel to the substrate, a width of the second dielectric layer is greater than or equal to a width of the first dielectric layer.
Therefore, the first dielectric layer and the second dielectric layer are arranged to have different widths, for example, the width of the first dielectric layer L1 is smaller than that of the second dielectric layer L2, so that the requirement of a capacitor structure is obtained in two spaces under the condition of size reduction or limit size, and the capacitance of the finally formed semiconductor structure is improved.
It is not limited to this, and it can be understood that, in some other embodiments, the width of the first dielectric layer may also be equal to or greater than the width of the second dielectric layer, and may be flexibly adjusted according to the actual situation.
With continued reference to fig. 13, it can be seen that in some embodiments, the semiconductor structure further includes a node contact plug 14, the node contact plug 14 being located between the lower electrode 13 and the substrate 10.
In addition, in the embodiment of the present disclosure, an insulating layer 12 is further disposed between adjacent contact plugs 14, and the insulating layer 12 plays a role of isolation between the adjacent contact plugs 14.
Alternatively, the material for forming the node contact plug may include, but is not limited to, one or a combination of polysilicon, metal silicide, conductive metal nitride, and the like. Specifically, the metal silicide may be, but is not limited to, cobalt silicide (CoSix) or the like; the conductive metal may include, but is not limited to, tungsten (W), etc.; the conductive metal nitride may include, but is not limited to, titanium nitride (TiN) and the like.
In summary, in the embodiment of the disclosure, since the first dielectric layer and the second dielectric layer are formed in two different steps, the size and the material of the first dielectric layer located in the space defined by the capacitor hole can be flexibly selected and adjusted according to the actual situation, so that the structure for storing charges can be finally formed in the space defined by the capacitor hole. And the material and the thickness of the second dielectric layer in the space formed after the partial support structure is removed are not limited by the size of the capacitor hole and the size of the space, and the second dielectric layer can be normally formed and even can be adjusted according to actual conditions. Compared with the conventional technology, the embodiment of the disclosure can significantly improve the flexibility of the formation process of the semiconductor structure, and can also effectively improve the capacitance of the semiconductor structure under the limit size.
It should be noted that the method for manufacturing a semiconductor device provided in the embodiments of the present disclosure may be applied to a DRAM structure or other semiconductor devices, and is not limited herein. The embodiment of the semiconductor device preparation method provided by the disclosure and the embodiment of the semiconductor device belong to the same concept; the technical features of the technical means described in the embodiments may be arbitrarily combined without conflict.
The above description is meant to be illustrative of the preferred embodiments of the present disclosure and should not be taken as limiting the scope of the disclosure, which is intended to include all modifications, equivalents, and improvements made within the spirit and scope of the present disclosure.
Claims (15)
1. A method for fabricating a semiconductor structure, comprising:
providing a substrate, wherein a support structure is formed on the substrate;
forming a plurality of capacitive holes in the support structure;
forming a lower electrode in the capacitor hole, wherein the lower electrode covers the side wall and the bottom of the capacitor hole;
forming a first dielectric layer, wherein the first dielectric layer covers the surface of the lower electrode;
forming a first upper electrode, wherein the first upper electrode covers the surface of the first dielectric layer;
removing a part of the support structure positioned between the capacitor holes to form a containing cavity, wherein at least a part of the lower electrode is exposed out of the containing cavity, and the remained support structure is positioned on a part of the side wall of the lower electrode;
forming a second dielectric layer, wherein the second dielectric layer covers the side wall and the bottom of the accommodating cavity;
and forming a second upper electrode, wherein the second upper electrode covers the second dielectric layer and the upper surface of the first upper electrode.
2. The method of claim 1, wherein the first dielectric layer and the second dielectric layer are different materials and/or different sizes.
3. The method of claim 2, wherein the dielectric constant of the material of the first dielectric layer is equal to or less than 3.9, and the dielectric constant of the second dielectric layer is greater than 3.9.
4. A method according to claim 2 or 3, characterized in that the width of the second dielectric layer is equal to or greater than the width of the first dielectric layer in a direction parallel to the substrate, and/or,
and in the direction vertical to the substrate, the height of the second dielectric layer is greater than or equal to that of the first dielectric layer.
5. The method of claim 1, wherein the opening size of the capacitive hole is 25nm or less in a direction parallel to the substrate.
6. The method of claim 1, wherein forming a lower electrode within the capacitive hole comprises:
depositing an electrode material covering the sidewalls and bottom of the capacitor hole and covering the upper surface of the support structure;
and performing an etching process to remove the electrode material on the upper surface of the support structure, wherein the electrode material remained on the side wall and the bottom of the capacitor hole forms a lower electrode.
7. The method of claim 6, wherein removing portions of the support structure between the capacitor holes to form a receiving cavity comprises:
forming a mask layer on the first upper electrode, wherein the mask layer comprises an etching window, and the orthographic projection of the etching window on the substrate is overlapped with the orthographic projection of part of the supporting structure on the substrate;
and etching the first upper electrode, the first dielectric layer and the support structure exposed by the etching window to form the accommodating cavity, wherein at least part of the lower electrode is exposed by the accommodating cavity, and the part of the side wall of the lower electrode is covered by the support structure which is not etched.
8. The method of claim 7, wherein forming a second dielectric layer comprises:
depositing a dielectric material, wherein the dielectric material covers the side wall and the bottom of the accommodating cavity and covers the upper surface of the first upper electrode;
and performing an etching process to remove the part of the dielectric material covering the upper surface of the first upper electrode, wherein the retained dielectric material forms a second dielectric layer.
9. A semiconductor structure, comprising:
the device comprises a substrate and a support structure positioned on the substrate, wherein a plurality of capacitance holes are formed in the support structure;
a lower electrode discretely disposed in the plurality of capacitor holes, the support structure being located on a portion of a sidewall of the lower electrode;
the first dielectric layer covers the surface of the lower electrode;
a first upper electrode overlying the first dielectric layer;
the second dielectric layer at least covers part of the side wall of the lower electrode;
and the second upper electrode covers the second dielectric layer and the upper surface of the first upper electrode.
10. The structure of claim 9, wherein the first dielectric layer and the second dielectric layer are different materials and/or different sizes.
11. The structure of claim 10, wherein the dielectric constant of the first dielectric layer is equal to or less than 3.9, and the dielectric constant of the second dielectric layer is greater than 3.9.
12. The structure of claim 9 or 10, characterized in that the width of the second dielectric layer is greater than or equal to the width of the first dielectric layer in a direction parallel to the substrate, and/or,
and in the direction vertical to the substrate, the height of the second dielectric layer is greater than or equal to that of the first dielectric layer.
13. The structure of claim 9, wherein the opening dimension of the capacitive aperture is 25nm or less in a direction parallel to the substrate.
14. The structure of claim 9, wherein the first dielectric layer covers side, bottom and top surfaces of the lower electrode and covers an upper surface of the support structure.
15. The structure of claim 14, further comprising a node contact plug between the lower electrode and the substrate.
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| CN202210975666.3A CN115312465A (en) | 2022-08-15 | 2022-08-15 | Preparation method of semiconductor structure and semiconductor structure |
| PCT/CN2022/123996 WO2024036722A1 (en) | 2022-08-15 | 2022-10-09 | Semiconductor structure manufacturing method and semiconductor structure |
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| KR101810531B1 (en) * | 2011-11-23 | 2017-12-20 | 삼성전자 주식회사 | Semiconductor device and method of manufacturing the same |
| CN108010913B (en) * | 2017-12-29 | 2023-07-18 | 长鑫存储技术有限公司 | Semiconductor memory structure and preparation method thereof |
| CN108717936A (en) * | 2018-06-27 | 2018-10-30 | 长鑫存储技术有限公司 | Double sided capacitor structure and preparation method thereof |
| CN112908968B (en) * | 2019-12-03 | 2022-06-10 | 长鑫存储技术有限公司 | Capacitor in semiconductor memory and method for fabricating the same |
| CN114078777A (en) * | 2020-08-13 | 2022-02-22 | 长鑫存储技术有限公司 | Semiconductor structure forming method and semiconductor structure |
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