KR100449558B1 - Charge pump circuit - Google Patents

Abstract

The present invention relates to a charge pump circuit, comprising: a pumping circuit for pumping a power supply voltage according to at least one clock signal, a reference voltage generating circuit for generating a reference voltage, and a sector for programming according to an address signal A sector information signal generation circuit for generating at least one sector information signal, and a regulation circuit for regulating a pumping voltage from the pumping circuit according to the reference voltage and the sector information signal to output various voltages according to sectors; The present invention provides a charge pump circuit capable of generating a pumping voltage of various levels with one power supply voltage, thereby preventing a decrease in program efficiency due to a loading effect according to the distance between the charge pump circuit and the sector.

Description

Charge pump circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump circuit. In particular, a charge pump circuit capable of generating a pumping voltage of various levels with one power supply voltage can prevent a decrease in program efficiency due to a loading effect according to a distance between the charge pump circuit and a sector. It is about.

In general, a flash memory cell can secure nonvolatile characteristics, electrical erase, and program characteristics at the same time. This advantage is applied to various semiconductor memory devices. Such flash memory cells block a plurality of blocks to form a plurality of sectors, and a flash memory device including a plurality of peripheral circuits is configured to select and drive one sector and a cell included therein among the plurality of sectors. In order to select and drive one cell in such a flash memory device, one cell is selected by an address signal according to driving, that is, a sector address signal for selecting a sector, a bit line for selecting a cell of a sector, and a word line address signal. Driven. For example, in order to implement a program for storing data in a flash memory cell, a positive high voltage must be applied to a gate terminal and a drain terminal of the cell, respectively.

FIG. 1 is a schematic diagram of a circuit for applying a voltage of 9V to a gate terminal of a cell and 5V to a drain terminal using two charge pump circuits to program a flash memory cell. The first charge pump circuit 11 is driven in accordance with the enable signal EN to distribute the outputs of the first pumping circuit and the first pumping circuit for generating a high voltage for application to the gate terminal of the cell and reference the divided voltage. And a first regulation circuit that regulates the output of the first pumping circuit to a constant level compared to the voltage. The second charge pump circuit 12 is driven in accordance with the enable signal EN to distribute the outputs of the second pumping circuit and the second pumping circuit for generating a high voltage for application to the drain terminal of the cell and reference the divided voltage. And a second regulation circuit that regulates the output of the second pumping circuit to a constant level compared to the voltage. On the other hand, the reference voltage generator 13 is driven according to the enable signal EN to generate a reference voltage as a reference when the first and second regulation circuits regulate the outputs of the first and second pumping circuits.

The circuit for programming the flash memory cell configured as described above generates a high voltage using one power supply voltage. However, as shown in FIG. 2, the sectors 0 through 14 are configured in the same size, and the flash memory device includes a plurality of sectors in which the size sum of the sectors 15 through 18 is the same as one of the remaining sectors. Even though a high voltage is applied in the charge pump circuit to program the cell, the voltage actually applied to the cell is reduced by the intermediate loading effect while reaching the cell. That is, the sector is located farther from the charge pump circuit, the voltage is reduced and applied by the line resistance that increases with distance. This phenomenon occurs by generating and supplying only one voltage level without considering the structure of the flash memory device, and is more remarkable as the capacity of the flash memory device is increased. This reduces the program efficiency of the cell and, in more severe cases, causes a program failure due to a drop in the voltage level.

SUMMARY OF THE INVENTION An object of the present invention is to provide a charge pump circuit capable of generating pumping voltages of various levels according to the position of a sector using sector information according to the position of the sector at the time of pumping.

Another object of the present invention is to provide a charge pump circuit capable of generating pumping voltages of various levels, thereby increasing program efficiency regardless of the position of a sector.

1 is a schematic diagram of a circuit for programming a typical flash memory cell.

2 is a schematic diagram of a flash memory device divided into a plurality of sectors.

3 is a configuration diagram of a charge pump circuit according to a first embodiment of the present invention.

4 (a) and 4 (b) is an example of the pumping circuit applied to the present invention and its operation waveform diagram.

5 is a regulation circuit diagram applied to a first embodiment of the present invention.

FIG. 6 is a first sense amplifier circuit diagram applied to the regulation circuit of FIG. 5. FIG.

FIG. 7 is a second sense amplifier circuit diagram applied to the regulation circuit of FIG. 5. FIG.

8 is a reference voltage generation circuit diagram applied to a first embodiment of the present invention.

9 is a configuration diagram of a charge pump circuit according to a second embodiment of the present invention.

10 is a regulation circuit diagram applied to a second embodiment of the present invention.

11 is a reference voltage generation circuit diagram applied to a second embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

31 and 91: pumping circuit 32 and 92: regulation circuit

33 and 93: reference voltage generating circuit 34 and 94: sector information generating circuit

According to an embodiment of the present invention, a charge pump circuit may include a pumping circuit for pumping a power supply voltage according to at least one clock signal, a reference voltage generation circuit for generating a reference voltage, and a sector for programming according to an address signal. Regulating a sector information signal generation circuit for generating at least one sector information signal to select, and a pumping voltage from the pumping circuit to adjust a bias level according to the sector to be programmed according to the reference voltage and the sector information signal. Characterized in that it comprises a regulation circuit for.

According to another embodiment of the present invention, a charge pump circuit may include a pumping circuit for pumping a power supply voltage according to at least one clock signal, and at least one sector information signal for selecting a sector for programming according to an address signal. A sector information signal generation circuit, a reference voltage generation circuit for adjusting and generating a reference voltage such that a bias level according to the sector to be programmed is adjusted according to the sector information signal, and a pumping voltage from the pumping circuit to the reference voltage. It characterized in that it comprises a regulation circuit for regulating accordingly.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the present disclosure and to those skilled in the art. It is provided to fully inform the scope of the invention. In addition, in the drawings, like reference numerals refer to like elements.

3 is a block diagram illustrating a schematic configuration of a charge pump circuit according to a first exemplary embodiment of the present invention.

The pumping circuit 31 is driven by the enable signal EN to generate a high voltage according to the first and second clock signals CLK1 and CLK2. The reference voltage generating circuit 33 is driven according to the enable signal EN to generate a predetermined reference voltage VREF. The regulation circuit 32 is driven according to the enable signal EN to regulate the output of the pumping circuit 31 according to the reference voltage VREF and the sector information signals SEC0 to SEC18. The sector information signals SEC0 to SEC18 are generated from the sector information generation circuit 34 using the address signals A <12:18> and are signals for selecting a sector for programming.

The charge pump circuit according to the first embodiment of the present invention configured as described above adjusts the regulation level in the regulation circuit 32 according to the sector information signals SEC0 to SEC18 from the sector information generation circuit 34. That is, when programming a sector located close to the charge pump circuit 31, the bias level is regulated to be lowered in consideration of the line resistance, and when programming a sector located far from the charge pump circuit, the bias is considered in consideration of the line resistance. Regulate to raise the level. By doing so, it is possible to prevent a decrease in the bias level due to line resistance or the like depending on the distance of the sector.

4A is a schematic diagram of a pumping circuit applied to a charge pump circuit according to a first embodiment of the present invention, and is configured as follows.

A first NMOS transistor N41 driven according to the enable signal EN is connected between the power supply terminal VDD and the first node Q41. The second NMOS transistor N42 is diode-connected between the first node Q41 and the second node Q42, and the third NMOS transistor N43 is connected between the second node Q42 and the third node Q43. Diode is connected. The fourth NMOS transistor N44 is diode-connected between the third node Q43 and the fourth node Q44, and the fifth NMOS transistor N45 is connected between the fourth node Q44 and the output terminal PUMP_OUT. Is diode connected. In addition, each of the nodes Q41 to Q44 and the output terminal PUMP_OUT is charged with the first and second clock signals CLK1 and CLK2 inverted by the first and second inverters I41 and I42, respectively. To fifth capacitors C41 to C45 are connected. That is, the first, third and third charges are charged to the first node Q41, the third node Q43 and the output terminal PUMP_OUT by the second clock signal CLK2 inverted by the second inverter I42. Five capacitors C41, C43, and C45 are connected, respectively, and the second and fourth nodes Q42 and Q44 are charged with the first clock signal CLK1 inverted by the first inverter I41. Fourth capacitors C42 and C44 are connected, respectively.

The driving method of the pumping circuit constituting the charge pump circuit according to the present invention configured as described above will be described with reference to the operation timing diagram shown in FIG.

When the enable signal EN is applied in a high state, the first NMOS transistor N41 is turned on to supply the power supply voltage VDD. The first and second clock signals CLK1 and CLK2 having opposite phases are inverted through the first and second inverters I41 and I42, respectively, to charge the first to fifth capacitors C41 to C45. . That is, the second clock signal CLK2 applied in the low state is inverted to the high state through the second inverter I42 to charge the first, third, and fifth capacitors C41, C43, and C45 so as to charge the first and third capacitors. The third nodes Q41 and Q43 and the output terminal PUMP_OUT are raised to a predetermined potential. In addition, the first clock signal CLK1 applied in the low state is inverted to the high state through the first inverter I41 to charge the second and fourth capacitors C42 and C44 so as to charge the second and fourth nodes Q42. And Q44) is raised to a predetermined potential. The potential of the node thus raised is transferred to the next stage through the diode-connected second to fifth NMOS transistors N42 to N45, and finally, the output terminal PUMP_OUT maintains a predetermined potential. It depends on the power supply voltage VDD and the number of capacitors and their capacity.

5 is a regulation circuit diagram applied to the charge pump circuit according to the first embodiment of the present invention.

The first sense amplifier 51 driven according to the enable signal EN compares the reference voltage Vref with the input voltage VIN and outputs the result. The first to nth resistors R51 to R5n serving as voltage distribution means are connected between the first sense amplifier 51 and the ground terminal Vss. The first to nth resistors R51 to R5n and the first to nth resistors R51 to R5n are connected. The voltage divided by the resistor R51 is fed back to become the input voltage VIN of the first sense amplifier 51. Further, the first to mth NMOS transistors N51 to N5m respectively driven in accordance with the plurality of sector information signals SEC15 to SEC0 are connected to each connection point of the second resistor R52 and the nth resistor R5n. For example, the first NMOS transistor N51 driven according to the nineteenth sector information signal SEC18 is connected between the second resistor R52 and the third resistor R53, and the mth resistor R5m and the nth resistor are connected. The mth NMOS transistor N5m driven in accordance with the first sector information signal SEC0 is connected between R5n. Here, the sector information signals SEC0 to SEC18 are signals for programming the selected sector. For example, the first sector information signal SEC0 is a signal for programming the first sector located closest to the charge pump circuit. The nineteen sector information signal SEC18 is a signal for programming the nineteenth sector located farthest from the charge pump circuit. For example, when the nineteenth sector information signal SEC18 is applied to the high state to program the nineteenth sector, and the first to eighteenth sector information signals SEC0 to SEC17 are applied to the low state, the first NMOS transistor ( Since N51 is turned on and the remaining transistors are turned off, the voltage divided according to the ratio of the first to nth resistors R51 to R5n and the first and second resistors R51 and R52 is adjusted to the regulating reference voltage REG_REF. Becomes In addition, when the first sector information signal SEC0 is applied to the high state to program the first sector and the second to nineteenth sector information signals SEC1 to SEC18 are applied to the low state, the mth NMOS transistor N5m is applied. Is turned on and the remaining transistors are turned off, so that the voltage divided according to the ratio of the first to nth resistors R51 to R5n and the first to mth resistors R51 to R5m becomes the adjustment reference voltage REG_REF. .

The second sense amplifier 52 is driven according to the enable signal EN, and compares the regulating reference voltage REG_REF with the level voltage REGLEVEL regulated by the diode chain and accordingly results in the output voltage of the pumping circuit ( PUMP_OUT). The PMOS transistor P50 is driven according to the output of the second sense amplifier 52 to output the output voltage PUMP_OUT of the pumping circuit to the output terminal VPPD. Between the output terminal VPPD and the ground terminal Vss, a diode chain in which a plurality of PMOS transistors P51 to P54 are diode-connected and an NMOS transistor N50 driven in accordance with the enable signal EN are connected in series. The voltage regulated by the chain is input to the input terminal of the second sense amplifier 52 at the regulation level voltage REGLEVEL.

As described above, the regulation circuit applied to the charge pump circuit according to the first embodiment of the present invention adjusts the output of the first sense amplifier by using a plurality of NMOS transistors driven according to a plurality of resistors and sector information signals, The regulated voltage is compared with the regulated level voltage by the second sense amplifier to drive the PMOS transistor according to the result and output the output voltage of the pumping circuit to the output terminal.

FIG. 6 is a detailed circuit diagram of the first sense amplifier of FIG. 5. The configuration thereof is as follows.

The first PMOS transistor P61 is connected between the power supply terminal VDD and the first node Q61 by the enable signal EN inverted by the first inverter I61. A second PMOS transistor P62 driven according to the potential of the second node Q62 is connected between the first node Q61 and the second node Q61, and the second node Q62 and the ground terminal Vss are connected to each other. The first NMOS transistor N61 which is driven in accordance with the potential of the second node Q62 is connected between them. A third PMOS transistor P63 driven according to the potential of the third node Q63 is connected between the first node Q61 and the third node Q63, and the third node Q63 and the fourth node Q64 are connected to each other. The second NMOS transistor N62 which is driven according to the first voltage V1, that is, the input voltage VIN is connected. A fourth PMOS transistor P64 driven according to the potential of the third node Q63 is connected between the first node Q61 and the fifth node Q65, and the fifth node Q65 and the fourth node Q64 are connected. ) Is connected to the third NMOS transistor N63 driven according to the second voltage V2, that is, the reference voltage VREF. A fourth NMOS transistor N64 driven according to the potential of the second node Q62 is connected between the fourth node Q64 and the ground terminal Vss. A fifth PMOS transistor P65 driven according to the potential of the fifth node Q65 is connected between the first node Q61 and the output terminal OUT. In addition, the enable signal EN inverted by the fifth NMOS transistor N65 and the first inverter I61 driven according to the potential of the second node Q62 between the output terminal OUT and the ground terminal Vss. Are connected in parallel with the sixth NMOS transistor N66.

A driving method of the first sense amplifier configured as described above is as follows.

When the enable signal EN is applied in a high state, the enable signal EN is inverted to a low state by the first inverter I61 to turn off the sixth NMOS transistor N66 and turn on the first PMOS transistor P61. The power supply voltage VDD is supplied to the first node Q61 through the turned on first PMOS transistor P61. The second PMOS transistor P62 and the first NMOS transistor N61 driven according to the potential of the second node Q62 allow the potential of the second node Q62 to maintain a predetermined voltage. The fourth NMOS transistor N64 is turned on by the potential of the second node Q62 that maintains the predetermined voltage. The potentials of the third node Q63 and the fifth node Q65 are determined by the magnitudes of the first voltage V1 and the second voltage V2, and the potential of the output terminal OUT is determined. That is, when the first voltage V1 is greater than the second voltage V2, the amount of current flowing through the third PMOS transistor P63 and the second NMOS transistor N62 to the ground terminal Vss is the fourth PMOS transistor. More than the amount of current flowing through P64 and the third NMOS transistor N63 to the ground terminal Vss. Accordingly, the third node Q63 is kept low and the fifth node Q65 is kept high. The fifth PMOS transistor P65 is turned off by the potential of the fifth node Q65 that maintains the high state, and thus the power supply voltage VDD is not output to the output terminal OUT. Goes low. On the contrary, when the first voltage V1 is smaller than the second voltage V2, the third node Q63 goes high and the fifth node Q65 goes low. The fifth PMOS transistor P65 is turned on by the potential of the fifth node Q65 that maintains the low state. As a result, the power supply voltage VDD is output to the output terminal OUT so that the output terminal OUT is high. It becomes

As described above, the first sense amplifier outputs a low state signal when the first voltage V1 is greater than the second voltage V2, and outputs a high state signal when the first voltage V1 is greater than the second voltage V2.

FIG. 7 is a detailed circuit diagram of the second sense amplifier of FIG. 5. The configuration thereof is as follows.

A first PMOS in which an enable signal EN is driven by a signal ENb inverted by the first inverter I71 between an input terminal VSO to which an output voltage of the pumping circuit is input and the first node Q71. Transistor P71 is connected. The second PMOS transistor P72 driven according to the output of the first inverter I71 between the power supply terminal VDD and the second node Q72 and the third PMOS transistor driven according to the potential of the second node Q72. P73 is connected in series, and the first NMOS transistor N71 is driven between the second node Q72 and the ground terminal Vss according to the potential of the second node Q72. A fourth PMOS transistor P74 driven according to the potential of the third node Q73 is connected between the first node Q71 and the third node Q73, and the third node Q73 and the fourth node Q74 are connected to each other. The second NMOS transistor N72, which is driven according to the first voltage V1, that is, the level voltage REGLEVEL regulated by the diode chain, is connected. A fifth PMOS transistor P75 driven according to the potential of the third node Q73 is connected between the first node Q71 and the output terminal OUT, and is connected between the output terminal OUT and the fourth node Q74. A third NMOS transistor N73 driven according to the second voltage V2, that is, the adjusted reference voltage REG_REF, is connected to the third voltage V2. A fourth NMOS transistor N74 is driven between the fourth node Q74 and the ground terminal Vss according to the potential of the second node Q72. A fifth NMOS transistor N75 driven according to the enable bar signal ENb in which the enable signal EN is inverted is connected between the power supply terminal VDD and the output terminal OUT.

A driving method of the second sense amplifier configured as described above is as follows.

When the enable signal EN is applied in a high state, the enable signal EN is inverted to a low state by the first inverter I71 to turn on the first and second PMOS transistors P71 and P72. The power supply voltage VDD is supplied through the turned-on second PMOS transistor P72. The third PMOS transistor P73 and the first NMOS transistor N71 are driven according to the potential of the second node Q72. The potential of the node Q72 is maintained at a predetermined voltage. The fourth NMOS transistor N74 is turned on by the potential of the second node Q72 that maintains the predetermined voltage. When the pumping voltage VSO is supplied to the first node Q71 through the first PMOS transistor P71, the third node Q73 and the output are controlled by the magnitudes of the first voltage V1 and the second voltage V2. The potential of the terminal OUT is determined. That is, when the first voltage V1 is greater than the second voltage V2, the amount of current flowing through the fourth PMOS transistor P74 and the second NMOS transistor N72 to the ground terminal Vss is the fifth PMOS transistor. More than the amount of current flowing through the P75 and the third NMOS transistor N73 to the ground terminal Vss. Accordingly, the third node Q73 goes low and the pumping voltage VSO is output to the output terminal OUT. On the contrary, when the first voltage V1 is smaller than the second voltage V2, the third node Q73 goes high and the output terminal OUT goes low. On the other hand, the fifth NMOS transistor N75 connected between the power supply terminal VDD and the output terminal OUT is turned on when the enable signal EN is applied in a low state to initialize the output terminal OUT in a high state. Have a state.

As described above, the second sense amplifier outputs a pumping voltage when the first voltage V1 is greater than the second voltage V2, and outputs a low state signal when the first voltage V1 is greater than the second voltage V2.

8 is a reference voltage generation circuit diagram applied to a charge pump circuit according to a first embodiment of the present invention.

The first PMOS transistor P81 is driven between the power supply terminal VDD and the first node Q81 according to the enable bar signal ENb in which the enable signal EN is inverted through the first inverter I81. Connected. A second PMOS transistor P82 driven according to the potential of the second node Q82 is connected between the first node Q81 and the second node Q82, and the first node Q81 and the third node Q83 are connected to each other. ) Is connected to the third PMOS transistor P83 driven according to the potential of the second node Q82. A second NMOS transistor N82 driven according to the reference voltage VREF is connected between the second node Q82 and the fourth node Q84, and is connected between the third node Q83 and the fourth node Q84. The third NMOS transistor N83 driven in accordance with the set voltage VB is connected. Meanwhile, a first NMOS transistor N81 driven according to the enable bar signal ENb is connected between the second node Q82 and the ground terminal Vss, and the fourth node Q84 and the ground terminal Vss are connected to each other. The fourth NMOS transistor N84 which is driven in accordance with the enable signal EN is connected therebetween.

A fourth PMOS transistor P84 driven according to the enable bar signal ENb is connected between the power supply terminal VDD and the fifth node Q85. A fifth PMOS transistor P85 driven according to the potential of the third node Q83 is connected between the fifth node Q85 and the sixth node Q86, and the fifth node Q85 and the seventh node Q87 are connected to each other. ) Is connected between the sixth PMOS transistor P86 driven according to the potential of the third node Q83. Here, the potential of the sixth node Q86 is output as the reference voltage VREF, and the potential of the seventh node Q87 is output as the set voltage VB, and each output terminal has a first and a second capacitor ( C81 and C82 are connected respectively. The first bipolar transistor B81 diode-connected with the first resistor R81 is connected in series between the sixth node Q86 and the eighth node Q88, and the seventh node Q87 and the eighth node ( The second bipolar transistor B82 is diode-connected between Q88). Meanwhile, a fifth NMOS transistor N85 driven according to the enable bar signal ENb is connected between the third node Q83 and the ground terminal Vss, and the eighth node Q88 and the ground terminal Vss are connected to each other. The second resistor R82 is connected between them.

The driving method of the reference voltage generator circuit configured as described above is as follows.

When the enable signal EN is applied in a high state, the first NMOS transistor N81 is turned off by being inverted to a low state by the first inverter I81, and the fourth NMOS transistor N84, the first and the fourth PMOS transistors P81 and P84 are turned on. The power supply voltage VDD is supplied to the first and fifth nodes Q81 and Q85 through the first and fourth PMOS transistors P81 and P84. When the power supply voltage VDD is supplied to the first node Q81, the voltage applied through the second and third PMOS transistors P82 and P83 is adjusted by the magnitude of the reference voltage VREF and the set voltage VB. The potentials of the second node Q82 and the third node Q83 are determined. That is, when the reference voltage VREF is greater than the set voltage VB, the amount of current flowing through the second PMOS transistor P82 and the second NMOS transistor N82 to the ground terminal Vss is increased by the third PMOS transistor P83. And the amount of current flowing through the third NMOS transistor N83 to the ground terminal Vss. Therefore, the potential of the second node Q82 drops, and the potential of the third node Q83 rises. On the contrary, when the reference voltage VREF is smaller than the set voltage VB, the potential of the second node Q82 rises and the potential of the third node Q83 falls. When the potential of the third node Q83 rises, the amount of current applied through the fifth and sixth PMOS transistors P85 and P86 decreases and the reference voltage VREF and the set voltage VB decrease. do. On the contrary, when the potential of the third node Q83 falls, the reference voltage VREF and the set voltage VB increase. The reference voltage VREF and the set voltage VB are fed back and compared, respectively, to repeat the above operation, and finally, the finally output reference voltage VREF maintains a constant voltage. Meanwhile, the first bipolar transistor B81 and the second bipolar transistor B82 connected in series with the first resistor R81 serve as a current mirror for determining the reference voltage VREF and the set voltage VB.

9 is a block diagram illustrating a schematic configuration of a charge pump circuit according to a second exemplary embodiment of the present invention.

The pumping circuit 91 is driven by the enable signal EN to generate a high voltage according to the first and second clock signals CLK1 and CLK2. The regulation circuit 92 is driven according to the enable signal EN to regulate the output of the pumping circuit 31 according to the reference voltage VREF. The reference voltage generating circuit 93 is driven according to the enable signal EN and the sector information signals SEC0 to SEC18 to generate a predetermined reference voltage VREF. The sector information signals SEC0 to SEC18 are generated from the sector information generation circuit 94 using the address signals A <12:18> and are signals for selecting a sector for programming.

The charge pump circuit according to the second embodiment of the present invention configured as described above has a reference voltage generated by the reference voltage generator circuit 92 according to the sector information signals SEC0 to SEC18 from the sector information generator circuit 94. VREF) is adjusted. That is, when programming a sector located close to the charge pump circuit, the reference voltage is generated by lowering the set voltage to lower the bias level in consideration of the line resistance, and when programming a sector located far from the charge pump circuit. The reference voltage is generated by increasing the set voltage to increase the bias level considering the line resistance. By regulating in the regulation circuit using the adjusted reference voltage, it is possible to prevent a decrease in the bias level due to line resistance according to the distance of the sector.

FIG. 10 is a regulation circuit diagram applied to a charge pump circuit according to a second exemplary embodiment of the present invention.

The first sense amplifier 101 driven according to the enable signal EN compares the reference voltage VREF with the input voltage VIN and outputs the result. The first to third resistors R101 to R103 serving as voltage distribution means are connected between the first sense amplifier 101 and the ground terminal Vss. The first to third resistors R101 to R103 and the first to third resistors R101 to R103 are connected. The voltage divided by the resistor R101 is fed back to become the input voltage VIN of the first sense amplifier 101. The voltage divided according to the ratio of the first to third resistors R101 to R103 and the first and second resistors R101 and R102 becomes the adjustment reference voltage REG_REF.

The second sense amplifier 102 is driven according to the enable signal EN, and the level voltage REGLEVEL is adjusted by a diode chain in which the adjustment reference voltage REG_REF and the plurality of PMOS transistors P101 to P104 are diode-connected. Are compared and the output voltage PUMP_OUT of the pumping circuit is output according to the result. The PMOS transistor P100 is driven according to the output of the second sense amplifier 102 to output the output voltage PUMP_OUT of the pumping circuit to the output terminal VPPD. Between the output terminal VPPD and the ground terminal Vss, a diode chain in which a plurality of PMOS transistors P101 to P104 are diode-connected and an NMOS transistor N100 driven in accordance with the enable signal EN are connected in series. The voltage regulated by the chain is input to the input terminal of the second sense amplifier 102 at the regulation level voltage REGLEVEL.

11 is a reference voltage generation circuit diagram applied to a charge pump circuit according to a second exemplary embodiment of the present invention.

The first PMOS transistor P111 is driven between the power supply terminal VDD and the first node Q111 according to the enable bar signal ENb in which the enable signal EN is inverted through the first inverter I111. Connected. A second PMOS transistor P112 driven according to the potential of the second node Q112 is connected between the first node Q111 and the second node Q112, and the first node Q111 and the third node Q113 are connected to each other. The third PMOS transistor P113 which is driven according to the potential of the second node Q112 is connected. A second NMOS transistor N112 driven according to the first set voltage VFB is connected between the second node Q112 and the fourth node Q114, and the third node Q113 and the fourth node Q114 are connected to each other. A third NMOS transistor N113 which is driven according to the second set voltage VB is connected between them. Meanwhile, a first NMOS transistor N111 driven according to the enable bar signal ENb is connected between the second node Q112 and the ground terminal Vss, and the fourth node Q114 and the ground terminal Vss are connected to each other. The fourth NMOS transistor N114 which is driven according to the enable signal EN is connected therebetween.

A fourth PMOS transistor P114 driven according to the enable bar signal ENb is connected between the power supply terminal VDD and the fifth node Q115. The fifth PMOS transistor P115 driven according to the potential of the third node Q113 is connected between the fifth node Q115 and the sixth node Q116, and the fifth node Q115 and the seventh node Q117 are connected. ) Is connected between the sixth PMOS transistor P116 which is driven according to the potential of the third node Q113. Here, the potential of the sixth node Q116 is fed back to the first set voltage VFB, and the potential of the seventh node Q117 is fed back to the second set voltage VB. The second capacitors C111 and C112 are connected respectively. The first bipolar transistor B111 diode-connected with the first resistor R111 is connected in series between the sixth node Q116 and the eighth node Q118, and the seventh node Q117 and the eighth node ( The second bipolar transistor B112 is diode-connected between Q118. Meanwhile, a fifth NMOS transistor N115 driven according to the enable bar signal ENb is connected between the third node Q113 and the ground terminal Vss, and the eighth node Q118 and the ground terminal Vss are connected to each other. The second resistor R112 is connected between them.

On the other hand, a plurality of resistors R113 to R11n are connected in series between the sixth node Q116, that is, the first set voltage VFB output terminal and the ground terminal Vss, and the sector information signals SEC0 to In accordance with SEC18, a plurality of NMOS transistors N121 to N12m each driven are connected. One of the NMOS transistors N121 to N12m is turned on in accordance with these sector information signals SEC0 to SEC18, so that the voltage divided by the plurality of resistors is output to the reference voltage VREF.

The driving method of the reference voltage generator circuit applied to the charge pump circuit according to the second embodiment of the present invention configured as described above is as follows.

When the enable signal EN is applied in a high state, the first NMOS transistor N111 is turned off by being inverted to a low state by the first inverter I111, and the fourth NMOS transistor N114, the first and the fourth PMOS transistors P111 and P114 are turned on. The power supply voltage VDD is supplied to the first and fifth nodes Q111 and Q115 through the first and fourth PMOS transistors P111 and P114. When the power supply voltage VDD is supplied to the first node Q111, it is applied through the second and third PMOS transistors P112 and P113 by the magnitude of the first set voltage VFB and the second set voltage VB. The voltage to be adjusted is adjusted to determine the potentials of the second node Q112 and the third node Q113. That is, when the first set voltage VFB is greater than the second set voltage VB, the amount of current flowing through the second PMOS transistor P112 and the second NMOS transistor N82 to the ground terminal Vss is 3rd. More than the amount of current flowing through the PMOS transistor P113 and the third NMOS transistor N113 to the ground terminal Vss. Accordingly, the potential of the second node Q112 is lowered and the potential of the third node Q113 is increased. In contrast, when the first set voltage VFB is smaller than the second set voltage VB, the second voltage is lowered. The potential of the node Q112 goes up, and the potential of the third node Q113 goes down. When the potential of the third node Q113 rises, the amount of current applied through the fifth and sixth PMOS transistors P115 and P116 decreases and the first and second set voltages VFB VB decrease. do. On the contrary, when the potential of the third node Q113 falls, the first and second set voltages VFB and VB increase. The first and second set voltages VFB and VB are fed back and compared, respectively, to repeat the above operation. The first bipolar transistor B111 and the second bipolar transistor B112 connected in series with the first resistor R111 serve as current mirrors for determining the first and second set voltages VFB and VB.

On the other hand, the first set voltage VFB is divided by the plurality of resistors R113 to R11n by the plurality of NMOS transistors N121 to N12m respectively driven according to the sector information signals SEC0 to SEC18 to divide the reference voltage VREF. ) For example, the sixteenth sector information signal SEC15 is applied in a high state to program the sixteenth sector that is farthest from the charge pump circuit, and the first through fifteenth sector information signals SEC0 through SEC14 are low. When applied in the state, the NMOS transistor N121 is turned on and the other transistors are turned off, so that the voltage divided according to the ratio of the third to nth resistors R113 to R11n and the third to mth resistors R113 to R11m. This reference voltage VREF is obtained. In addition, the first sector information signal SEC0 is applied in a high state to program the first sector that is closest to the charge pump circuit, and the second to 19th sector information signals SEC1 to SEC18 are in a low state. When applied, since the NMOS transistor N12m is turned on and the remaining transistors are turned off, the voltage divided according to the ratio of the third to nth resistors R113 to R11n and the third resistor R113 is increased to the reference voltage VREF. do.

As described above, the reference voltage generator circuit applied to the charge pump circuit according to the second embodiment of the present invention adjusts the first set voltage by using a plurality of NMOS transistors driven according to a plurality of resistors and sector information signals. Output by voltage.

As described above, according to the present invention, program efficiency can be increased by generating and programming a pumping voltage having a different bias level according to the position of the sector using the sector information signal according to the position of the sector, thereby improving the yield of the device. You can.

Claims (10)

A pumping circuit for pumping a power supply voltage in accordance with at least one clock signal; A reference voltage generator circuit for generating a reference voltage; A sector information signal generation circuit for generating at least one sector information signal for selecting a sector for programming in accordance with the address signal; And And a regulation circuit for regulating a pumping voltage from the pumping circuit so that a bias level according to the sector to be programmed is adjusted according to the reference voltage and the sector information signal. 2. The apparatus of claim 1, wherein the regulation circuit comprises: a first comparison circuit for re-input its output and comparing the reference voltage to determine the output; Distribution means for distributing an output of the comparison circuit according to the sector information signal to generate an adjustment reference voltage; A second comparison circuit for comparing the adjustment reference voltage and the adjustment level voltage; Switching means for supplying a pumping voltage of the pumping circuit to a cell in accordance with an output of the second comparing circuit; And And a voltage drop means for dropping the pumping voltage output through the switching means to generate the regulated level voltage. 3. The apparatus of claim 2, wherein the distributing means comprises: a plurality of resistors connected in series between the first comparison circuit and a ground terminal; And And a plurality of switching means each connected between the plurality of resistors and driven according to each of at least one sector information signal. 4. The charge pump circuit according to claim 3, wherein said switching means is an NMOS transistor. 3. The charge pump circuit according to claim 2, wherein said switching means is a PMOS transistor. 3. The charge pump circuit according to claim 2, wherein the voltage drop means is diode-connected with a plurality of PMOS transistors. A pumping circuit for pumping a power supply voltage in accordance with at least one clock signal; A sector information signal generation circuit for generating at least one sector information signal for selecting a sector for programming in accordance with the address signal; A reference voltage generator circuit for generating and adjusting a reference voltage to adjust a bias level according to the sector to be programmed according to the sector information signal; And And a regulation circuit for regulating the pumping voltage from the pumping circuit according to the reference voltage. 8. The apparatus of claim 7, wherein the reference voltage generator comprises: a comparison circuit for comparing the first and second set voltages and adjusting and outputting a power supply voltage accordingly; A current mirror for outputting the first and second reference voltages by adjusting the power supply voltage according to an output of the comparison circuit; And And distribution means for distributing said first reference voltage in accordance with said sector information signal to produce an adjustment reference voltage. 9. The apparatus of claim 8, wherein the distributing means comprises: a plurality of resistors connected in series between the first comparison circuit and a ground terminal; And And a plurality of switching means each connected between the plurality of resistors and driven according to each of at least one sector information signal. 10. The charge pump circuit according to claim 9, wherein said switching means is an NMOS transistor.