KR100442230B1 - lnductor fabricating method - Google Patents

Abstract

PURPOSE: An inductor fabrication method is provided to increase a resonant frequency and reduce insertion less by forming a column-shaped insulating layer with a material having a leakage capacitance and a low leakage resistance on a substrate and forming an inductor thereon. CONSTITUTION: A first insulating layer is formed on a substrate(10) by using SiO2. The first insulating layer is removed from the remaining region except for an inductor region by a patterning/etching process. A second insulating layer(12) is formed on the entire surface of the substrate by using Si3N4. The first insulating layer is exposed by etching the second insulating layer. A metal layer for inductor is formed on the entire surface of the substrate. A shape of an inductor(14) is formed on the first insulating layer by patterning and etching the metal layer. The first insulating layer is exposed by etching back the second insulating layer.

Description

Inductor fabricating method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an inductor in a semiconductor device. In particular, the present invention relates to a method of manufacturing an inductor in a semiconductor device capable of operating at a high frequency and reducing signal transmission loss by supporting an inductance device using a supporting insulating film therein. It is about a method.

In general, as an item for evaluating characteristics of an inductor, there are a Q value (Q factor) for evaluating signal transmission characteristics, a resonant frequency indicating an operating frequency of the device, and an insertion loss indicating a loss ratio of the amount of power in the device.

When the imaginary component value of the input impedance Zin of the inductor is Im (Zin) and the real information value of input inductor Zin of the inductor is Re (Zin), Q = Im (Zin) / Re (Zin). ), The high Q value can be matched with a small loss, and can be effectively used in the oscillator design.

On the other hand, if the reflection coefficient at the input of the inductor is S11 and the transfer coefficient of the output at the input of the inductor is S21, insertion loss = | S21 | 2 / 1- | S11 | 2 is expressed.

In other words, the insertion loss is the amount of power lost in the device, which also has a small value so that the circuit loss is small. The resonant frequency is the imaginary component becomes negative due to parasitic capacitance with increasing frequency of reflection factor of inductance S11 and S22. From this frequency, the inductor is no longer an inductor but a capacitor. Higher is better characteristic.

The equivalent circuit of the inductor in the semiconductor device is shown in FIG.

In FIG. 1, L is an inductance value of the inductor to be designed, Rs is a metal resistance of the inductor, Cf is a coupling capacitance between metals, and Cp1 and Cp2 are leakage capacitances on the input and output sides, Rp1, Rp2 is also the leakage resistance of the input and output shafts, which are determined by the characteristics of the substrate, respectively. These equivalent components have a great influence on the resonance frequency and insertion loss.

In the low frequency region, the Q value increases as the frequency increases, but in the high frequency region, the Q decreases due to parasitic capacitance. The resonance frequency value increases as the leakage capacitances Cp1 and Cp2 are lower, and the insertion loss decreases as the leakage capacitances Cp1 and Cp2 are smaller and the leakage resistances Rp1 and Rp2 are smaller.

However, since inductance elements formed in conventional CMOS are usually formed by forming an insulating layer of a thin film on a substrate or a conductive layer and patterning an inductance element on the insulating layer of the thin film, the values of the leakage capacitances Cp1 and Cp2 to the substrate and As the values of the leakage resistances Rp1 and Rp2 become large, the Q-value, insertion loss, and resonant frequency characteristics of the inductor described above are deteriorated, so that they are unable to meet the application of increasingly high frequency integrated circuits.

Accordingly, the present invention has been made in view of the above-described problems of the prior art, and an object thereof is to provide a method of manufacturing an inductor that can operate at a high frequency and has a small loss of signal transmission.

1 is a circuit diagram schematically showing an equivalent circuit of an inductor manufactured on a semiconductor

2A to 2I are diagrams schematically showing respective cross sections and planes in the manufacturing process of the present invention.

Explanation of symbols for main parts of the drawings

10 substrate 11 first insulating layer

11 ': columnar etched first insulating layer

12 second insulating layer 13 metal layer for inductor

14: inductor

In order to achieve the above object, an inductor manufacturing method according to the present invention includes forming a first insulating layer on a substrate and leaving only a predetermined region where an inductor is formed through a pattern / etching process. Forming a second insulating layer on a front surface of the substrate, etching and planarizing the second insulating layer to expose the first insulating layer, and forming a metal layer for an inductor on the flattened front surface; Patterning / etching the metal layer so as to leave the metal layer on the first insulating film and forming a predetermined inductor, and etching all of the second insulating film so that the first insulating film is exposed. do.

Hereinafter, embodiments of the manufacturing method of the present invention will be described in detail with reference to the accompanying drawings.

2a to 2i schematically show each step and plane in the manufacturing process of the present invention, as shown in Figure 2a on the Si substrate 10 at about 400 ℃ by the Spiongrass (SOG) method 10 A first insulating film 11 of SiO 2 having a thickness of μm is formed.

Subsequently, as shown in the cross-sectional view of FIG. 2B and the plan view of FIG. 2C, the first insulating film 11 is subjected to a photo / etching process to leave a pillar-shaped insulating film at predetermined intervals at a portion where the inductor is to be formed. Thereafter, as shown in FIG. 2D, the second insulating film 12 of Si 3 N 4 is formed on the entire surface including the pillar-shaped insulating film 11 ′ at about 400 ° C. at about 10 μm. Flatten the top of ') to expose it completely.

Subsequently, as shown in FIG. 2F, an Al inductor metal layer 13 is formed on the flattened front surface by about 3 μm by sputtering.

Subsequently, as shown in FIG. 2G, the inductor 14 is formed by leaving only the portion where the inductor is to be formed through the photo / etch process.

Then, as shown in the cross-sectional view of FIG. 2H and the top view of FIG. 2I, the second insulating film 12 is completely removed by wet etching, so that the inductor 14 is placed on the pillar-shaped first insulating film 11 ′. Manufactured to lose. Subsequently, the inductor is connected to the electrode pad in a usual manner to complete the process.

The manufacturing method of the present invention as described above has a high Q value, high resonance frequency, and low insertion loss because a pillar-shaped insulating film is formed of a material having a very low leakage capacitance and a leakage resistance on a substrate, and an inductor is formed thereon. The advantage is the ability to operate at higher frequencies and provide an inductor with very low signal loss.

Claims (2)

Forming a first insulating layer of SiO 2 on the substrate, and removing the first insulating layer in the remaining regions except for the region where a predetermined inductor is to be formed through a pattern / etch process; Forming a second insulating layer on the entire surface of the patterned / etched substrate with Si 3 N 4 having a larger etching ratio than the first insulating layer; Etching and flattening the second insulating layer to expose the first insulating layer; Forming a metal layer for an inductor on the plated front surface; Patterning / etching the metal layer so that the metal layer remains only on the first insulating layer and at the same time forms a predetermined inductor; And etching all of the second insulating layer so that the first insulating layer is exposed. The method of claim 1, And the first insulating layer is patterned / etched so as to remain in a pillar shape formed at a predetermined interval according to a region in which the inductor is to be formed.