CN112530939B - Integrated capacitor and manufacturing method thereof, and radio frequency circuit - Google Patents
Integrated capacitor and manufacturing method thereof, and radio frequency circuit Download PDFInfo
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- CN112530939B CN112530939B CN202011298361.0A CN202011298361A CN112530939B CN 112530939 B CN112530939 B CN 112530939B CN 202011298361 A CN202011298361 A CN 202011298361A CN 112530939 B CN112530939 B CN 112530939B
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- 239000003990 capacitor Substances 0.000 title claims abstract description 106
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 263
- 239000002184 metal Substances 0.000 claims abstract description 263
- 239000000758 substrate Substances 0.000 claims description 42
- 238000002161 passivation Methods 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 21
- 238000000059 patterning Methods 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 238000000206 photolithography Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 238000001459 lithography Methods 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 229910000679 solder Inorganic materials 0.000 claims description 5
- 230000003746 surface roughness Effects 0.000 claims description 4
- 238000004381 surface treatment Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 description 26
- 229910000838 Al alloy Inorganic materials 0.000 description 12
- JRBRVDCKNXZZGH-UHFFFAOYSA-N alumane;copper Chemical compound [AlH3].[Cu] JRBRVDCKNXZZGH-UHFFFAOYSA-N 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 230000008569 process Effects 0.000 description 10
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 239000011521 glass Substances 0.000 description 6
- 229910052744 lithium Inorganic materials 0.000 description 6
- 239000007769 metal material Substances 0.000 description 5
- 239000005360 phosphosilicate glass Substances 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- IIPYXGDZVMZOAP-UHFFFAOYSA-N lithium nitrate Chemical compound [Li+].[O-][N+]([O-])=O IIPYXGDZVMZOAP-UHFFFAOYSA-N 0.000 description 4
- 239000010453 quartz Substances 0.000 description 4
- 239000010980 sapphire Substances 0.000 description 4
- 229910052594 sapphire Inorganic materials 0.000 description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910003071 TaON Inorganic materials 0.000 description 3
- 229910010413 TiO 2 Inorganic materials 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000002207 thermal evaporation Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The application relates to an integrated capacitor and a manufacturing method thereof, a radio frequency circuit; the integrated capacitor includes: a first metal layer; the first dielectric layer is arranged on the first metal layer; the second metal layer is arranged on the first dielectric layer; the second dielectric layer is arranged on the first dielectric layer; the third metal layer is arranged on the second metal layer and is in direct contact with the second metal layer, the third metal layer extends to the second medium layer, and the thickness of the third metal layer is larger than that of the second metal layer; the first metal layer comprises a first polar plate of the capacitor, the first dielectric layer comprises a capacitance dielectric layer of the capacitor, and the second metal layer comprises a second polar plate of the capacitor; the whole edge of the second metal layer is covered by the second dielectric layer, so that the contact area of the third metal layer and the second metal layer is smaller than the area of the second polar plate. The application can obtain high quality factor without sacrificing capacitance density, occupied area and reliability of the capacitor under the premise of ensuring that the capacitor obtains accurate capacitance value.
Description
Technical Field
The application relates to the field of semiconductor manufacturing, in particular to an integrated capacitor, a manufacturing method of the integrated capacitor and a radio frequency circuit.
Background
Wafer level integrated capacitors are a type of passive component commonly found in radio frequency integrated circuits. Integrated capacitors, in combination with other wafer circuit elements (e.g., inductors and transistors), can form circuit networks and microsystems with a variety of functions, including filters, impedance matching networks, power amplifiers, low noise amplifiers, balun, couplers, frequency dividers, combiners, and the like.
The capacitance of the integrated capacitor may affect the yield of the rf circuit if it deviates too much from the design value, for example, resulting in a deviation of the center frequency and bandwidth of the filter from the design value.
Disclosure of Invention
Based on this, it is necessary to provide an integrated capacitor having a capacitance value conforming to the design value.
An integrated capacitor, comprising: a first metal layer; the first dielectric layer is arranged on the first metal layer; the second metal layer is arranged on the first dielectric layer; the second dielectric layer is arranged on the first dielectric layer; the third metal layer is arranged on the second metal layer and is in direct contact with the second metal layer, the third metal layer extends to the second medium layer, and the thickness of the third metal layer is larger than that of the second metal layer; the first metal layer comprises a first polar plate of a capacitor, the first dielectric layer comprises a capacitance dielectric layer of the capacitor, and the second metal layer comprises a second polar plate of the capacitor; and all edges of the second metal layer are covered by the second dielectric layer, so that the contact area of the third metal layer and the second metal layer is smaller than the area of the second polar plate.
In one embodiment, the first polar plate forms a step at the edge, and the first metal layer and the third metal layer at the step are isolated by the first dielectric layer and the second dielectric layer.
In one embodiment, the orthographic projection of the second plate onto the first metal layer is within the range of the first metal layer.
In one embodiment, the second metal layer has a thickness of 50nm to 1000 nm.
In one embodiment, the capacitor further comprises a substrate, and the capacitor is arranged on the substrate.
In one embodiment, the semiconductor device further comprises a passivation layer arranged between the substrate and the first metal layer, wherein the substrate comprises a silicon substrate.
In one embodiment, the passivation layer has a thickness of 200nm to 2 μm.
In one embodiment, the material of the passivation layer is silicon nitride or silicon dioxide.
In one embodiment, the third metal layer covers the entire upper surface of the second electrode plate except for the position covered by the second dielectric layer.
In one embodiment, the thickness of the first dielectric layer is 10 nm to 2 μm, and the thickness of the second dielectric layer is 100 nm to 10 μm.
In one embodiment, the material of the first dielectric layer is as followsAt least one of: siNx, siO 2 、TaON、TiO 2 、AlN、Al 2 O 3 。
In one embodiment, the material of the second dielectric layer is at least one of: siO (SiO) 2 BCB, spin-on doped glass, phosphosilicate glass.
In one embodiment, the material of the second metal layer is at least one of: aluminum, copper-aluminum alloy.
In one embodiment, the copper-aluminum alloy comprises 0.1 to 3% of copper by mass.
In one embodiment, the first metal layer has a thickness of 1 μm to 5 μm.
In one embodiment, the material of the first metal layer is at least one of: aluminum, copper-aluminum alloy.
In one embodiment, the copper-aluminum alloy comprises 0.1 to 3% of copper by mass.
In one embodiment, a passivation layer is further disposed on the third metal layer.
In one embodiment, the third metal layer extends over and thus covers the steps at each step of the edge of the location where the third metal layer is in direct contact with the first metal layer; at each step of the edge of the position where the third metal layer is in direct contact with the second metal layer, the third metal layer extends over the steps so as to cover the steps.
It is also desirable to provide a radio frequency circuit that includes an integrated capacitor as described in any of the above embodiments.
It is also necessary to provide a method of manufacturing an integrated capacitor. The method consists of a specific sequence of microfabrication steps involving a series of metallic and insulating materials. The resulting structure demonstrates the coverage and superposition of these materials in the partial regions, and the electrical contact in the partial regions, to complete the stack of functions of the capacitor. The method is purposely designed and a particular sequence is chosen to achieve the stacking and superposition required for the design.
A method of manufacturing an integrated capacitor, comprising: obtaining a substrate, wherein a first metal layer is formed on the substrate, and a first dielectric layer is formed on the first metal layer; forming a second metal layer on the first dielectric layer; forming a second dielectric layer on the second metal layer and the first dielectric layer; patterning the second dielectric layer, wherein all edges of the second metal layer are covered by the patterned second dielectric layer; forming a third metal layer on the second metal layer, wherein the third metal layer is in direct contact with the second metal layer, extends to the second dielectric layer, and has a thickness larger than that of the second metal layer; the first metal layer comprises a first polar plate of a capacitor, the first dielectric layer comprises a capacitance dielectric layer of the capacitor, the second metal layer comprises a second polar plate of the capacitor, and all edges of the second metal layer are covered by the second dielectric layer, so that the contact area of the third metal layer and the second metal layer is smaller than the area of the second polar plate.
In one embodiment, the step of forming a second metal layer on the first dielectric layer includes: depositing metal on the first dielectric layer; patterning the deposited metal; wherein the step of patterning the deposited metal comprises using photoresist lithography and dry etching the deposited metal.
In one embodiment, the base includes a silicon substrate, and a passivation layer is further formed between the silicon substrate and the first metal layer in the step of obtaining the base.
In one embodiment, the step of forming a second dielectric layer on the second metal layer and on the first dielectric layer includes: depositing a second dielectric layer on the second metal layer and the first dielectric layer; the step of patterning the second dielectric layer includes photolithography and etching the second dielectric layer and the first dielectric layer.
In one embodiment, after the step of forming a third metal layer on the second metal layer, the method further includes a step of forming a passivation layer on the third metal layer.
In one embodiment, after the step of forming the third metal layer on the second metal layer, the method further includes a step of flip-chip bonding the chip on which the integrated capacitor is formed.
According to the integrated capacitor and the manufacturing method thereof, the second metal layer serving as the second polar plate of the capacitor is made of thin metal, so that the higher photoetching resolution can be realized in the photoetching step corresponding to the second metal layer, and the capacitance value of the capacitor can be easily and accurately defined. The problem of low quality factor (Q value) of the thin metal electrode plate is solved by providing a thick metal layer (third metal layer) directly contacting the second metal layer. On the premise of ensuring that the capacitor obtains an accurate capacitance value, a higher quality factor can be provided for the capacitor without sacrificing the capacitance density, the occupied area and the reliability of the capacitor.
Drawings
For a better description and illustration of embodiments and/or examples of those applications disclosed herein, reference may be made to one or more of the accompanying drawings. Additional details or examples used to describe the drawings should not be construed as limiting the scope of the disclosed application, the presently described embodiments and/or examples, and any of the presently understood modes of carrying out the application.
FIG. 1 is a schematic cross-sectional view of an integrated capacitor in one embodiment;
FIG. 2 is a flow chart of a method of fabricating an integrated capacitor in one embodiment;
FIGS. 3 a-3 f are schematic diagrams illustrating cross-sections of an integrated capacitor during fabrication according to one embodiment;
FIG. 4 is a schematic cross-sectional view of an integrated capacitor in another embodiment;
fig. 5 is a schematic diagram of a chip incorporating 4 of the above-described integrated capacitors.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element is referred to as being "fixed to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and the like are used herein for illustrative purposes only. When an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
The terms "comprises," "comprising," and/or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.
Integrated capacitors on a chip generally have a variety of performance advantages. We have the following expectations for an integrated capacitor: first, they should provide sufficient capacitance density (i.e., capacitance per unit area) to cover the large range of capacitance required for the above functions in small dimensions. Second, they should provide a high Q factor and low loss so that a Radio Frequency Integrated Circuit (RFIC), whether passive or active, can achieve high performance without wasting power to compensate for losses on the capacitor. Third, they should be able to withstand sufficiently large voltage swings and therefore have high power handling capabilities. Fourth, they should be completed in a manufacturing flow compatible with monolithic or heterogeneous integration of other RFIC circuit elements. A final critical aspect in determining the yield of such rf components (e.g., integrated filters) is the accuracy with which the sensing values of such integrated components can be set. Almost all of the above requirements relate to the method of manufacturing the integrated capacitor and the materials involved in the manufacturing process. The most advanced chip-level or wafer-level capacitors employ a fabrication process (flow) that aims to integrate and deploy passive components, where the capacitor and inductor are co-fabricated on the same substrate. While these process flows are very effective in providing high performance integrated passive components, a compromise needs to be made in defining the layer thickness and associated accuracy of the assembly. For example, extremely thick metal layers are used to minimize inductor losses, but the use of extremely thick metal layers constrains the photolithographic process resolution of definable capacitor layers, thereby significantly reducing the accuracy of defining capacitor values.
FIG. 1 is a schematic cross-sectional view of an integrated capacitor in one embodiment. In the embodiment shown in fig. 1, the integrated capacitor disposed on a wafer (wafer) includes a first metal layer 32, a first dielectric layer 24, a second metal layer 34, a second dielectric layer 26, and a third metal layer 36.
The first dielectric layer 24 is disposed on the first metal layer 32. The second metal layer 34 is disposed on the first dielectric layer 24. The second dielectric layer 26 is disposed on the first dielectric layer 24. The third metal layer 36 is disposed on the second metal layer 34, and is in direct contact with the second metal layer 34, and the third metal layer 36 extends onto the second dielectric layer 24. The thickness of the third metal layer 36 is greater than the thickness of the second metal layer 34.
Wherein the first metal layer 32 comprises a lower plate 32a of the capacitor, the first dielectric layer 24 comprises a capacitive dielectric layer of the capacitor, and the second metal layer 34 comprises an upper plate of the capacitor. The entire edge of the second metal layer 34 is covered by the second dielectric layer 26 so that the contact area of the third metal layer 36 with the second metal layer 34 is smaller than the area of the upper plate. In the embodiment shown in fig. 1, the third metal layer 36 also serves as a metal interconnect.
In the integrated capacitor, the second metal layer 34 serving as the upper electrode plate of the capacitor is made of thin metal, so that the photolithography resolution can be higher in the photolithography step corresponding to the second metal layer, and the capacitance value of the capacitor can be easily and accurately defined. The problem of low quality factor (Q value) of the thin metal electrode plate is solved by providing a thick metal layer (third metal layer 36) directly contacting the second metal layer 34. On the premise of ensuring that the capacitor obtains an accurate capacitance value, a higher quality factor can be provided for the capacitor without sacrificing the capacitance density, the occupied area and the reliability of the capacitor.
In one embodiment, the second metal layer 34 has a thin layer thickness of 50 nanometers to 1000 nanometers. Further, the thickness of the second metal layer 34 may be 100 nm to 1000 nm. In order to make the capacitance value of the manufactured capacitor conform to the design value, the area (shape size) of the second metal layer 34 needs to be accurately defined. In one embodiment, the second metal layer 34 is formed by patterning the metal material by photolithography and dry etching after depositing the corresponding metal material; and the photoresist exposure should be performed using high fidelity lithography methods such as stepper, or high precision mask aligner, or direct lithography tools. In one embodiment, the material of the second metal layer 34 may be aluminum or copper-aluminum alloy; for copper-aluminum alloys, the mass percent of copper is 0.1% to 3%.
In the embodiment shown in fig. 1, the first plate 32a forms a step at the edge, where the first metal layer 32 and the third metal layer 36 (e.g., the locations shown by the oval dashed boxes in fig. 1) are separated by the first dielectric layer 24 and the second dielectric layer 26. If the insulating isolation structure between the two layers of metal at the step is thin, electrical breakdown easily occurs. In the embodiment shown in fig. 1, two insulating dielectric layers (i.e., the first dielectric layer 24 and the second dielectric layer 26) are disposed between the first metal layer 32 and the third metal layer 36, so that the thickness of the insulating isolation structure is relatively thick, and electrical breakdown is unlikely to occur. In one embodiment, the thickness of the first dielectric layer 24 is 10 nanometers to 2 micrometers and the thickness of the second dielectric layer 26 is 100 nanometers to 10 micrometers.
Also, in the embodiment shown in fig. 1, the front projection of the upper plate onto the first metal layer 32 is within the range of the first metal layer 32, i.e., the front projection of the upper plate onto the first metal layer 32 does not exceed the range of the first metal layer 32. This design can avoid the step of the first dielectric layer 24 being disposed between the step of the first metal layer 32 and the edge of the upper plate, which is also helpful in improving electrical breakdown at the step.
In the embodiment shown in FIG. 1, the wafer further includes a substrate 10, and the capacitor is disposed on the substrate10. The base 10 may comprise a substrate having a size (wafer diameter) ranging from 4 inches to 12 inches. The material of the substrate may be any of the following: silicon, glass, quartz, sapphire, lithium nitrate, lithium titanate. In the embodiment shown in fig. 1, the base 10 comprises a silicon substrate, and a passivation layer 22 is further provided between the base 10 and the first metal layer 32. The passivation layer 22 covers the top surface of the substrate 10. In one embodiment, the passivation layer 22 has a thickness ranging from 200nm to 2 μm. In one embodiment, the material of passivation layer 22 may be silicon nitride (SiNx) or silicon dioxide (SiO 2 ). In embodiments where the material of the substrate is an insulating material, the passivation layer 22 may not be provided. In embodiments where the material of the substrate is quartz or sapphire or lithium nickelate or lithium titanate, the substrate may be of any cut and lattice orientation.
In one embodiment, the third metal layer 36 covers the entire upper surface of the upper plate except where it is covered by the second dielectric layer 24. Further, the upper surface of the upper plate is not in direct contact with other structures except for the third metal layer 36 and the second dielectric layer 24.
In one embodiment, the thickness of the third metal layer 36 is 1 μm to 15 μm.
In one embodiment, the thickness of the first metal layer 32 is 1 μm to 5 μm. The material of the first metal layer 32 may be aluminum or copper-aluminum alloy; for copper-aluminum alloys, the mass percent of copper is 0.1% to 3%.
In one embodiment, the first dielectric layer 24 is an insulating layer, and the material may be any of the following: siNx, siO 2 、TaON、TiO 2 AlN or Al 2 O 3 。
In one embodiment, the second dielectric layer 26 is an insulating layer, and the material may be any of the following: siO (SiO) 2 BCB (Benzocyclobutene), spin-on-glass (SOG) or phosphosilicate glass (PSG).
In the embodiment shown in fig. 1, third metal layer 36 extends over the steps at each step at the edge of the location where third metal layer 36 is in direct contact with first metal layer 32 so as to cover the steps (e.g., the location indicated by arrow X). At each step of the edge of the location where the third metal layer 36 is in direct contact with the second metal layer 34, the third metal layer 36 extends over the steps so as to cover the steps (e.g., the location indicated by arrow Y). This arrangement protects the first metal layer 32/second metal layer 34 below the third metal layer 36 from moisture and the like entering the joint between the third metal layer 36 and the first metal layer 32/second metal layer 34.
Referring to fig. 4, in one embodiment, a passivation layer 28 is also provided on the third metal layer 36. As shown in fig. 4, passivation layer 28 may expose portions of third metal layer 36 in direct contact with first metal layer 32 as vias. The passivation layer 28 is optional, i.e. in other embodiments the passivation layer 28 may not be provided.
The application correspondingly provides a radio frequency circuit which comprises the integrated capacitor in any embodiment.
The application also provides a manufacturing method of the integrated capacitor, as shown in fig. 2, comprising the following steps:
s210, acquiring a substrate.
Typically starting with a wafer, as a substrate for material stacking and forming capacitors. The base may comprise a substrate, the substrate size (wafer diameter) varying from 4 inches to 12 inches. The material of the substrate may be any of the following: silicon, glass, quartz, sapphire, lithium nitrate, lithium titanate. In one embodiment, the base comprises a silicon substrate and the base is provided with a passivation layer thereon, i.e. the passivation layer covers the top surface of the base. In one embodiment, the passivation layer has a thickness ranging from 200nm to 2 μm. In one embodiment, the material of the passivation layer may be silicon nitride (SiNx) or silicon dioxide (SiO 2 ). In embodiments where the material of the substrate is an insulating material, the passivation layer may not be provided. In embodiments where the substrate material is quartz, sapphire, lithium nickelate, and lithium titanate, the substrate may be in any cut and lattice orientation.
A first metal layer is formed on the substrate as a lower plate of the capacitor, and a first dielectric layer is formed on the first metal layer as a capacitance dielectric layer of the capacitor. The first metal layer and the first metal layer can be formed by conventional methodsA dielectric layer. In an embodiment of the present application, the first metal layer and the first dielectric layer are formed as follows: a passivation layer 22 is deposited on the substrate 10 as shown in fig. 3 a. Metal is then deposited on the wafer surface (over passivation layer 22) by Physical Vapor Deposition (PVD), such as sputtering, electron beam evaporation (e-beam), thermal evaporation, and the like. The material of the metal can be aluminum or copper-aluminum alloy; for copper-aluminum alloys, the mass percent of copper is 0.1% to 3%. The first metal layer 32 is patterned by a photolithographic and etching process after deposition to obtain the desired bottom plate of the capacitor, as shown in fig. 3 b. Etching the first metal layer 32 may employ a wet etching process (based on corrosive chemicals) or a dry etching process (based on reactive ions). After etching, a first dielectric layer 24 is deposited on the wafer surface (over the first metal layer 32), as shown in fig. 3 c. In one embodiment, the first dielectric layer 24 is an insulating layer, and the material may be any of the following: siNx, siO 2 、TaON、TiO 2 AlN or Al 2 O 3 . In one embodiment, the thickness of the first dielectric layer 24 is 10 nanometers to 2 micrometers.
In step S220, a second metal layer is formed on the first dielectric layer.
The corresponding schematic cross-sectional view after the completion of step S220 is shown in fig. 3d. The second metal layer 34, which is the upper plate of the capacitor, is a thin metal layer. In one embodiment, the thickness of the second metal layer 34 is 50 nanometers to 1000 nanometers. Further, the thickness of the second metal layer 34 may be 100 nm to 1000 nm. In order to make the capacitance value of the manufactured capacitor conform to the design value, the area (shape size) of the second metal layer 34 needs to be accurately defined. In one embodiment, step S220 includes patterning the metal material by photolithography and dry etching after depositing the corresponding metal material, resulting in second metal layer 34. Further, the photoresist is exposed using high fidelity lithography methods, such as stepper, or high precision mask aligner, or direct lithography tools. In one embodiment, the material of the second metal layer 34 may be aluminum or copper-aluminum alloy; for copper-aluminum alloys, the mass percent of copper is 0.1% to 3%.
In step S230, a second dielectric layer is formed on the second metal layer and on the first dielectric layer.
The corresponding schematic cross-sectional view after the completion of step S230 is shown in fig. 3e. In one embodiment, the insulating material is deposited on the wafer (on the second metal layer 34 and on the first dielectric layer 24) by a deposition process, which may be any of the following: siO (SiO) 2 BCB, spin-on-glass (spin-on-glass) or phosphosilicate glass (PSG). In one embodiment, the thickness of the second dielectric layer 26 is 100 nanometers to 10 micrometers.
S240, patterning the second dielectric layer.
The corresponding schematic cross-section after the completion of step S240 is shown in fig. 3f. The entire edge of the second metal layer 34 is covered by the patterned second dielectric layer 26. In one embodiment, step S240 includes photolithography and etching of second dielectric layer 26 and first dielectric layer 24, i.e., patterning of second dielectric layer 26 and first dielectric layer 24 using the same reticle, etching using the same photoresist as the etch stop layer. In one embodiment, the second dielectric layer 26 and the first dielectric layer 24 are etched using an etchant having a high etch selectivity to the material of the second dielectric layer 26 (first dielectric layer 24) and the second metal layer 34 to ensure that the second metal layer 34 is not etched damaged after the second dielectric layer 26 over the second metal layer 34 is etched through. After patterning is completed, it is necessary to ensure that the entire edge of the second metal layer 34 is covered by the second dielectric layer 26, so that the contact area between the third metal layer 36 and the second metal layer 34 is smaller than the area of the upper plate of the capacitor.
S250, forming a third metal layer on the second metal layer.
The corresponding schematic cross-sectional view after the completion of step S240 is shown in fig. 1. A third metal layer 36 is obtained after deposition of metal on top and patterning. The third metal layer 36 is a thick metal layer. In one embodiment, the third metal layer 36 also serves as a metal interconnect. In one embodiment, the third metal layer 36 covers the entire upper surface of the upper plate except where it is covered by the second dielectric layer 24. Further, the upper surface of the upper plate is not in direct contact with other structures except for the third metal layer 36 and the second dielectric layer 24.
In the above method for manufacturing an integrated capacitor, the second metal layer 34 serving as the upper electrode plate of the capacitor is made of thin metal, so that the photolithography resolution can be higher in the photolithography step corresponding to the second metal layer, and the capacitance value of the capacitor can be easily and accurately defined. The problem of low quality factor (Q value) of the thin metal electrode plate is solved by providing a thick metal layer (third metal layer 36) directly contacting the second metal layer 34. On the premise of ensuring that the capacitor obtains an accurate capacitance value, a higher quality factor can be provided for the capacitor without sacrificing the capacitance density, the occupied area and the reliability of the capacitor.
In one embodiment, after forming the first metal layer 32 and before forming the first dielectric layer 24, the method further includes a step of performing a surface treatment on the upper surface of the first metal layer 32, thereby increasing the surface roughness of the upper surface of the first metal layer 32. After the surface treatment, a first dielectric layer 24 is formed on the first metal layer 32. In one embodiment, a Chemical Mechanical Polishing (CMP) process may be employed to increase the surface roughness; in another embodiment, a diamond cutting process is used to increase the surface roughness.
The above description of the process flow focuses on describing the formation of a capacitor, but these steps may be used simultaneously to form vias between the first metal layer 32 and the second metal layer 34, and to form vias between the second metal layer 34 and the third metal layer 36.
In one embodiment, step S250 is followed by a step of forming passivation layer 28 on third metal layer 36, see fig. 4. This step is optional, i.e., passivation layer 28 may not be formed in other embodiments.
In one embodiment, the method of manufacturing the integrated capacitor is compatible with a subsequent flip-chip bonding (flip-chip bonding) process in which solder balls are placed on another substrate or laminate, that is, the step S250 may be followed by a step of placing solder balls on another substrate or laminate and flip-chip bonding the chip on which the integrated capacitor is formed.
Fig. 5 is a schematic diagram of a chip incorporating 4 of the above-described integrated capacitors. Precision of each capacitor 410 is excellentAt 2%, the accuracy value is based on the expected variation of the 6 inch wafer lithography process and the minimum capacitor size of 0.5 pF. In this embodiment, the material of the first dielectric layer as the capacitance dielectric layer is SiN, has a thickness of 150nm, and has a thickness of 0.4 fF/. Mu.m 2 Can ensure a capacitance density of 500X 500 μm 2 Can accommodate 4 of the above-described integrated capacitors. And the chip size contains enough space to accommodate 4-5 solder balls 420 to flip-chip bond the chip to a separate substrate. It is noted that the number of discrete capacitors may be changed to any value depending on the requirements of the end application. Likewise, the size and number of solder balls may be modified to suit the end application. In one embodiment, the integrated capacitor is modeled as formed on a high resistivity silicon wafer, with a quality factor q=300 in 5GHz simulation.
In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (15)
1. An integrated capacitor, comprising:
a first metal layer;
the first dielectric layer is arranged on the first metal layer;
the second metal layer is arranged on the first dielectric layer;
the second dielectric layer is arranged on the first dielectric layer;
the third metal layer is arranged on the second metal layer and is in direct contact with the second metal layer, the third metal layer extends to the second medium layer, and the thickness of the third metal layer is larger than that of the second metal layer;
the first metal layer comprises a first polar plate of a capacitor, the first dielectric layer comprises a capacitance dielectric layer of the capacitor, and the second metal layer comprises a second polar plate of the capacitor; all edges of the second metal layer are covered by the second dielectric layer, so that the contact area of the third metal layer and the second metal layer is smaller than the area of the second polar plate; the third metal layer also serves as a metal interconnection; the first polar plate forms a step at the edge, the third metal layer covers the step, and the first metal layer at the step and the third metal layer at the step are isolated by the first dielectric layer and the second dielectric layer; at each step of the edge of the position where the third metal layer is in direct contact with the first metal layer, the third metal layer extends over the steps so as to cover the steps.
2. The integrated capacitor of claim 1, wherein an orthographic projection of the second plate onto the first metal layer is within a range of the first metal layer.
3. The integrated capacitor of claim 1, wherein the second metal layer has a thickness of 50nm to 1000 nm.
4. The integrated capacitor of claim 1, further comprising a substrate, the capacitor being disposed on the substrate.
5. The integrated capacitor of claim 4, further comprising a passivation layer disposed between the base and the first metal layer, the base comprising a silicon substrate.
6. The integrated capacitor of claim 1, wherein the third metal layer covers all of the upper surface of the second plate except where covered by the second dielectric layer.
7. The integrated capacitor of claim 1, wherein the first dielectric layer has a thickness of 10 nanometers to 2 microns and the second dielectric layer has a thickness of 100 nanometers to 10 microns.
8. The integrated capacitor of claim 1, wherein the third metal layer extends over and thereby covers the steps at each step of the edge of the location where the third metal layer is in direct contact with the second metal layer.
9. A radio frequency circuit comprising the integrated capacitor of any one of claims 1-8.
10. A method of manufacturing an integrated capacitor, comprising:
obtaining a substrate, wherein a first metal layer is formed on the substrate, and a first dielectric layer is formed on the first metal layer;
forming a second metal layer on the first dielectric layer;
forming a second dielectric layer on the second metal layer and the first dielectric layer;
patterning the second dielectric layer, wherein all edges of the second metal layer are covered by the patterned second dielectric layer;
forming a third metal layer on the second metal layer, wherein the third metal layer is in direct contact with the second metal layer, extends to the second dielectric layer, and has a thickness larger than that of the second metal layer;
the first metal layer comprises a first polar plate of a capacitor, the first dielectric layer comprises a capacitance dielectric layer of the capacitor, the second metal layer comprises a second polar plate of the capacitor, and all edges of the second metal layer are covered by the second dielectric layer, so that the contact area of the third metal layer and the second metal layer is smaller than the area of the second polar plate; the third metal layer also serves as a metal interconnection; the first polar plate forms a step at the edge, the third metal layer covers the step, and the first metal layer at the step and the third metal layer at the step are isolated by the first dielectric layer and the second dielectric layer; at each step of the edge of the position where the third metal layer is in direct contact with the first metal layer, the third metal layer extends over the steps so as to cover the steps.
11. The method of claim 10, wherein the step of forming a second metal layer on the first dielectric layer comprises:
depositing metal on the first dielectric layer;
patterning the deposited metal;
wherein the step of patterning the deposited metal comprises using photoresist lithography and dry etching the deposited metal.
12. The method of claim 10, wherein the base comprises a silicon substrate, and wherein a passivation layer is further formed between the silicon substrate and the first metal layer in the step of obtaining the base.
13. The method of manufacturing an integrated capacitor of claim 10, wherein the step of forming a second dielectric layer on the second metal layer and on the first dielectric layer comprises: depositing a second dielectric layer on the second metal layer and the first dielectric layer;
the step of patterning the second dielectric layer includes photolithography and etching the second dielectric layer and the first dielectric layer.
14. The method of manufacturing an integrated capacitor of claim 10, wherein the step of obtaining a substrate comprises:
forming a first metal layer on the substrate;
surface treatment is carried out on the upper surface of the first metal layer, so that the surface roughness of the upper surface of the first metal layer is improved;
and forming a first dielectric layer on the surface-treated first metal layer.
15. The method of manufacturing an integrated capacitor according to claim 10, further comprising the step of placing solder balls on another substrate or laminate and flip-chip bonding a chip on which the integrated capacitor is formed, after the step of forming a third metal layer on the second metal layer.
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| CN102157514A (en) * | 2010-01-07 | 2011-08-17 | 三星电机株式会社 | RF semiconductor device and fabrication method thereof |
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| CN1253661A (en) * | 1997-04-29 | 2000-05-17 | 艾利森电话股份有限公司 | Capacitors in integrated circuits |
| EP1170797A2 (en) * | 2000-07-04 | 2002-01-09 | Alps Electric Co., Ltd. | Thin-film capacitor element and electronic circuit board on which thin-film capacitor element is formed |
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