KR100226835B1 - Method for manufacturing inductor of semiconductor device - Google Patents
Method for manufacturing inductor of semiconductor device Download PDFInfo
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- KR100226835B1 KR100226835B1 KR1019960079257A KR19960079257A KR100226835B1 KR 100226835 B1 KR100226835 B1 KR 100226835B1 KR 1019960079257 A KR1019960079257 A KR 1019960079257A KR 19960079257 A KR19960079257 A KR 19960079257A KR 100226835 B1 KR100226835 B1 KR 100226835B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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Abstract
본 발명은 높은 주파수에서 동작할수 있고 신호전달 손실이 경감되도록 기판에 트렌치 공법을 이용하여 인덕터 제조시 금속층이나 기판자체로의 누설전류 성분과 누설 커패시터 성분을 대폭적으로 경감할 수 있는 인덕터의 제조방법을 제공하기 위한 것이다.The present invention provides a method of manufacturing an inductor that can operate at a high frequency and reduce the leakage current component and leakage capacitor component to the metal layer or the substrate itself by using the trench method on the substrate to reduce the signal transmission loss. It is to provide.
이와 같은 본 발명의 목적을 달성하기 위한 반도체 소자내의 인덕터의 제조 방법은, 기판상에 산화막 및 제1절연층을 순차적으로 형성하는 단계와, 상기 제1절연층상에 제1금속층을 증착한후 소정 형상으로 패터닝하여 배선층을 형성하는 단계와, 상기 배선층을 포함한 기판 전면에 제2절연층을 형성하는 단계와, 상기 제2절연층상에 마스크로 사용할 제2금속층을 증착하여 패터닝한후 패터닝된 제2금속층을 마스크로 하여 기판내부 깊이까지 식각하여 제거한후 상기 트렌치를 절연막으로 입혀 메워서 평탄화하는 단계와, 상기 배선층으로의 접속공을 형성한후 상기 접속공 및 트렌치를 포함하는 전면에 제3금속층을 증착한후 상기 트렌치내의 절연막위의 제3금속층 부분 및 상기 접속공을 통하여 상기 배선층과 전기적으로 접속되는 제3금속층 부분이 남겨지도록 패터닝하여 인덕터를 형성하는 단계를 포함함을 특징으로 하고 있다.In order to achieve the object of the present invention, a method of manufacturing an inductor in a semiconductor device includes sequentially forming an oxide film and a first insulating layer on a substrate, and depositing a first metal layer on the first insulating layer. Patterning to form a wiring layer, forming a second insulating layer on the entire surface of the substrate including the wiring layer, depositing and patterning a second metal layer to be used as a mask on the second insulating layer, and then patterning the second Etching and removing the metal layer as a mask to the inner depth of the substrate, and then flattening the trench by covering the trench with an insulating layer, forming a connection hole to the wiring layer, and then forming a third metal layer on the entire surface including the connection hole and the trench. After deposition, the third metal layer portion on the insulating film in the trench and the third metal layer portion electrically connected to the wiring layer through the connection hole are formed. And it is characterized in that it comprises the step of forming an inductor by patterning so as offal.
Description
본 발명은 반도체 소자내의 인덕터 제조방법에 관한 것으로, 특히 반도체 소자내에 트렌치를 형성하고 그위에 인덕트의 배선을 배치함으로서 높은 주파수에서 동작할수 있고 신호전달의 손실을 경감하도록 한 반도체 소자내의 인덕터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an inductor in a semiconductor device. In particular, a method of manufacturing an inductor in a semiconductor device can operate at high frequency and reduce signal transmission loss by forming a trench in the semiconductor device and arranging inductance thereon. It is about.
일반적으로 인덕터의 특성을 평가하는 항목으로서 신호전달 특성을 평가하는 Q값(Q factor)과, 소자의 동작주파수를 나타내는 공진주파수와, 소자 내에서의 전력량의 손실비율을 나타내는 삽입손실이 있다.In general, the items for evaluating the characteristics of the inductor include a Q value (Q factor) for evaluating signal transmission characteristics, a resonant frequency indicating an operating frequency of the device, and an insertion loss indicating a loss ratio of the amount of power in the device.
상기 Q값은 인덕터의 입력 임피던스(ZIin)의 허수성분값을 Im(Zin)이라 하고, 인덕터의 입력임피더스(Zin)의 실수성분값을 Re(Zin)이라 할때, Q=Im(Zin)/Re(Zin)으로 표시되며, 상기 Q값이 높아야만 적은 손실로 매칭이 가능할 뿐만 아니라 오실 레이터 설계시 효율적으로 사용할수 있다.The Q value is an imaginary component value of the input impedance ZIin of the inductor, and Im (Zin), and the real component value of the input impedance Zin of the inductor is Re (Zin), where Q = Im (Zin). / Re (Zin), and the higher the Q value, the less loss can be matched and the oscillator can be efficiently used.
한편, 인덕터의 입력에서의 반사계수를 S11이라 하고, 인덕트의 입력에 대한 출력의 전달계수를 S21이라 하면, 삽입손실=｜S21｜2/1-｜S11｜2로 표시된다.On the other hand, because the reflection coefficient at the input S of the inductor 11 and, when the transfer coefficient of the output inductor for the input of the bit as S 21, an insertion loss = | is represented by 2 | S 21 | 2 / 1- | S 11 .
즉, 삽입손실은 소자내에서 잃어버리는 전력의 량으로서, 이것 역시 작은 값을 가져야만 회로손실이 적다.In other words, the insertion loss is the amount of power lost in the device, which also has a small value so that the circuit loss is small.
공진주파수는 인덕턴스의 반사계수 항목인 S11, S22가 주파수 증가에 따른 기생 커패시턴스로 인하여 허수성분이 음수로 되고 이것에 의해 이 주파수 부터는 인덕터가 더 이상 인덕터가 아니고 커패시터로 되며 이 값 공진주파수는 높을수록 좋은 특성이다.The resonant frequency becomes negative because the parasitic capacitances of S 11 and S 22, which are the coefficients of reflection of inductance, become negative because of the parasitic capacitance, and from this frequency, the inductor is no longer an inductor but a capacitor. Higher is better characteristic.
또한 반도체 소자내에서의 인덕터의 등가회로는 도1과 같다. 도1에서 L은 설계하고자 하는 인덕터의 인덕턴스값이고, RS는 인더터의 금속저항, Cf는 금속간의 카플링 커패시턴스, Cp1, CP2는 각각 기판의 특성에 따라 정해지는 입력 및 출력측의 누설 커패시턴스, Rp1, Rp2역시 각각 기판의 특성에 따라 정해지는 입력 및 출력측의 누설저항으로서, 이들 등가성분들은 공진주파수, 삽입손실값에 큰 영향을 미친다.The equivalent circuit of the inductor in the semiconductor device is shown in FIG. In FIG. 1, L is an inductance value of an inductor to be designed, R S is a metal resistance of the inductor, C f is a coupling coupling between metals, and Cp 1 and CP 2 are leakages on the input and output sides respectively determined according to the characteristics of the substrate. Capacitances, Rp 1 and Rp 2 are also leakage resistances on the input and output sides, which are determined according to the characteristics of the substrate, respectively. These equivalent components have a great influence on the resonance frequency and insertion loss.
그리고 Q값은 저주파 영역에서는 주파수가 올라감에 따라 Q가 증가하지만, 고주파 영역에서는 기생 커패시터에 의해 Q가 감소한다. 공진주파수값은 누설 커패시턴스 Cp1, Cp2의 값이 낮을수록 커지며, 손입손실은 누설 커패시턴스 Cp1, Cp2의 값 및 누설저항 Rp1, Rp2의 값이 작을수록 적게 된다.In the low frequency region, the Q value increases as the frequency increases, but in the high frequency region, Q decreases due to the parasitic capacitor. The resonant frequency value increases as the values of leakage capacitances Cp 1 and Cp 2 decrease, and the loss of input decreases as the values of leakage capacitances Cp 1 and Cp 2 and the values of leakage resistances Rp 1 and Rp 2 decrease.
그러나 종래의 CMOS내에 형성되어 있는 인덕턴스 소자는 통상 기판이나 또는 도전층위에 박막의 절연층을 형성하고 이 박막의 절연층위에 인덕턴스 소자를 패터닝하여 형성하기 때문에 기판으로의 누설 커패시턴스 Cp1, Cp2의 값 및 누설저항 Rp1, Rp2의 값이 크게 되어서 상술한 바 있는 인덕터의 Q값, 삽입손실 및 공진주파수 특성이 나쁘기 때문에 점차 증가되는 높은 주파수의 집적회로의 응용에 부응하지 못하게 되었다.However, inductance elements formed in conventional CMOS are usually formed by forming an insulating layer of a thin film on a substrate or a conductive layer and patterning an inductance element on the insulating layer of the thin film, so that leakage capacitances Cp 1 and Cp 2 to the substrate are formed. As the values of the leakage resistances Rp 1 and Rp 2 become large, the Q-value, insertion loss, and resonant frequency characteristics of the inductor described above are deteriorated, so that the application of the increasingly high frequency integrated circuit cannot be met.
따라서, 본 발명은 전술한 종래 기술의 문제점을 감안하여 발명한 것으로, 높은 주파수에서 동작할수 있고 신호전달 손실이 경감되도록 기판에 트렌치 공법을 이용하여 인덕터 제조시 금속층이나 기판자체로의 누설저항 성분과 누설 커패시터 성분을 대폭적으로 경감할 수 있는 인덕터의 제조방법을 제공하기 위한 것이다.Accordingly, the present invention has been made in view of the above-described problems of the prior art, and it is possible to operate at a high frequency and to reduce signal transmission loss by using a trench method on a substrate. An object of the present invention is to provide a method of manufacturing an inductor capable of significantly reducing a leakage capacitor component.
제1도는 본 발명의 제1실시예의 인덕터의 레이아웃을 나타낸 도면1 is a diagram showing the layout of the inductor of the first embodiment of the present invention.
제2a도 내지 제2f도는 본 발명의 제1실시예의 인덕터의 제조공정을 제1도의 A-A' 단면에 도시한 단면도.2A to 2F are sectional views showing the manufacturing process of the inductor of the first embodiment of the present invention in the cross-sectional view taken along line A-A 'of FIG.
제3a도 내지 제3f도는 본 발명의 제2실시예의 인덕터의 제조공정을 일단면에 따라 도시한 단면도이다.3A to 3F are sectional views showing, according to one side, the manufacturing process of the inductor of the second embodiment of the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
10 : 기판 11 : 산화막10 substrate 11 oxide film
12 : 절연체층 13 : 배선층12: insulator layer 13: wiring layer
14 : 타이타늄층 15 : 인덕터가 형성될 타이타늄의 식각부분14: titanium layer 15: etching portion of titanium to form an inductor
16 : 트랜치 17 : 절연막16: trench 17: insulating film
18 : 접속층 19 : 인덕트 형성용 금속층18: connection layer 19: metal layer for induct formation
20 : 절연층20: insulation layer
이와 같은 본 발명의 목적을 달성하기 위한 반도체 소자내의 인덕터의 제조방법은, 기판상에 산화막 및 제1절연층을 순차적으로 형성하는 단계와, 상기 제1절연층상에 제1금속층을 증착한후 소정 형상으로 패터닝하여 배선층을 형성하는 단계와, 상기 배선층을 포함한 기판 전면에 제2절연층을 형성하는 단계와, 상기 제2절연층상에 마스크로 사용할 제2금속층을 증착하여 패터닝한후 패턴닝된 제2금속층을 마스크로 하여 기판내부 깊이까지 식각하여 제거한후 상기 트렌치를 절연막으로 입혀 메워서 평탄화하는 단계와, 상기 배선층으로의 접속공을 형성한후 상기 접속공 및 트렌치를 포함하는 전면에 제3금속층을 증착한후 상기 트렌치내의 절연막위의 제3금속층 부분 및 상기 접속공을 통하여 상기 배선층과 전기적으로 접속되는 제3금속층 부분이 남겨지도록 패터닝하여 인덕터를 형성하는 단계를 포함함을 특징으로 하고 있다.In order to achieve the object of the present invention, a method of manufacturing an inductor in a semiconductor device may include sequentially forming an oxide film and a first insulating layer on a substrate, and depositing a first metal layer on the first insulating layer. Forming a wiring layer by patterning the pattern, forming a second insulating layer on the entire surface of the substrate including the wiring layer, and depositing and patterning a second metal layer to be used as a mask on the second insulating layer, followed by patterning Etching to the inner depth of the substrate using the second metal layer as a mask, removing the trench and filling the trench with an insulating layer to planarize; forming a connection hole to the wiring layer; and forming a third hole on the front surface including the connection hole and the trench. Deposits a third metal layer portion over the insulating film in the trench and a third metal layer portion electrically connected to the wiring layer through the connection hole. Patterning to form a stretch to form an inductor.
본 발명의 목적을 달성하기 위한 또 하나의 다른 양태의 반도체 소자내의 인덕터 제조방법은, 반도체 기판상에 제1절연층을 형성하는 단계와, 상기 제1절연층상에 마스크로 사용한 제1금속층을 증착하여 인덕터가 형성될 위치에 따라 상기 제1금속층을 패터닝한후 상기 패터닝된 제1금속층을 마스크로 사용 기판 내부까지 식각하여 트랜치 구조를 형성하는 단계와, 상기 제1금속층을 식각하여 제거한후 상기 트렌치를 절연막으로 입혀서 메운후 평탄화하는 단계와, 상기 평탄화된 전면에 제2금속층을 증착한후 패터닝하여 상기 트렌치내의 절연막위에 인덕터의 배선을 형성하는 단계와, 상기 인덕터의 배선을 포함하는 전면에 제2절연막을 형성하는 단계와, 상기 인덕터 배선의 일단과 통하도록 접속공을 형성하는 단계와, 상기 접속공을 포함한 상기 제2절연막상에 제2금속층을 증착한후 상기 접속공을 통하여 인덕터 배선의 일단과 전기적으로 접속되게 상기 제3금속층을 패터닝하여 배선층을 형성하는 단계를 포함함을 특징으로 한다.In another aspect of the present invention, an inductor manufacturing method in a semiconductor device includes forming a first insulating layer on a semiconductor substrate and depositing a first metal layer used as a mask on the first insulating layer. Patterning the first metal layer according to a position where an inductor is to be formed, and etching the patterned first metal layer to an inside of a substrate using a mask as a mask to form a trench structure; and removing the first metal layer by etching and removing the trench. Forming a wiring of an inductor on the insulating film in the trench by patterning and depositing a second metal layer on the planarized front surface to form a wiring of the inductor on the front surface including the wiring of the inductor. Forming an insulating film, forming a connection hole to communicate with one end of the inductor wiring, and the second hole including the connection hole And depositing a second metal layer on the insulating layer to pattern the third metal layer to be electrically connected to one end of the inductor wiring through the connection hole to form a wiring layer.
이하 첨부도면에 근거하여 본 발명의 실시예를 설명한다.Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
[실시예 1]Example 1
도1은 본 발명의 인덕터 레이아웃을 모식적으로 나타낸 것이고, 도2a∼도2f는 도1의 A-A' 단면을 사용하여 본 발명의 인덕터 제조공정을 개략적으로 나타낸 것이다.FIG. 1 schematically shows the inductor layout of the present invention, and FIGS. 2A-2F schematically illustrate the inductor manufacturing process of the present invention using the AA ′ cross section of FIG. 1.
먼저 도2e와 같이 통상의 CMOS 공정순서에 따라 기판(10)상에 SiO2산화막(11)및 Si3N4의 절연체층(12)을 형성하여 상기 절연체층(12)위에 배선용 금속층을 증착시킨후 패터닝하여 배선층(13)을 형성한다.First, as shown in FIG. 2E, an insulator layer 12 of SiO 2 oxide film 11 and Si 3 N 4 is formed on a substrate 10 according to a general CMOS process procedure, and a wiring metal layer is deposited on the insulator layer 12. Subsequently, the wiring layer 13 is formed by patterning.
도2b와 같이 상기 배선층(13)을 포함하여 절연체층(12) 전면에 절연체층(12') 및 타이타늄(Ti)(14)을 증착시킨후 인덕터가 형성될야 10㎛ 폭의 타이타늄의 부위(15)가 제거되도록 타이타늄(14)을 식각한다.As shown in FIG. 2B, after the insulator layer 12 ′ and the titanium (Ti) 14 are deposited on the entire surface of the insulator layer 12 including the wiring layer 13, the inductor should be formed to have a portion of 10 μm wide titanium ( Etch the titanium 14 to remove 15).
이어 도2c와 같이 상기 타이타늄(14)을 마스크로 하여 기판 깊이까지 식각하여 트렌치(16)를 형성한다.Next, as shown in FIG. 2C, the trench 14 is formed by etching to the substrate depth using the titanium 14 as a mask.
그다음 도2d와 같이 타이타늄(14)을 완전 제거한후 트렌치(16)에 질화막(Si3N4)등의 절역막(17)을 입혀 평탄화한후 배선층(13)으로의 접속공(18)을 형성한후 도2e에 도시된 바와 같이 상기 평탄화된 전면에 인덕터를 형성할 금속층(19)을 증착시킨다.Next, as shown in FIG. 2D, after the titanium 14 is completely removed, the trench 16 is coated with a cut film 17 such as a nitride film (Si 3 N 4 ) to be planarized to form a connection hole 18 into the wiring layer 13. Then, as shown in FIG. 2E, a metal layer 19 to form an inductor is deposited on the planarized front surface.
그후 도2f와 같이 트렌치(16)내의 절연막(17)위 및 접속공(18)에 접속된 부위만을 남겨지도록 상기 금속층(19)을 식각하여 인덕터를 형성한후 도1에 도시된 바와 같이 상기 접속공(18)을 통하여 인더터의 일단과 접속된 배선층(13)과 인덕터의 타단을 각각 전극(가), (나)에 접속한다.Thereafter, as shown in FIG. 2F, the metal layer 19 is etched to form an inductor so as to leave only portions connected to the insulating layer 17 and the connection hole 18 in the trench 16, and then the connection as shown in FIG. 1. The wiring layer 13 connected to one end of the inductor and the other end of the inductor are connected to the electrodes (a) and (b) through the holes 18, respectively.
[실시예 2]Example 2
상기 실시예에서는 배선층(13)을 먼저 만든후 인덕터를 만들었으나, 실시예 2에서 인덕터를 먼저 만든후 절연층을 입히고 그 위에 배선층을 형성한다.In the above embodiment, the wiring layer 13 is first made, and then the inductor is made. In the second embodiment, the inductor is first made and then the insulating layer is coated to form the wiring layer thereon.
즉, 도3a에 도시된 바와 같이, 제1실시예와 같이 기판(10)위에 산화막(11) 및 절연체층(12)을 형성하고, 상기 절연체층(12)위에 타이타늄(Ti)(14)을 증착시킨후 인덕터가 형성될 부위를 패턴화 하고 도3b와 같이 상기 패턴화된 타이타늄(14)을 마스크로 기판(10) 깊이까지 식각하여 트렌치(16)를 형성하며, 도3c와 같이 상기 타이타늄(14)을 완전 제거하고 상기 트렌치(16)에 질화막(Si3N3) 등의 절연막(17)을 입혀 메운후 평탄화 한다.That is, as shown in FIG. 3A, the oxide film 11 and the insulator layer 12 are formed on the substrate 10 as in the first embodiment, and titanium (Ti) 14 is formed on the insulator layer 12. After the deposition, the region where the inductor is to be formed is patterned, and the trench 14 is formed by etching the patterned titanium 14 to the depth of the substrate 10 using a mask as shown in FIG. 3B, and the titanium ( 14) completely removed, and the trench 16 is filled with an insulating film 17 such as a nitride film (Si 3 N 3 ), and then flattened.
이어 도3d와 같이 상기 평탄화된 전면에 걸쳐 인덕터 형성용 금속층(19)을 형성한후 도3e와 같이 트렌치(16)의 절연막(17)위에만 금속층(19)이 남겨지도록 패턴화하여 상기 금속층(19)을 식각한다.Subsequently, as shown in FIG. 3D, the inductor forming metal layer 19 is formed over the planarized entire surface, and then the metal layer 19 is patterned such that the metal layer 19 remains only on the insulating film 17 of the trench 16 as shown in FIG. 3E. Etch 19).
이때 형성되는 금속층(19)은 도1의 레이아웃도에 도시된 바와 같은 와선형으로 된다.At this time, the metal layer 19 formed becomes a vortex as shown in the layout diagram of FIG.
그후 도3f와 같이 상기 금속층(19)을 포함한 전면에 절연체층(20)을 형성한 후 포토/식각 공정으로 금속층(19)의 일단에 이르도록 집속공(18)을 형성하고 상기 집속공(18)을 포함한 절연체층(20)위에 배선용 금속층(13)을 증착한후 패터닝하여 주변의 전극(도1 참조)과 연결되는 배선층(13)을 형성한다.Thereafter, as shown in FIG. 3F, an insulator layer 20 is formed on the entire surface including the metal layer 19, and then a focusing hole 18 is formed to reach one end of the metal layer 19 by a photo / etching process. The metal layer 13 for wiring is deposited on the insulator layer 20 including), and then patterned to form a wiring layer 13 connected to a peripheral electrode (see FIG. 1).
나머지 인덕터의 하단도 주변의 전극돠 통상의 방법으로 접속공을 형성하여 접속한다.The lower ends of the remaining inductors are also connected to each other by forming connection holes in the usual manner.
이상과 같이 본 발명의 제조방법은 기판 및 절연층에 트렌치를 형성하고 상기 트렌치내에 저항성분 및 커패시터 성분이 아주 낮은 절연물질로 입혀서 메우고, 이 절연물질위에만 인덕터용 배선을 형성하였기 때문에 상기 인덕터의 기판으로의 저항성분과 커패시터 성분을 대폭적으로 경감시킬수 있어 값, 삽입손실 및 공진주파수의 특성을 크게 개선할 수 있기 때문에 CMOS 등의 반도체 소자내에 형성하더라도 높은 동작주파수에서도 신호전달이 뛰어난 인덕터를 형성하도록 할수 있다는 효과가 있다.As described above, the manufacturing method of the present invention forms a trench in the substrate and the insulating layer, fills the trench with an insulating material having a very low resistance component and a capacitor component, and forms an inductor wiring only on the insulating material. Since the resistance component and capacitor component to the substrate can be greatly reduced, the characteristics of the value, insertion loss, and resonant frequency can be greatly improved. Therefore, even when formed in a semiconductor device such as CMOS, it is possible to form an inductor having excellent signal transmission even at a high operating frequency. There is an effect.
Claims (8)
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| KR1019960079257A KR100226835B1 (en) | 1996-12-31 | 1996-12-31 | Method for manufacturing inductor of semiconductor device |
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| KR100392254B1 (en) * | 2000-12-05 | 2003-07-23 | 한국전자통신연구원 | Thin film Inductor and Fabrication Method of Thin film Inductor |
| KR100611474B1 (en) * | 2003-12-30 | 2006-08-09 | 매그나칩 반도체 유한회사 | Method of manufacturing inductor in a semiconductor device |
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