KR100437862B1 - Circuit for driving P-channel Field Effective Transistor - Google Patents

Abstract

The present invention relates to a channel-effect transistor driving circuit, comprising: a first current mirror configured to output first to third currents having the same magnitude; A second current mirror configured to output fourth to sixth currents having the same magnitude; A load for lowering the power supply voltage and outputting a seventh current; A third current mirror configured to output eighth and ninth currents having the same magnitude; A fourth current mirror configured to separate the sixth current into a tenth current and an eleventh current, and input the tenth and eighth currents with the same magnitude; An input unit which inputs the fifth current and an external input signal, is activated when the input signal is at a high level to flow the fifth current, and is deactivated when the input signal is at a low level; A switching unit configured to input the fifth current and the eleventh current and to flow on the eleventh current when the input unit is deactivated and to be off when the input unit is activated; A resistor through which the ninth current flows; An amplifier connected to the switching unit and a resistor and inputting the eleventh current, inactivated when the switching unit is on, and activated when the switching unit is off, for flowing a ninth current flowing through the resistor; And an output unit connected to the amplifying unit to generate an output signal, outputting the output signal at a low level when the amplifying unit is activated, and outputting the output signal as a power supply voltage level when the amplifying unit is deactivated. The low level output signal is always output constantly.

Description

Circuit for driving P-channel Field Effective Transistor

The present invention relates to a channel-effect transistor driving circuit, and more particularly to a circuit for driving a channel-effect transistor used in the switching circuit.

FIG. 1 is a circuit diagram of a conventional buck converter having a channel-effect transistor driving circuit and a channel-effect transistor. Referring to FIG. 1, the conventional channel-channel field effect transistor driving circuit 101 includes resistors R1 and R2, NPN transistors Q1 and Q2, and diodes D1 and D2. 111 includes a channel-effect transistor 115, a diode D3, an inductor L1, capacitors C1 and C2, and a load 117.

An operation of the driving circuit 101 will be described. The input signal Vin is composed of a pulse signal as shown in FIG. When the input signal Vin is input, the NPN transistor Q2 repeats on / off. If the NPN transistor Q2 is turned on, a low level voltage is applied to the gate of the channel-effect transistor 115 so that the channel-effect transistor 115 is turned on. Power is supplied to the drain of the transistor 115. At this time, the voltage Vg applied to the gate of the channel-effect field transistor 115 is expressed by Equation 1 below.

Vg = Vcc-2 Vbe-Vce

Here, Vcc is the power supply voltage, and Vce is the collector-emitter voltage at the turn-on of the NPN transistor Q2.

According to Equation 1, the voltage Vout applied to the gate of the channel-effect field transistor 115 changes as the power supply voltage Vcc changes (211 in FIG. 2). That is, when the power supply voltage Vcc is increased, the voltage Vout applied to the gate of the field effect transistor 115 is increased, and when the power supply voltage 115 is decreased, it is applied to the gate of the channel effect transistor 115. The applied voltage Vout is reduced. Therefore, the output signal Vout fluctuates as shown in FIG. 2 (see 211).

In addition, when the NPN transistor Q2 is turned on, a current flowing through the resistor R1 is also input to the NPN transistor Q2, and the current at this time also changes as the power supply voltage Vcc changes.

When the voltage Vout applied to the gate of the channel-effect transistor 115 increases, the channel-effect transistor 115 is subjected to excessive switching stress, thereby lowering the reliability of the channel-effect transistor 115. . In addition, since the current flowing through the NPN transistor Q2 increases as the power supply voltage Vcc increases, the NPN transistor Q2 also receives a lot of switching stress.

An object of the present invention is to provide a channel-effect transistor driving circuit that reduces the switching stress applied to the channel-effect transistor connected to the output terminal by outputting a constant voltage in spite of the change in the power supply voltage.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

FIG. 1 is a circuit diagram of a conventional buck converter having a channel-effect transistor driving circuit and a channel-effect transistor.

FIG. 2 is a waveform diagram of an input signal and an output signal shown in FIG. 1.

3 is a block diagram of a channel-effect field effect transistor driving circuit according to a first embodiment of the present invention.

4 is a block diagram of a channel-effect transistor driving circuit according to a second embodiment of the present invention.

5 is a circuit diagram of a channel-effect field effect transistor driving circuit according to a third embodiment of the present invention.

6 is a waveform diagram of an input signal and an output signal illustrated in FIGS. 3 to 5.

The present invention to achieve the above technical problem,

A first current mirror configured to output first to third currents having the same magnitude; Input the first to third currents, output a fourth current corresponding to the first current, a fifth current corresponding to the second current, and a sixth current corresponding to the third current, and output the fourth current A second current mirror configured to output sixth to sixth currents having the same magnitude; A load for lowering the power supply voltage and outputting a seventh current; Inputting the third current and the seventh current, outputting an eighth current corresponding to the third current and a ninth current corresponding to the seventh current, and outputting the eighth and ninth currents with the same magnitude; A third current mirror; A fourth current mirror configured to separate the sixth current into a tenth current and an eleventh current, input the tenth and eighth currents, and allow the input current to flow in the same manner; An input unit which inputs the fifth current and an external input signal, is activated when the input signal is at a high level to flow the fifth current, and is deactivated when the input signal is at a low level; A switching unit configured to input the fifth current and the eleventh current and to flow on the eleventh current when the input unit is deactivated and to be off when the input unit is activated; A resistor through which the ninth current flows; An amplifier connected to the switching unit and a resistor and inputting the eleventh current, inactivated when the switching unit is on, and activated when the switching unit is off, for flowing a ninth current flowing through the resistor; And an output unit connected to the amplifying unit to generate an output signal, outputting the output signal at a low level when the amplifying unit is activated, and outputting the output signal as a power supply voltage level when the amplifying unit is deactivated. The low level output signal provides a channeled field effect transistor driving circuit which is always output constantly.

The present invention also to achieve the above technical problem,

A first reference voltage generator configured to output a first reference voltage and a first current; A load dropping the supply voltage; A second reference voltage generator configured to receive an output of the load and output a second reference voltage and a fourth current; A comparator for comparing the first and second reference voltages to output second and third currents; The second current is divided into a fifth current and a sixth current, a current mirror configured to input the fifth current and the third current and allow the input current to flow the same; An input unit configured to input the first current and an external input signal, to be activated when the input signal is at a high level, to flow the first current, and to be inactivated when the input signal is at a low level; A switching unit configured to input the first current and the sixth current, turn on when the input unit is inactivated to flow the sixth current, and turn off when the input unit is activated; A resistor connected to an output terminal of the second reference voltage generator; An amplifier connected to the switching unit and a resistor and inputting the sixth current, inactivated when the switching unit is turned on, and activated when the switching unit is turned off, to flow a current output from the resistor; And an output unit connected to the amplifying unit to generate an output signal, outputting the output signal at a low level when the amplifying unit is activated, and outputting the output signal as a power supply voltage level when the amplifying unit is deactivated. The low level output signal provides a channeled field effect transistor driving circuit which is always output constantly.

The present invention also to achieve the above technical problem,

A first resistor to which a power supply voltage is applied; A first PNP transistor having an emitter connected to the first resistor; A second PNP transistor having an emitter connected to the base and the collector of the first PNP transistor; A current source connected to the base and the collector of the second PNP transistor; A second resistor to which the power supply voltage is applied; A third PNP transistor having an emitter connected to the second resistor and a base connected to a base of the first PNP transistor; A fourth PNP transistor having an emitter connected to the collector of the third PNP transistor and a base connected to the base of the second PNP transistor, and outputting a first current; A third resistor to which the power supply voltage is applied; A fifth PNP transistor having an emitter connected to the third resistor and a base connected to the base of the first PNP transistor; A sixth PNP transistor having an emitter connected to a collector of the fifth PNP transistor, a base connected to a base of the second PNP transistor, and outputting a second current; A seventh PNP transistor having an emitter connected to the emitter of the sixth PNP transistor and outputting a third current; A fourth resistor to which the power supply voltage is applied; An eighth PNP transistor having a base connected to a base of the seventh PNP transistor; A ninth PNP transistor having an emitter connected to the fourth resistor and a base and a collector connected to the emitter of the eighth PNP transistor; A fifth resistor connected to the collector of the eighth PNP transistor; An input unit configured to input the first current and an external input signal, to be activated when the input signal is at a high level, to flow the first current, and to be inactivated when the input signal is at a low level; The second current is divided into a fifth current and a sixth current, a current mirror configured to input the fifth current and the third current, and allow the input current to have the same magnitude; A switching unit configured to input the first current and the second current, turn on when the input unit is inactivated to flow the second current, and turn off when the input unit is activated; An amplifier connected to the switching unit and a fifth resistor and inputting the second current, deactivated when the switching unit is on, and activated when the switching unit is off, and flowing current outputted from the fifth resistor; And an output unit connected to the amplifying unit to generate an output signal, outputting the output signal at a low level when the amplifying unit is activated, and outputting the output signal as a power supply voltage level when the amplifying unit is deactivated. The low level output signal provides a channeled field effect transistor driving circuit which is always output constantly.

According to the present invention, the low level output signal of the channel-effect transistor driving circuit is constantly output.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is a block diagram of a channel-effect field effect transistor driving circuit according to a first embodiment of the present invention. Referring to FIG. 3, the channel-effect field effect transistor driving circuit 301 includes first to fourth current mirrors 311 to 314, a current source 321, a load 331, a resistor 341, and an input unit 351. And a switching unit 361, an amplifier 371 and an output 381.

The first current mirror 311 outputs first to third currents i1 to i3 having the same magnitude.

The second current mirror 312 inputs first to third currents i1 to i3 and outputs fourth to sixth currents i4 to i6 having the same magnitude. The fourth current i4 is output corresponding to the first current i1, the fifth current i5 is output corresponding to the second current i2, and the sixth current i6 is the third current i3. Is output corresponding to). That is, the first current i1 is amplified and output as the fourth current i4, the second current i2 is amplified and output as the fifth current i5, and the third current i3 is amplified and It is output as 6 current i6. The sixth current i6 is divided into a tenth current i10 and an eleventh current i11.

Since the fourth current i4 flows to the ground terminal GND through the current source 321, the fourth current i4 is always constant.

The load 331 drops the power supply voltage Vcc and outputs it. The load 331 outputs a seventh current i7 from the load 331.

The third current mirror 313 inputs the third and seventh currents i3 and i7 and outputs the eighth and ninth currents i8 and i9 having the same magnitude. The eighth current i8 is output in correspondence with the third current i3, and the ninth current i9 is output in correspondence with the seventh current i7. That is, the third current i3 is amplified and output as the eighth current i8, and the seventh current i7 is amplified and output as the ninth current i9.

The ninth current i9 is applied to the amplifier 371 through the resistor 341. The low level of the output signal Vout varies according to the value of the resistor 341. That is, when the value of the resistor 341 is increased, the low level of the output signal Vout is lower, and when the value of the resistor 341 is decreased, the low level of the output signal Vout is higher.

The fourth current mirror 314 inputs the tenth and eighth currents i10 and i8 and controls the tenth and eighth currents i10 and i8 to flow in the same manner.

The input unit 351 inputs an external input signal Vin consisting of a fifth current i5 and a pulse. The input signal Vin is composed of pulses that repeat a high level and a low level. If the input signal Vin is at the high level, the input unit 351 is activated to flow the fifth current i5 to the inside. If the input signal Vin is at the low level, the input unit is deactivated to not input the fifth current i5. Do not.

The switching unit 361 is connected to the amplifier 371 and inputs fifth and eleventh currents i5 and i11. When the input unit 351 is deactivated, the fifth current i5 is not input to the input unit 351 but is input to the switching unit 361. Accordingly, the switching unit 361 is turned on so that the eleventh current i11 is input into the switching unit 361. When the input unit 351 is activated, since the fifth current i5 is input to the input unit 351, the switching unit 361 is turned off, and thus the eleventh current i11 is not input to the switching unit 361.

The ninth current i9 flows through the resistor 341 to the amplifier 371. By changing the value of the resistor 341, the low level of the output signal Vout can be adjusted. In other words, when the value of the resistor is increased, the low level of the output signal Vout is lower, and when the value of the resistor is decreased, the low level of the output signal Vout is higher.

The amplifier 371 is connected to the switching unit 361 and the node N1 and inputs an eleventh current i11. The amplifier 371 is inactivated when the eleventh current i11 is input to the switching unit 361 when the switching unit 361 is turned on, and is activated when the switching unit 361 is turned off and is outputted through the resistor 9401. 9 Amplify by inputting current i9. When the switching unit 361 is activated, the node N1 is lowered to the ground voltage GND level.

The output unit 381 is connected to the node N1 to generate an output signal Vout. When the amplifier 371 is activated, the output signal Vout is output at a low level. When the amplifier 371 is deactivated, the output signal Vout is output at a high level, that is, a power supply voltage Vcc level.

An operation of the channel-effect transistor driving circuit shown in FIG. 3 will be described.

If the input signal Vin is at a high level, the input unit 351 is activated, the switching unit 361 is turned off, and the amplifying unit 371 is activated. When the amplifier 371 is activated, the output signal Vout is lowered to a low level. In this state, when the power supply voltage Vcc increases, the voltage applied to the load 331 increases to increase the seventh current i7. Then, the ninth current i9 is increased to increase the voltage of the node N1. However, when the ninth current i9 is increased, the eighth current i8 is also increased, thereby increasing the tenth current i10. Then, since the sixth current i6 is always constant, the eleventh current i11 decreases. When the eleventh current i11 is decreased, the amplifier 371 is activated to be small so that the amount of input of the ninth current i9 to the amplifier 371 is reduced, so that the voltage of the node N1 is kept constant. Therefore, the magnitude of the output signal Vout is kept constant.

On the contrary, when the power supply voltage Vcc decreases, the voltage applied to the load 331 decreases and the seventh current i7 decreases. Then, the ninth current i9 is decreased to reduce the voltage of the node N1. However, when the ninth current i9 decreases, the eighth current i8 also decreases, thereby decreasing the tenth current i10. Then, since the sixth current i6 is always constant, the eleventh current i11 increases. When the eleventh current i11 increases, the amplifier 371 is greatly activated, and the amount of the ninth current input to the amplifier 371 increases, so that the voltage of the node N1 is kept constant. Therefore, the magnitude of the output signal Vout is kept constant.

If the input signal Vin is at a low level, the input unit 351 is inactivated, and accordingly, the switching unit 361 is turned on and the amplifying unit 9937 is inactivated. Therefore, the output signal Vout is output at a high level.

As described above, when the output signal Vout is at the low level, the output signal Vout is constantly output despite the change in the power supply voltage Vcc, thereby connecting the channel-effect field transistors connected to the driving circuit 301 (see FIG. 1). 115 is subjected to a small switching stress, thereby improving the reliability of the channel-effect transistor (115 in FIG. 1).

4 is a block diagram of a channel-effect transistor driving circuit according to a second embodiment of the present invention. Referring to FIG. 4, the P-channel field effect transistor driving circuit 401 includes first and second reference voltage generators 411 and 412, a load 441, a resistor 451, a comparator 421, and a current mirror 431. ), An input unit 461, a switching unit 471, an amplifier 481, and an output unit 491.

The first reference voltage generator 411 outputs the first reference voltage Vref1 and the first current i1.

The load 441 drops the power supply voltage Vcc and outputs a predetermined current.

The second reference voltage generator 412 inputs a current output from the load 441 and outputs a second reference voltage Vref2 and a fourth current i4.

The fourth current i4 is input to the amplifier 481 through the resistor 451. The low level of the output signal Vout varies according to the value of the resistor 451. That is, when the value of the resistor 451 is increased, the low level of the output signal Vout is lower, and when the value of the resistor 451 is reduced, the low level of the output signal Vout is higher.

The comparator 421 inputs the first and second reference voltages Vref1 and Vref2 and outputs the second and third currents i2 and i3. Since the first reference voltage Vref1 is kept constant, the amount of the second current i2 generated by the first reference voltage Vref1 is always constant. Therefore, when the second reference voltage Vref2 increases, the third current i3 increases. On the contrary, when the second reference voltage Vref2 decreases, the third current i3 decreases. When the second reference voltage Vref2 increases, the fourth current i4 increases, and when the second reference voltage Vref2 decreases, the fourth current i4 decreases. The second current i2 is separated into a fifth current i5 and a sixth current i6.

The current mirror 431 inputs the fifth current i5 and the third current i3, and controls the input current to flow in the same manner.

The input unit 461 inputs an external input signal Vin consisting of a first current i1 and a pulse. The input signal Vin is composed of pulses that repeat a high level and a low level. If the input signal Vin is at a high level, the input unit 461 is activated to flow the first current i1 therein. If the input signal Vin is at a low level, the input unit 461 is deactivated to make the first current i1. Do not enter.

The switching unit 471 is connected to the amplifier 481 and inputs first and sixth currents i1 and i6. When the input unit 461 is deactivated, the first current i1 is not input to the input unit 461, but is input to the switching unit 471. The switching unit 471 is turned on so that the sixth current i6 is the switching unit 471. ) Is entered. When the input unit 461 is activated, since the first current i1 is input to the input unit 461, the switching unit 471 is turned off, and accordingly, the sixth current i6 is not input to the switching unit 471.

The amplifier 481 is connected to the switching unit 471 and the node N1 and inputs a sixth current i6. The amplifier 481 is deactivated when the sixth current i6 is input to the switching unit 471 when the switching unit 471 is turned on, and is activated when the switching unit 471 is turned off and output through the resistor 451. The fourth current i4 is input and amplified. When the switching unit 471 is activated, the node N1 is lowered to the ground voltage GND level.

The output unit 491 is connected to the node N1 to generate an output signal Vout. When the amplifier 481 is activated, the output signal Vout is output at a low level. When the amplifier 481 is deactivated, the output signal Vout is output at a high level, that is, a power supply voltage Vcc level.

The operation of the channel-effect transistor driving circuit 401 shown in FIG. 4 will be described.

If the input signal Vin is at a high level, the input unit 461 is activated, the switching unit 471 is turned off, and the amplifier 481 is activated. When the amplifier 481 is activated, the output signal Vout is lowered to a low level. In this state, when the power supply voltage Vcc increases, the voltage applied to the load 441 increases and the fourth current i4 increases. As the fourth current i4 increases, the voltage of the node N1 also increases. However, when the fourth current i4 is increased, the third current i3 is also increased, thereby increasing the fifth current i5. Then, since the second current i2 is always constant, the sixth current i6 is relatively decreased. When the sixth current i6 decreases, the amplifier 481 is activated to be small so that the amount of input of the fourth current i4 to the amplifier 481 is reduced, so that the voltage of the node N1 is kept constant without increasing. do. Therefore, the magnitude of the output signal Vout is kept constant.

On the contrary, when the power supply voltage Vcc decreases, the voltage applied to the load 441 decreases and the fourth current i4 decreases. When the fourth current i4 decreases, the voltage of the node N1 decreases. However, when the fourth current i4 decreases, the third current i3 also decreases, thereby decreasing the fifth current i5. When the fifth current i5 decreases, the second current i2 is always constant, so that the sixth current i6 increases relatively. When the sixth current i6 increases, the amplifier 481 is greatly activated, and the amount of the fourth current i4 input to the amplifier 481 increases, so that the voltage of the node N1 is kept constant. Therefore, the magnitude of the output signal Vout is kept constant.

If the input signal Vin is at a low level, the input unit 461 is inactivated, and accordingly, the switching unit 471 is turned on to deactivate the amplifying unit 481. Therefore, the output signal Vout is output at a high level.

As such, when the output signal Vout is at a low level, the output signal Vout is constantly output despite the change in the power supply voltage Vcc, thereby connecting the channel-effect field transistors connected to the driving circuit 401 (see FIG. 1). 115 is subjected to a small switching stress, thereby improving the reliability of the channel-effect transistor (115 in FIG. 1).

5 is a circuit diagram of a channel-effect field effect transistor driving circuit according to a third embodiment of the present invention. Referring to FIG. 5, the P-channel field effect transistor driving circuit 501 may include first to fifth resistors R1 to R5, first to ninth PNP transistors PQ1 to PQ9, a current source 511, and an input unit. 521, a current mirror 531, a switching unit 541, an amplifier 551, and an output unit 561.

A power supply voltage Vcc is applied to the first resistor R1, an emitter of the first PNP transistor PQ1 is connected to the first resistor R1, and an emitter of the second PNP transistor PQ2 is connected to the first resistor R1. A current source 511 connected to the base and the collector of the PNP transistor PQ1 is connected to the base and the collector of the second PNP transistor PQ2. Thus, a constant reference current (iref) always flows through the current source 511.

The power supply voltage Vcc is applied to the second resistor R2, the emitter of the third PNP transistor PQ3 is connected to the second resistor R2, and the second resistor R2 and the first PNP transistor PQ1 are connected to the second resistor R2. The emitter and the base of the third PNP transistor (PQ3) are respectively connected to the base of), and the collector of the third PNP transistor (PQ3) and the emitter of the fourth PNP transistor (PQ4) are connected to the base of the second PNP transistor (PQ2). And base are respectively connected, and the first current i1 is output from the collector of the fourth PNP transistor PQ4. Since the first and third PNP transistors PQ1 and PQ3 and the second and fourth PNP transistors PQ2 and PQ4 constitute current mirrors, the first current i1 is the reference current irf and its magnitude. Is the same.

The power supply voltage Vcc is applied to the third resistor R3, the emitter of the fifth PNP transistor PQ5 is connected to the third resistor R3, and the third resistor R3 and the third PNP transistor PQ3. The emitter and the base of the fifth PNP transistor (PQ5) are respectively connected to the base of), and the collector of the fifth PNP transistor (PQ5) and the emitter of the sixth PNP transistor (PQ6) are connected to the base of the fourth PNP transistor (PQ4). And the base are respectively connected, and the second current i2 is output from the collector of the sixth PNP transistor PQ6. The second current i2 is divided into a fifth current i5 and a sixth current i6 and input to the current mirror 531, the switching unit 541, or the amplifier 551, respectively. Since the first and fifth PNP transistors PQ1 and PQ5 and the second and sixth PNP transistors PQ2 and PQ6 respectively constitute a current mirror, the second current i2 is the reference current irf and its magnitude. Is the same.

The emitter of the seventh PNP transistor PQ7 is connected to the emitter of the sixth PNP transistor PQ6, and the third current i3 is output from the collector of the seventh PNP transistor PQ7. The voltage applied to the base of the sixth PNP transistor PQ6 and the voltage applied to the base of the seventh PNP transistor PQ7 are compared. That is, when the voltage applied to the gate of the seventh PNP transistor PQ7 is higher than the voltage applied to the base of the sixth PNP transistor PQ6, the third current i3 increases, and vice versa, the third current i3. Decreases.

The power supply voltage Vcc is applied to the fourth resistor R4, an emitter of the ninth PNP transistor PQ9 is connected to the fourth resistor R4, and a base is applied to the base and the collector of the ninth PNP transistor PQ9. 8 The emitter of the PNP transistor PQ8 is connected, the base of the eighth PNP transistor PQ8 is connected to the base of the seventh PNP transistor PQ7, and the fourth current i4 from the collector of the eighth PNP transistor PQ8. ) Is output to the amplifier 551 through the fifth resistor R5.

Since the seventh PNP transistor PQ7 and the eighth PNP transistor PQ8 form a current mirror, the fourth current i4 and the third current i3 have the same magnitude.

The output unit 561 may include a sixth resistor R6 connected between the power supply voltage Vcc and the node N1, a seventh resistor R7 connected between the node N1 and the amplifier 551, and a power supply voltage Vcc. ) Is applied to the collector, the base is connected to node N1, and the emitter is the first NPN transistor NQ1 connected to the output node N2, the power supply voltage Vcc is applied to the collector and the base, and to the output node N2. A second NPN transistor NQ2 to which the emitter is connected, and a third NPN transistor NQ3 to which the collector and the base are connected to the output node N2 and the emitter is connected to the node N1 are provided. The output signal Vout of the drive circuit is output from the output node N2. When the amplifier 551 is activated, the first NPN transistor NQ1 is turned off so that a current flows through the sixth and seventh resistors R6 and R7 to the amplifier 551, whereby the node N3 As the voltage is lowered, the output signal Vout is lowered to the low level. When the amplifier 551 is deactivated, current does not flow through the sixth and seventh resistors R6 and R7, so the first NPN transistor NQ1 is turned on so that the output signal Vout is at a high level, that is, a power supply voltage ( Vcc) level is increased.

The current mirror 531 is a fifth NPN transistor NQ5 having a fifth current i5 input to the collector and an emitter grounded, and a third current i3 is input to the collector and base, and the base has a fifth NPN transistor ( The emitter has a sixth NPN transistor NQ6 connected to the base of NQ5) and is grounded. The fifth current i5 and the third current i3 flow in the same magnitude by the current mirror 531.

The input unit 521 has an eighth resistor R8 to which an external input signal Vin is input, an output of the eighth resistor R8 is input to the base, a first current i1 is input to the collector, and the emitter is grounded. A fourth NPN transistor NQ4 is provided. The input signal Vin is composed of pulses that repeat a high level and a low level. When the input signal Vin is at a high level, the fourth NPN transistor NQ4 is turned on, that is, the input unit 521 is activated, so that the first current i1 is transferred to the ground terminal GND through the fourth NPN transistor NQ4. When the input signal Vin is at a low level, the fourth NPN transistor NQ4 is turned off, that is, the input unit 521 is deactivated and the first current i1 is not input to the input unit 521.

The switching unit 541 has a base and a ground terminal GND of a seventh NPN transistor NQ7 and a seventh NPN transistor NQ7 having a first current i1 input to a base and a sixth current i6 input to a collector. 11th resistor (R9) connected between the ninth resistor (R10) connected between the emitter of the seventh NPN transistor (NQ7) and the ground terminal (GND), the first current (i1) R11) and a base connected to the eleventh resistor R11, a collector connected to the amplifier 551, and the emitter includes an eighth NPN transistor NQ8 grounded. When the input unit 521 is deactivated, the first current i1 is not input to the input unit 521, but is input to the seventh and eighth NPN transistors NQ7 and NQ8, and thus the seventh and eighth NPN transistors NQ7 and NQ8. Turn on). Then, the sixth current I6 flows to the ground terminal GND through the seventh NPN transistor NQ7. When the sixth current i6 is input to the switching unit 541, the sixth current i6 is not input to the amplifier 551, and thus the amplifier 551 is deactivated at this time. If the input unit 521 is activated, since the first current i1 is input to the input unit 521, the switching unit 541 is turned off, and accordingly, the sixth current i6 is not input to the switching unit 541.

The amplifier 551 has a ninth NPN transistor NQ9 and a ninth NPN transistor NQ9 having a sixth current i6 input thereto as a base, a collector connected to the node N3, and an emitter connected to the switching unit 541. The capacitor 555 is connected between the collector and the base of the (), and the collector and the base are connected to the collector and the emitter of the ninth NPN transistor (NQ9), respectively, and the emitter has a tenth NPN transistor (NQ10) grounded. The amplifier 551 is deactivated when the sixth current i6 is input to the switching unit 541 when the switching unit 541 is turned on, and the sixth current i6 is the ninth NPN when the switching unit 541 is turned off. Since the ninth NPN transistor NQ9 is input to the base of the transistor NQ9 and the ninth NPN transistor NQ9 is turned on, the fourth current i4 output from the fifth resistor R5 is used to replace the ninth and tenth NPN transistors NQ (, NQ10). Therefore, the voltage of the node N3 is lowered to the low level, that is, the ground voltage level, and the capacitor 555 serves as an compensation capacitor to include the AC component included in the current applied to the gate of the ninth NPN transistor NQ9. By-passing causes the amplifier 551 to perform a stable amplification operation.

The operation of the channel-effect field driving transistor driving circuit 501 shown in FIG. 5 will be described.

When the input signal Vin is at a high level, the fourth NPN transistor NQ4 is turned on so that the seventh and eighth NPN transistors NQ7 and NQ8 are turned off, and instead, the ninth and tenth NPN transistors NQ9 and NQ10 are turned off. ) Is turned on. Then, since the voltage of the node N3 drops, the output signal Vout is lowered to a low level. In this state, when the power supply voltage Vcc increases, voltages applied to the fourth and fifth resistors R4 and R5 and the eighth and ninth PNP transistors NQ8 and NQ9 increase, thereby increasing the fourth current i4. Increases. As the fourth current i4 increases, the voltage of the node N3 also increases. However, when the fourth current increases, the third current i3 also increases, thereby increasing the fifth current i5. Then, since the second current i2 is always constant, the sixth current i6 is relatively decreased. When the sixth current i6 decreases, the ninth and tenth NPN transistors NQ9 and NQ10 are weakly turned on, thereby reducing the amount of input of the fourth current i4 to the amplifier 551, thereby reducing the amount of the node N3. The voltage does not increase and remains constant. Therefore, the magnitude of the output signal Vout is kept constant.

On the contrary, when the power supply voltage Vcc decreases, voltages applied to the fourth and fifth resistors R4 and R5 and the eighth and ninth PNP transistors NQ8 and NQ9 decrease to decrease the fourth current i4. do. When the fourth current i4 decreases, the voltage of the node N3 decreases. However, when the fourth current i4 decreases, the third current i3 also decreases, thereby decreasing the fifth current i5. When the fifth current i5 decreases, the second current i2 is always constant, so that the sixth current i6 increases relatively. When the sixth current i6 is increased, the ninth and tenth NPN transistors NQ9 and NQ10 are turned on greatly, and the amount of input of the fourth current i4 to the amplifier 551 is increased, so that the node N3 is increased. The voltage of is kept constant. Therefore, the magnitude of the output signal Vout is kept constant.

When the input signal Vin is at a low level, the fourth NPN transistor NQ4 is turned off, and accordingly, the seventh and eighth NPN transistors NQ7 and NQ8 are turned on, and the ninth and tenth NPN transistors NQ9 and NQ4 are turned on. NQ10) is turned off. Therefore, the output signal Vout is at a high level.

As described above, when the output signal Vout is at the low level, the output signal Vout is constantly output despite the change in the power supply voltage Vcc, thereby connecting the channel-effect transistor (Fig. 1) connected to the driving circuit 501. 115 is subjected to a small switching stress, thereby improving the reliability of the channel-effect transistor (115 in FIG. 1). In addition, the switching stress applied to the ninth and tenth NPN transistors NQ9 and NQ10 is reduced.

6 is a waveform diagram of an input signal Vin and an output signal Vout illustrated in FIGS. 3 to 5. Referring to FIG. 6, it can be seen that the output signal Vout is at the low level when the input signal Vin is at the high level, and the magnitude 611 of the output signal Vout at this time is constant.

The best embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, according to the present invention, when the output signal Vout of the channel-effect field effect transistor driving circuit is at the low level, the output signal Vout is constantly output (see 611 of FIG. 6). Therefore, the switching stress applied to the channel-effect transistors connected to the channel-effect transistor driving circuit is reduced, so that the reliability of the channel-effect transistors is improved. In addition, the low level of the output signal Vout may be adjusted by adjusting the values of the resistors 341, 451, and R5.

Claims (10)

A first current mirror configured to output first to third currents having the same magnitude; Input the first to third currents, output a fourth current corresponding to the first current, a fifth current corresponding to the second current, and a sixth current corresponding to the third current, and output the fourth current A second current mirror configured to output sixth to sixth currents having the same magnitude; A load for lowering the power supply voltage and outputting a seventh current; Inputting the third current and the seventh current, outputting an eighth current corresponding to the third current and a ninth current corresponding to the seventh current, and outputting the eighth and ninth currents with the same magnitude; A third current mirror; A fourth current mirror configured to separate the sixth current into a tenth current and an eleventh current, input the tenth and eighth currents, and allow the input current to flow in the same manner; An input unit which inputs the fifth current and an external input signal, is activated when the input signal is at a high level to flow the fifth current, and is deactivated when the input signal is at a low level; A switching unit configured to input the fifth current and the eleventh current and to flow on the eleventh current when the input unit is deactivated, and to be off when the input unit is activated; A resistor through which the ninth current flows; An amplifier connected to the switching unit and a resistor and inputting the eleventh current, inactivated when the switching unit is on, and activated when the switching unit is off, for flowing a ninth current flowing through the resistor; And The output unit connected to the amplifying unit to generate an output signal, and outputting the output signal at a low level when the amplifying unit is activated, and outputting the output signal as a power supply voltage level when the amplifying unit is deactivated. A channel-effect transistor driving circuit according to claim 1, wherein the output signal of the level is always output constantly. 2. The channel-effect transistor driving circuit according to claim 1, wherein the output signal at the low level is lower when the resistance value is increased, and the output signal at the low level is higher when the resistance value is decreased. A first reference voltage generator configured to output a first reference voltage and a first current; A load dropping the supply voltage; A second reference voltage generator configured to receive an output of the load and output a second reference voltage and a fourth current; A comparator for comparing the first and second reference voltages to output second and third currents; The second current is divided into a fifth current and a sixth current, a current mirror configured to input the fifth current and the third current and allow the input current to flow the same; An input unit configured to input the first current and an external input signal, to be activated when the input signal is at a high level, to flow the first current, and to be inactivated when the input signal is at a low level; A switching unit configured to input the first current and the sixth current, turn on when the input unit is inactivated to flow the sixth current, and turn off when the input unit is activated; A resistor connected to an output terminal of the second reference voltage generator; An amplifier connected to the switching unit and a resistor and inputting the sixth current, inactivated when the switching unit is turned on, and activated when the switching unit is turned off, to flow a current output from the resistor; And The output unit connected to the amplifying unit to generate an output signal, and outputting the output signal at a low level when the amplifying unit is activated, and outputting the output signal as a power supply voltage level when the amplifying unit is deactivated. A channel-effect transistor driving circuit according to claim 1, wherein the output signal of the level is always output constantly. 4. The channel-effect transistor driving circuit of claim 3, wherein the output signal of the low level is lower when the resistance value is increased, and the output signal of the low level is higher when the resistance value is decreased. A first resistor to which a power supply voltage is applied; A first PNP transistor having an emitter connected to the first resistor; A second PNP transistor having an emitter connected to the base and the collector of the first PNP transistor; A current source connected to the base and the collector of the second PNP transistor; A second resistor to which the power supply voltage is applied; A third PNP transistor having an emitter connected to the second resistor and a base connected to a base of the first PNP transistor; A fourth PNP transistor having an emitter connected to the collector of the third PNP transistor and a base connected to the base of the second PNP transistor, and outputting a first current; A third resistor to which the power supply voltage is applied; A fifth PNP transistor having an emitter connected to the third resistor and a base connected to the base of the first PNP transistor; A sixth PNP transistor having an emitter connected to a collector of the fifth PNP transistor, a base connected to a base of the second PNP transistor, and outputting a second current; A seventh PNP transistor having an emitter connected to the emitter of the sixth PNP transistor and outputting a third current; A fourth resistor to which the power supply voltage is applied; An eighth PNP transistor having a base connected to a base of the seventh PNP transistor; A ninth PNP transistor having an emitter connected to the fourth resistor and a base and a collector connected to the emitter of the eighth PNP transistor; A fifth resistor connected to the collector of the eighth PNP transistor; An input unit configured to input the first current and an external input signal, to be activated when the input signal is at a high level, to flow the first current, and to be inactivated when the input signal is at a low level; The second current is divided into a fifth current and a sixth current, a current mirror configured to input the fifth current and the third current, and allow the input current to have the same magnitude; A switching unit configured to input the first current and the second current, turn on when the input unit is inactivated to flow the second current, and turn off when the input unit is activated; An amplifier connected to the switching unit and a fifth resistor and inputting the second current, inactivated when the switching unit is turned on, and activated when the switching unit is turned off, and flowing current output from the fifth resistor; And The output unit connected to the amplifying unit to generate an output signal, and outputting the output signal at a low level when the amplifying unit is activated, and outputting the output signal as a power supply voltage level when the amplifying unit is deactivated. A channel-effect transistor driving circuit according to claim 1, wherein the output signal of the level is always output constantly. The method of claim 5, wherein the output unit A sixth resistor connected between the power supply voltage and a node; A seventh resistor connected between the node and the amplifier; The power supply voltage is applied to the collector, the base is connected to the node, and the emitter comprises: a first NPN transistor; A second NPN transistor having the power supply voltage applied to the collector and the base and having an emitter connected to the output node; And And a third NPN transistor having a collector and a base connected to the output node and an emitter connected to the node. The method of claim 5, wherein the input unit An eighth resistor to which the input signal is input; And And an output of the eighth resistor is input to the base, the first current is input to the collector, and the emitter has a grounded fourth NPN transistor. The method of claim 5, wherein the current mirror A fifth NPN transistor in which the fifth current is input to the collector and the emitter is grounded; And And the third current is input to the collector and the base, the base is connected to the base of the fifth NPN transistor, and the emitter has a grounded sixth NPN transistor. The method of claim 5, wherein the switching unit A seventh NPN transistor in which the first current is input to the base and the sixth current is input to the collector; A ninth resistor connected between the base and the ground terminal of the seventh NPN transistor; A tenth resistor connected between the emitter and the ground terminal of the second NPN transistor; An eleventh resistor to which the first current is input; And And a base connected to the eleventh resistor, a collector connected to the amplifying unit, and an emitter having an eighth NPN transistor which is grounded. The method of claim 5, wherein the amplification unit A ninth NPN transistor having a sixth current input to a base, a collector connected to the fifth and seventh resistors, and an emitter connected to the switching unit; A capacitor connected between the collector and the base of the ninth NPN transistor; And And a collector connected to the collector of the ninth NPN transistor, a base connected to the emitter of the ninth NPN transistor, and the emitter having a tenth NPN transistor which is grounded.