KR100424186B1 - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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KR100424186B1
KR100424186B1 KR1019970030417A KR19970030417A KR100424186B1 KR 100424186 B1 KR100424186 B1 KR 100424186B1 KR 1019970030417 A KR1019970030417 A KR 1019970030417A KR 19970030417 A KR19970030417 A KR 19970030417A KR 100424186 B1 KR100424186 B1 KR 100424186B1
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layer
solution
oxide layer
resist pattern
silicon oxide
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KR1019970030417A
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Korean (ko)
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KR19990006195A (en
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박병준
조성윤
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to simplify a fabricating process and prevent etching residue from being attached to the inner wall of etching equipment by removing a silicon oxide layer from a desired resist pattern composed of a photoresist layer, a silylation layer and the silicon oxide layer and by simultaneously removing the photoresist layer and the silylation layer while using a TMAH(tetra methyl ammonium hydroxide) solution. CONSTITUTION: The silicon oxide layer(6) of the desired resist pattern(10) is eliminated by using an oxide layer etching solution. The silylation layer(5) and the photoresist layer(2) are simultaneously eliminated by using a TMAH solution wherein the etch process is performed while ultrasonic vibration is applied to the TMAH solution or N2 gas bubble occurs in the TMAH solution.

Description

반도체 소자의 제조방법Manufacturing method of semiconductor device

본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 구체적으로는 반도체 소자에서 마스크 패턴으로 이용되는 레지스트 패턴의 제거방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of removing a resist pattern used as a mask pattern in a semiconductor device.

일반적으로, 반도체 기술의 진보와 더불어 더 나아가서는 반도체 소자의 고속화, 고집적화가 진행되고 있고, 이에 수반해서 패턴에 대한 미세화의 필요성이점점 높아지고 있으며, 또한 패턴의 칫수도 고정밀화가 요구되고 있다.In general, with the progress of semiconductor technology, further, the speed and integration of semiconductor devices are progressing. As a result, the necessity of miniaturization of the pattern is increasing, and the size of the pattern is also required to be highly precise.

이러한 미세한 패턴을 형성하기 위하여, 종래에는 레지스트막을 노광, 현상 등에 의하여 부분적으로 제거하지 않고, 식각처리하여 소정 부분을 제거하여, 미세한 패턴을 형성하는 기술이 제안되었다. 이러한 기술로는, TRI(tri-layer resist) 또는 디자이어(DESIRE:diffusion enhanced silylated resist) 방법이 있다.In order to form such a fine pattern, conventionally, a technique of forming a fine pattern by removing a predetermined portion by etching, without partially removing the resist film by exposure or development, has been proposed. Such a technique includes a tri-layer resist (TRI) or design (diffusion enhanced silylated resist) method.

여기서, 도 1A 내지 도 1C는 종래의 DESIRE 방법에 따른 레지스트 패턴 형성방법의 전형적인 일예를 도시한 것으로서, 도면을 참조하여 설명하도록 한다.1A to 1C illustrate a typical example of a resist pattern forming method according to a conventional DESIRE method, which will be described with reference to the drawings.

먼저, 도 1A를 참조하여, 단차를 갖는 반도체 기판(1) 상부에 결과물이 평탄화되도록 비교적 후막으로 포토레지스트층(2)이 도포된다. 그후, 포토레지스트층(2) 상부에 패턴 예정 부분이 노출되도록 레티클(3)이 적절히 배치된다음, 빛을 인가하여 노광한다. 이때, 노광 공정은 포토레지스트층(2)의 소정 두께만큼이 노광될 수 있도록 얕은 노광(shallow expose) 공정을 실시한다. 이때, 미설명 부호 4는 노광이 이루어진 포토레지스트층을 나타낸다.First, referring to FIG. 1A, a photoresist layer 2 is applied to a relatively thick film so that the resultant is planarized on the semiconductor substrate 1 having a step. Thereafter, the reticle 3 is appropriately disposed so that the pattern predetermined portion is exposed on the photoresist layer 2, and then light is applied by exposure. At this time, the exposure process is to perform a shallow exposure process so that the predetermined thickness of the photoresist layer (2) can be exposed. In this case, reference numeral 4 denotes a photoresist layer in which exposure is performed.

그후, 도 1B에 도시된 바와 같이, 레티클(3)을 제거한다음, 실리콘 이온을 노광된 부분에 확산시키어, 실리콘이 확산된 노광층(이하, 실릴레이션층: 5)을 형성한다.Thereafter, as shown in Fig. 1B, the reticle 3 is removed, and then silicon ions are diffused into the exposed portions to form an exposure layer (hereinafter referred to as a silicide layer 5) in which silicon is diffused.

그리고나서, 도 1C에서와 같이, 실릴레이션층(5)을 마스크로 하여, 포토레지스트막(2)을 산소 플라즈마 식각하여, 레지스트 패턴(10)을 형성한다. 이때, 산소 플라즈마 식각 공정시, 실릴레이션층(5)의 일부는 상기 산소 플라즈마에 의하여 산화되어, 레지스트 패턴(10)의 최상단 부분에는 실리콘 산화층(6)이 형성된다.Then, as shown in FIG. 1C, the photoresist film 2 is etched by oxygen plasma using the silicide layer 5 as a mask to form a resist pattern 10. At this time, during the oxygen plasma etching process, a part of the sillation layer 5 is oxidized by the oxygen plasma, and the silicon oxide layer 6 is formed on the uppermost part of the resist pattern 10.

이와같이, 다층의 레지스트 패턴(10)을 형성하게 되면, 단차를 구비한 기판(1) 상부에도 균일한 폭 또는 간격을 갖는 패턴을 형성할 수 있으며, 노광량의 조절로서 기존의 포토리소그라피 공정에 의하여 형성된 패턴의 폭 또는 간격 보다 더 미세한 패턴을 형성할 수 있다.As such, when the multilayered resist pattern 10 is formed, a pattern having a uniform width or spacing can be formed on the substrate 1 having a step, and is formed by a conventional photolithography process as a control of the exposure amount. It is possible to form a pattern finer than the width or spacing of the pattern.

그러나, 상기와 같은 종래의 디자이어 방식에 의하여 형성된 패턴은 다음과 같은 문제점을 지닌다.However, the pattern formed by the conventional design method as described above has the following problems.

상기와 같은 디자이어 방식에 의하여 형성된 패턴은, 포토레지스트층, 실릴레이션층, 실리콘 산화층의 3층으로 되어있어, 제거시 복잡한 공정을 거쳐야 한다. 즉, 상기의 3층 패턴을 제거하기 위하여는 실리콘 산화층을 제거하는 공정, 실릴레이션층을 제거하는 공정, 포토레지스트층을 제거하는 3번의 식각 공정을 진행하여야 한다.The pattern formed by the design method as described above is composed of three layers of a photoresist layer, a silylation layer, and a silicon oxide layer, and thus must be subjected to a complicated process during removal. That is, in order to remove the three-layer pattern, a process of removing the silicon oxide layer, a process of removing the silicide layer, and three etching processes of removing the photoresist layer should be performed.

이로 인하여, 원하지 않는 부분에 레지스트 패턴이 형성되는 경우, 용이하게 제거하기 어렵게 되는 문제점이 발생된다.For this reason, when a resist pattern is formed in an unwanted part, the problem which becomes difficult to remove easily arises.

또한, 이 레지스트 패턴의 잔재가 장비 내벽에 피착되기 쉬어, 장비내 오염을 유발한다.In addition, the residue of this resist pattern is likely to be deposited on the inner wall of the equipment, causing contamination in the equipment.

따라서, 본 발명의 목적은, 상기한 종래의 문제점을 해결하기 위하여 안출된 것으로, 디자이어 방식에 의하여 형성된 3층의 레지스트 패턴을 용이하게 제거할 수 있는 반도체 소자의 제조방법을 제공하는 것이다.Accordingly, it is an object of the present invention to provide a method for manufacturing a semiconductor device, which is devised to solve the above-mentioned conventional problems and which can easily remove a resist pattern of three layers formed by a design method.

도 1A 내지 도 1C는 종래의 디자이어 방식의 레지스트 패턴을 형성하는 방법을 설명하기 위한 도면.1A to 1C are views for explaining a method of forming a resist pattern of a conventional design.

도 2A 내지 도 2C는 본 발명에 따른 디자이어 레지스트 패턴을 제거하는 방법을 설명하기 위한 각 공정별 단면도.2A to 2C are cross-sectional views of respective processes for explaining a method of removing a design resist pattern according to the present invention.

*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

1 : 반도체 기판 2 : 포토레지스트층1 semiconductor substrate 2 photoresist layer

3 : 레티클 4 : 노광된 포토레지스트층3: reticle 4: exposed photoresist layer

5 : 실릴레이션층 6 : 실리콘 산화층5: silylation layer 6: silicon oxide layer

10 : 레지스트 패턴10: resist pattern

상기한 본 발명의 목적을 달성하기 위하여, 포토레지스트층과 실릴레이션층 및 실리콘산화층이 적층된 디자이어 레지스트 패턴을 제거하는 반도체 소자의 제조방법에 있어서, 상기 디자이어 레지스트 패턴은, 상기 실리콘 산화층을 산화층 식각 용액에 의하여 제거하는 단계; 및 상기 실릴레이션층과 포토레지스트층을 TMAH 용액에 의하여 동시에 제거하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object of the present invention, in the method of manufacturing a semiconductor device for removing a semiconductor resist pattern in which a photoresist layer, a silication layer, and a silicon oxide layer are laminated, the design of the resist pattern is a silicon oxide layer. Removing by the oxide layer etching solution; And simultaneously removing the sililation layer and the photoresist layer by TMAH solution.

본 발명에 의하면, 포토레지스트층, 실릴레이션층, 실리콘 산화층으로 이루어진 디자이어 레지스트 패턴의 제거 공정시, 1차적으로 실리콘 산화층을 제거하고, 2차적으로 TMAH 용액에 의하여 포토레지스트층, 실릴레이션층을 동시에 제거하므로써, 2번의 공정으로 디자이어 레지스트 패턴을 제거하게 된다.According to the present invention, during the process of removing the design resist pattern consisting of the photoresist layer, the silylation layer, and the silicon oxide layer, the silicon oxide layer is first removed, and the photoresist layer and the silicide layer are secondly formed by TMAH solution. By simultaneously removing, the design resist pattern is removed in two steps.

[실시예]EXAMPLE

이하 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

첨부한 도면 도 2A 내지 도 2C는 본 발명에 따른 디자이어 레지스트 패턴을 제거하는 방법을 설명하기 위한 각 공정별 단면도이다.2A to 2C are cross-sectional views of respective processes for explaining a method of removing a design resist pattern according to the present invention.

참고로, 본 실시예의 구성을 설명함에 있어, 명세서의 서두에서 설명된 종래의 기술과 동일 부분에 대하여 중복 설명을 배제하며, 종래와 동일한 부분에 대하여는 동일한 부호를 부여하도록 한다.For reference, in describing the configuration of the present embodiment, duplicate descriptions of the same parts as those of the prior art described at the beginning of the specification are omitted, and the same reference numerals are given to the same parts as the prior art.

도 2A를 참조하여, 반도체 기판의 적소에, 공지의 디자이어 패턴 형성 방식에 의하여, 3층 레지스트 패턴(10)이 형성된다. 앞서 설명된 바와 같이, 상기 레지스트 패턴(10)은 포토레지스트층(2)과, 실리콘이 확산된 노광층(5) 및 실리콘 산화층(6)으로 이루어진다.With reference to FIG. 2A, the three-layer resist pattern 10 is formed in the appropriate place of a semiconductor substrate by a well-known design pattern formation method. As described above, the resist pattern 10 includes a photoresist layer 2, an exposure layer 5 in which silicon is diffused, and a silicon oxide layer 6.

이때, 원하지 않는 부분에 레지스트 패턴(10)이 형성된 경우, 상기 레지스트 패턴(10)은 먼저, 도 2B에 도시된 것과 같이, 공지의 산화막 식각 용액 예를들어, BOE(buffer oxide etchant) 또는 HF 용액에 의하여 상부의 실리콘 산화층(6)을 제거한다.In this case, when the resist pattern 10 is formed in an undesired portion, the resist pattern 10 may first be a known oxide etching solution, for example, a buffer oxide etchant (BOE) or HF solution, as shown in FIG. 2B. By doing so, the upper silicon oxide layer 6 is removed.

그리고나서, 도 2C에 도시된 바와 같이, 잔존하는 실릴레이션층(5)과 포토레지스트층(2)은 TMAH(tetra methyl ammoium hydroxide)를 식각액에 의하여 용해되어, 제거된다. 그러면, 실릴레이션층(5)과 포토레지스트층(2)이 동시에 제거된다. 이때, 상기 TMAH 용액은 고분자 포토레지스트층과 폴리실리콘을 동시에 용해시킬 수 있다는 장점을 지닌다. 여기서, 상기 TMAH층의 활성화를 도모하기 위하여 고온(70 내지 90℃)의 TMAH 용액을 사용하거나, 또는 용액에 초음파를 진동을 가하거나, 또는 N2가스 버블을 사용할 수 있다.Then, as shown in FIG. 2C, the remaining silylation layer 5 and the photoresist layer 2 are dissolved by removing the tetramethyl ammoium hydroxide (TMAH) with an etchant. Then, the sillation layer 5 and the photoresist layer 2 are simultaneously removed. At this time, the TMAH solution has the advantage of dissolving the polymer photoresist layer and polysilicon at the same time. Here, in order to activate the TMAH layer, a high temperature (70 to 90 ° C.) TMAH solution may be used, or ultrasonic waves may be applied to the solution, or N 2 gas bubbles may be used.

따라서, 하나의 용액으로 두 층을 동시에 제거하므로 공정이 단순화된다.Thus, the process is simplified by removing both layers simultaneously with one solution.

이상에서 자세히 설명된 바와 같이, 본 발명에 의하면, 포토레지스트층, 실릴레이션층, 실리콘 산화층으로 이루어진 디자이어 레지스트 패턴의 제거 공정시, 1차적으로 실리콘 산화층을 제거하고, 2차적으로 TMAH 용액에 의하여 포토레지스트층, 실릴레이션층을 동시에 제거하므로써, 2번의 공정으로 디자이어 레지스트 패턴을 제거하게 된다.As described in detail above, according to the present invention, during the removal process of the design resist pattern consisting of a photoresist layer, a silylation layer, and a silicon oxide layer, the silicon oxide layer is first removed, and secondly, by a TMAH solution. By simultaneously removing the photoresist layer and the silicide layer, the design resist pattern is removed in two steps.

따라서, 공정이 단순화되고, 식각시 잔재가 식각 장비 내벽에 붙지않게 된다.Therefore, the process is simplified, and the residue does not adhere to the inner wall of the etching equipment during etching.

기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (3)

포토레지스트층과 실릴레이션층 및 실리콘산화층이 적층된 디자이어(DESIRE) 레지스트 패턴을 제거하는 반도체 소자의 제조방법에 있어서,In the method of manufacturing a semiconductor device for removing a DESIRE resist pattern laminated a photoresist layer, a silylation layer and a silicon oxide layer, 상기 디자이어 레지스트패턴을 이루는 상기 실리콘산화층을 산화층 식각용액에 의하여 제거하는 단계;Removing the silicon oxide layer constituting the design resist pattern by using an oxide layer etching solution; 상기 실릴레이션층과 포토레지스트층을 TMAH(tetra methyl ammoium hydroxide) 용액에 의하여 동시에 제거하되, 상기 TMAH 용액에 초음파 진동을 가하면서 식각하거나, 상기 TMAH 용액에 N2가스 버블을 일으키면서 식각하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Simultaneously removing the silylation layer and the photoresist layer by TMAH (tetra methyl ammoium hydroxide) solution, and etching while applying ultrasonic vibration to the TMAH solution, or etching while generating N 2 gas bubbles in the TMAH solution A method for manufacturing a semiconductor device comprising the. 제 1 항에 있어서, 상기 산화층 식각 용액은 BOE 또는 HF 용액인 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the oxide layer etching solution is a BOE or HF solution. 제 1 항에 있어서, 상기 TMAH 용액은 70 내지 90℃의 온도인 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the TMAH solution is a temperature of 70 to 90 ℃.
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