KR100419747B1 - Method for forming high voltage transistor to compensate for sidewall of gate oxide layer and avoid side attack in source/drain implantation process - Google Patents
Method for forming high voltage transistor to compensate for sidewall of gate oxide layer and avoid side attack in source/drain implantation process Download PDFInfo
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- KR100419747B1 KR100419747B1 KR1019960017360A KR19960017360A KR100419747B1 KR 100419747 B1 KR100419747 B1 KR 100419747B1 KR 1019960017360 A KR1019960017360 A KR 1019960017360A KR 19960017360 A KR19960017360 A KR 19960017360A KR 100419747 B1 KR100419747 B1 KR 100419747B1
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- Prior art keywords
- gate
- oxide film
- gate oxide
- oxide layer
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- 238000000034 method Methods 0.000 title claims abstract description 23
- 238000002513 implantation Methods 0.000 title abstract description 4
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000009792 diffusion process Methods 0.000 claims abstract description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract 3
- 238000005530 etching Methods 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 2
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 1
- 239000012535 impurity Substances 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000000059 patterning Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 125000001495 ethyl group Chemical group [H]C([H])([H])C([H])([H])* 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
본 발명은 고전압 트랜지스터 형성방법에 관한것으로, 특히 게이트 산화막 측벽을 보완하고, 소오스/드레인 임플란트시 측면 어택(attack)을 방지하도록 하는 고전압 트랜지스터 형성방법에 관한것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a high voltage transistor, and more particularly, to a method of forming a high voltage transistor that complements a gate oxide sidewall and prevents side attack during source / drain implants.
종래의 고전압용 게이트 산화막은 비교적 두껍게 예를들어 800Å의 두께로 형성한다음, 그상부에 게이트용 폴리실리콘층을 증착하고 게이트 마스크를 이용한패터닝 공정으로 폴리 게이트를 형성하고 n+불순물 또는 문턱전압 불순물, 소오스/드레인용 불순물을 임플란트 해야하기 때문에 게이트 산화막을 식각한다.A gate oxide film for the conventional high voltage is relatively thick, for example formed in a thickness of 800Å, and then depositing a gate polysilicon layer for thereon to form a poly gate by patterning process using the gate mask, and n + impurity or threshold voltage impurities The gate oxide film is etched because the source / drain impurities must be implanted.
이때 게이트 산화막의 측벽은 식각시 식각가스에 의해 의해 어택을 받아 손실이 발생되며, 후공정으로 소오스/드레인을 형성하기 위한 임플란트시 측면 확산에 의해 게이트 산화막의 격자 왜곡 현상이 발생된다. 그로인하여 게이트 산화막의 특성이 저하되는 문제점이 발생된다.At this time, the sidewalls of the gate oxide film are attacked by the etching gas during etching, and loss is generated. The lattice distortion of the gate oxide film is generated by the side diffusion during implantation to form the source / drain in a later process. This causes a problem that the characteristics of the gate oxide film are degraded.
따라서, 본 발명은 상기한 문제점을 해소하기 위하여 게이트 산화막을 식각한다음, 게이트와 게이트 산화막 측벽에 산화막을 증착한후 소오스/드레인 임플란트를 실시하는 고전압 트랜지스터 형성 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of forming a high voltage transistor in which a gate oxide film is etched to solve the above problem, and then a source / drain implant is deposited after the oxide film is deposited on the gate and gate oxide sidewalls.
상기한 목적을 달성하기 위한 본 발명은 반도체기판 상부에 게이트 산화막과 도전층을 적층하고, 게이트 마스크를 이용한 식각공정으로 상기 도전층을 식각하여 게이트를 형성하는 단계와,According to an aspect of the present invention, a gate oxide film and a conductive layer are stacked on a semiconductor substrate, and the gate is formed by etching the conductive layer by an etching process using a gate mask;
노출된 게이트 산화막을 식각하는 단계와,Etching the exposed gate oxide layer;
상기 게이트를 포함하는 전체 구조 상부에 산화막을 증착하고, 패터닝공정으로 상기 게이트 산화막와 게이트의 적층 구조의 측면과 상부에만 산화막을 남기고 나머지는 제거하는 단계와,Depositing an oxide film over the entire structure including the gate, leaving an oxide film on only the side and the top of the stacked structure of the gate oxide film and the gate by a patterning process, and removing the rest;
소오스/드레인용 불순물을 반도체기판으로 임플란트하여 소오스/드레인용 확산영역을 형성하는 단계를 포함한다.Implanting a source / drain impurity onto a semiconductor substrate to form a source / drain diffusion region.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제1도는 게이트 패터닝 공정과 게이트 산화막을 식각할때 게이트 산화막의 양측면에 손실과 손상이 발생됨을 도시한것으로, 반도체기판(1) 상부에 게이트 산화막(2)과 폴리실리콘층을 적층하고, 그 상부에 게이트 마스크용 감광막패턴(4)을 형성한후, 건식식각 공정으로 상기 폴리실리콘층을 식각하여 폴리게이트(3)을 형성한후, 노출된 게이트 산화막(2)을 식각을 한것이다.1 shows loss and damage on both sides of the gate oxide layer when the gate patterning process and the gate oxide layer are etched. The gate oxide layer 2 and the polysilicon layer are stacked on the semiconductor substrate 1 and thereon. After the photoresist pattern 4 for gate mask is formed, the polysilicon layer is formed by etching the polysilicon layer by a dry etching process, and then the exposed gate oxide layer 2 is etched.
상기 게이트 산화막(2)을 식각할때 폴리게이트(3)의 양단부 하부에서 게이트 산화막(2)의 측벽이 플라즈마 개스 및 케미칼에 노출되어 직접적인 어택을 받아 손실과 손상(10)이 발생되며, 그로인하여 고전압 절연체 구성이 어렵게 된다.When the gate oxide film 2 is etched, sidewalls of the gate oxide film 2 are exposed to the plasma gas and the chemical under the both ends of the polygate 3 and are directly attacked to cause loss and damage 10. High voltage insulator construction becomes difficult.
상기 게이트 산화막(2)은 600-800Å의 두께로 증착되고, 폴리실리콘층은 4000-5000Å의 두께로 증착된다.The gate oxide film 2 is deposited to a thickness of 600-800 kPa, and the polysilicon layer is deposited to a thickness of 4000-5000 kPa.
제2도는 상기 감광막패턴(4)을 제거한다음, 본 발명에 의해 제1도 공정후 전체적으로 고온 산화막(5)을 형성하고, 패터닝공정으로 게이트(3)와 게이트 산화막(2)의 표면에만 고온 산화막(5)을 남긴다음, 불순물을 반도체기판(1)으로 임플란트하여 소오스/드레인용 확산영역(6)을 형성한 것을 도시한 단면도이다.2 shows that the photoresist pattern 4 is removed, and then the high temperature oxide film 5 is formed as a whole after the process of FIG. 1 according to the present invention. After leaving (5), the cross-sectional view shows that the source / drain diffusion region 6 is formed by implanting impurities into the semiconductor substrate 1.
참고로, 상기 고온 산화막(5)은 830-900℃의 온도에서 SiCl2H2+ 2H2O2를 사용하여 400-600Å의 두께로 증착한다. 그리고, 고온 산화막의 막질을 향상시키기 위하여 N2분위기와 900℃의 온도에서 20분 정도 열처리한다.For reference, the high temperature oxide film 5 is deposited to a thickness of 400-600 kW using SiCl 2 H 2 + 2H 2 O 2 at a temperature of 830-900 ℃. In order to improve the film quality of the high temperature oxide film, heat treatment is performed for about 20 minutes in an N 2 atmosphere and a temperature of 900 ° C.
상기의 고온 산화막(5)은 CVD 산화막 중에서 전기적 절연특성이 우수하며 또한, 디클로로 싸일렌(SiCl2H2) 소오스를 사용함으로 Cl에 의한 산화막 특성 향상이나타나서 양호한 절연 특성을 가지며, 브렉다운 특성이 우수하다.The high temperature oxide film 5 has excellent electrical insulating properties in the CVD oxide film, and also has an excellent insulating property due to the improvement of the oxide film property by Cl by using a dichlorosilane (SiCl 2 H 2 ) source. great.
본 발명의 다른 실시예는 상기 고온 산화막(5) 대신에 TEOS(tetra ethyl ortho sillicate) 막을 300-500Å의 두께로 증착하는 것이다.Another embodiment of the present invention is to deposit a TEOS (tetra ethyl ortho sillicate) film in the thickness of 300-500Å instead of the high temperature oxide film (5).
상기와 같이 산화막을 게이트 산화막의 측벽에 형성한다음, 소오스/드레인용 고농도 불순물을 임플란트하는 경우에 측면 방향으로 As 또는 BF2가 확산되는 것을 방지할수가 있다.As described above, when the oxide film is formed on the sidewall of the gate oxide film, As or BF 2 can be prevented from spreading laterally in the case of implanting a high concentration impurity for source / drain.
또한, 손상된 게이트 산화막의 리커버리(recovery) 효과와 게이트 산화막과 고온 산화막의 계면 특성의 향상을 기대할 수 가 있다.In addition, the recovery effect of the damaged gate oxide film and the improvement of the interfacial properties of the gate oxide film and the high temperature oxide film can be expected.
제1도는 게이트를 형성하고, 하부의 게이트 산화막을 식각할때 게이트 산화막의 측벽에 손실과 손상이 발생되는 것을 도시한 단면도.1 is a cross-sectional view showing that loss and damage occurs in the sidewall of the gate oxide when the gate is formed and the lower gate oxide is etched.
제2도는 본 발명에의해 게이트 산화막과 게이트가 적층된 구조의 측벽에 산화막을 형성한 단면도.2 is a cross-sectional view of an oxide film formed on a sidewall of a structure in which a gate oxide film and a gate are stacked according to the present invention.
※ 도면의 주요 부분에 대한 부호의 설명※ Explanation of codes for main parts of drawing
1 : 반도체 기판 2 : 게이트 산화막1 semiconductor substrate 2 gate oxide film
3 : 폴리게이트 4 : 감광막패턴3: polygate 4: photoresist pattern
5 : 산화막 6 : 확산영역5: oxide film 6: diffusion region
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960017360A KR100419747B1 (en) | 1996-05-22 | 1996-05-22 | Method for forming high voltage transistor to compensate for sidewall of gate oxide layer and avoid side attack in source/drain implantation process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960017360A KR100419747B1 (en) | 1996-05-22 | 1996-05-22 | Method for forming high voltage transistor to compensate for sidewall of gate oxide layer and avoid side attack in source/drain implantation process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970077728A KR970077728A (en) | 1997-12-12 |
| KR100419747B1 true KR100419747B1 (en) | 2004-07-07 |
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| KR1019960017360A KR100419747B1 (en) | 1996-05-22 | 1996-05-22 | Method for forming high voltage transistor to compensate for sidewall of gate oxide layer and avoid side attack in source/drain implantation process |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01278048A (en) * | 1988-04-28 | 1989-11-08 | Nec Corp | Manufacture of semiconductor device |
| KR910017671A (en) * | 1990-03-05 | 1991-11-05 | 문정환 | Sideol spacer manufacturing method |
| KR920015424A (en) * | 1991-01-10 | 1992-08-26 | 문정환 | Semiconductor manufacturing method |
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1996
- 1996-05-22 KR KR1019960017360A patent/KR100419747B1/en not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01278048A (en) * | 1988-04-28 | 1989-11-08 | Nec Corp | Manufacture of semiconductor device |
| KR910017671A (en) * | 1990-03-05 | 1991-11-05 | 문정환 | Sideol spacer manufacturing method |
| KR920015424A (en) * | 1991-01-10 | 1992-08-26 | 문정환 | Semiconductor manufacturing method |
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| Publication number | Publication date |
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| KR970077728A (en) | 1997-12-12 |
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