KR100400280B1 - Method for forming metal interconnection of semiconductor device - Google Patents
Method for forming metal interconnection of semiconductor device Download PDFInfo
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- KR100400280B1 KR100400280B1 KR1019960024294A KR19960024294A KR100400280B1 KR 100400280 B1 KR100400280 B1 KR 100400280B1 KR 1019960024294 A KR1019960024294 A KR 1019960024294A KR 19960024294 A KR19960024294 A KR 19960024294A KR 100400280 B1 KR100400280 B1 KR 100400280B1
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- titanium
- nitrogen
- rich
- nitride film
- titanium nitride
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 27
- 239000002184 metal Substances 0.000 title claims abstract description 27
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 69
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 32
- 239000010936 titanium Substances 0.000 claims abstract description 30
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 30
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 29
- 239000010410 layer Substances 0.000 claims abstract description 20
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000011229 interlayer Substances 0.000 claims abstract description 9
- 230000004888 barrier function Effects 0.000 claims abstract description 7
- 238000009792 diffusion process Methods 0.000 claims abstract description 6
- 229910001873 dinitrogen Inorganic materials 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 5
- 230000008569 process Effects 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 5
- 238000009751 slip forming Methods 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract 4
- 230000003667 anti-reflective effect Effects 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 7
- 239000011800 void material Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 150000003608 titanium Chemical class 0.000 description 2
- 238000005054 agglomeration Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000012421 spiking Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 특히 리소그래피(lithography) 공정시 발생될 수 있는 금속배선의 손상을 방지하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in a semiconductor device, and more particularly, to a technique for preventing damage to metal wirings that may occur during a lithography process.
일반적으로, 소자간이나 소자와 외부회로 사이를 전기적으로 접속시키기 위한 반도체소자의 배선은, 배선을 위한 소정의 콘택홀 및 비아홀을 배선재료로 매립하여 배선층을 형성하고 후속공정을 거쳐 이루어지며, 낮은 저항을 필요로 하는 곳에는 금속배선을 사용한다.In general, the wiring of a semiconductor device for electrically connecting between devices or between an element and an external circuit is formed by filling a predetermined contact hole and via hole for wiring with a wiring material and forming a wiring layer through a subsequent process. Metal wiring is used where resistance is required.
상기 금속배선은 알루미늄(Al)에 소량의 실리콘이나 구리가 포함되거나 실리콘과 구리가 모두 포함되어 비저항이 낮으면서 가공성이 우수한 알루미늄합금을 배선재료로 하여 물리기상증착 ( Physical Vapor Deposition, 이하에서 PVD 라 함 )방법의 스퍼터링으로 상기의 콘택홀 및 비아홀을 매립하는 방법이 가장 널리 이용되고 있다.The metal wiring includes a small amount of silicon or copper in aluminum (Al), or both silicon and copper, and has a low resistivity and excellent workability. The method of filling the contact hole and the via hole by sputtering of the method is most widely used.
제1도는 종래기술에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도이다.1 is a cross-sectional view showing a metal wiring formation method of a semiconductor device according to the prior art.
먼저, 반도체기판(31) 상부에 층간절연막(33)을 형성한다. 이때, 상기 층간절연막(33)은 상기 반도체기판(31) 상부에 소자분리절연막(도시안됨), 워드라인(도시안됨), 비트라인(도시안됨) 또는 캐패시터(도시안됨) 등을 형성하고 비.피.에스.지. ( Boro Phospho Silicate Glass, 이하에서 BPSG 라 함 ) 등과 같이 유동성이 우수한 절연물로 평탄화시킨 것이다.First, an interlayer insulating film 33 is formed on the semiconductor substrate 31. In this case, the interlayer insulating layer 33 forms an isolation layer (not shown), a word line (not shown), a bit line (not shown), or a capacitor (not shown) on the semiconductor substrate 31. P.S.G. It is flattened with an insulating material having excellent fluidity such as Boro Phospho Silicate Glass (hereinafter referred to as BPSG).
그 다음에, 상기 반도체기판(31)의 예정된 부분을 노출시키는 콘택홀(35)을 형성한다. 이때, 상기 콘택홀(35)은 콘택마스크(도시안됨)를 이용한 식각공정으로 형성한다.Next, a contact hole 35 exposing a predetermined portion of the semiconductor substrate 31 is formed. In this case, the contact hole 35 is formed by an etching process using a contact mask (not shown).
그리고, 전체표면상부에 티타늄/티타늄질화막으로 형성된 장벽금속층(37)을 소정두께 형성한다.Then, a barrier metal layer 37 formed of a titanium / titanium nitride film is formed on the entire surface, and has a predetermined thickness.
그 다음에, 전체표면상부에 알루미늄합금(39)을 증착한다.Then, an aluminum alloy 39 is deposited on the entire surface.
그리고, 전체표면상부에 반사방지막(41)인 티타늄질화막을 소정두께 형성한다.Then, a titanium nitride film, which is an antireflection film 41, is formed on the entire surface.
이때, 상기 티타늄질화막으로 형성된 반사방지막(41) 형성공정이나 알루미늄 합금(39) 형성공정시 온도차에 의한 응력의 차이로 인하여 상기 반사방지막(41)에 크랙(43)이 발생된다.At this time, a crack 43 is generated in the anti-reflection film 41 due to the difference in stress caused by the temperature difference during the formation of the anti-reflection film 41 formed of the titanium nitride film or the process of forming the aluminum alloy 39.
그리고, 상기 알루미늄합금(39)은 온도변화에 의하여 수축 또는 팽창하여 표면을 변형시킨다.In addition, the aluminum alloy 39 is deformed or expanded by temperature change to deform the surface.
이때, 상기 알루미늄합금(39)의 표면 변형은 주로 실리콘 노듈 ( silicon nodule ) 에 의하여 발생한다.At this time, the surface deformation of the aluminum alloy 39 is mainly caused by a silicon nodule.
참고로, 상기 실리콘 노듈은 접합-스파이킹 ( junction spiking ) 현상을 방지하기 위하여 알루미늄합금에 과고용시킨 실리콘 원자가 후속 열공정시 석출되어 상기 알루미늄합금으로 형성되는 배선의 표면이나 그레인 바운더리 ( grain boundary ) 에 위치한 것으로, 상기 실리콘 노듈은 덩어리 형태로 다수의 실리콘 원자가 합쳐서 형성되어 상기 실리콘 노듈이 없는 부분은 래티스-보이드 ( lattice void ) 가 형성된다.For reference, the silicon nodules may be formed on the surface or grain boundary of a wiring formed of the aluminum alloy by depositing silicon atoms over-solubilized in the aluminum alloy to prevent junction spiking. In this case, the silicon nodules are formed by agglomeration of a plurality of silicon atoms in a lump form so that a lattice void is formed in a portion without the silicon nodules.
그리고, 상기 실리콘 노듈은 상기 알루미늄합금으로 형성되는 금속배선의 일렉트로-마이그레이션 ( electro-migration, 이하에서 EM 이라 함 ) 이나 스트레스-마이그레이션 ( stress-migration, 이하에서 SM 이라 함 ) 특성을 악화시킬 수 있다.In addition, the silicon nodules may deteriorate electro-migration (hereinafter referred to as EM) or stress-migration (hereinafter referred to as SM) characteristics of the metal wire formed of the aluminum alloy. .
그 다음에, 후속공정인 감광막패턴(도시안됨) 형성공정시 사용되는 현상액이 상기 크랙(43)을 통하여 침투함으로써 금속배선을 손상시킬 수 있다. (제1도)Then, the developer used in the subsequent process of forming the photoresist pattern (not shown) may penetrate through the crack 43, thereby damaging the metal wiring. (Figure 1)
상기한 바와 같이 종래기술에 따른 반도체소자의 금속배선 형성방법은, 금속 배선 물질의 공정조건에 따라 발생하는 반사방지막의 결함으로 인하여, 현상액을 이용한 패터닝 ( patterning ) 공정시 금속배선이 손상되어 반도체소자의 특성 및 신뢰성을 저하시키고 그에 따른 반도체소자의 고집적화를 어렵게 하는 문제점이 있다.As described above, in the method of forming a metal wiring of a semiconductor device according to the prior art, due to a defect of an anti-reflection film generated according to a process condition of a metal wiring material, the metal wiring is damaged during a patterning process using a developer and thus, There is a problem in that the characteristics and reliability of the deterioration and thereby the high integration of the semiconductor device is difficult.
따라서, 본 발명은 상기한 문제점을 해결하기위하여, 반사방지막을 티타늄-리치(rich)-티타늄질화막과 질소-리치(rich)-티타늄질화막의 적층구조로 형성함으로써 반사방지막에 발생할 수 있는 결함을 억제할 수 있어 후속공정으로 금속배선의 손상을 방지함으로써 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 반도체소자의 금속배선 형성방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above problems, the present invention suppresses defects that may occur in the antireflection film by forming the antireflection film in a laminated structure of a titanium-rich-titanium nitride film and a nitrogen-rich-titanium nitride film. The purpose of the present invention is to provide a method for forming a metal wiring of a semiconductor device which can improve the characteristics and reliability of the semiconductor device by preventing damage to the metal wiring in a subsequent process.
이상의 목적을 달성하기위해 본 발명에 따른 반도체소자의 금속배선 형성방법의 특징은,In order to achieve the above object, a feature of the metal wiring forming method of a semiconductor device according to the present invention,
반도체기판 상부에 층간절연막을 형성하고, 콘택마스크를 이용한 식각공정으로 상기 반도체기판의 예정된 부분을 노출시키는 콘택홀을 형성하는 공정과,Forming an interlayer insulating layer on the semiconductor substrate and forming a contact hole exposing a predetermined portion of the semiconductor substrate by an etching process using a contact mask;
전체표면상부에 확산방지층과 금속배선 물질인 알루미늄합금을 형성하는 공정과,Forming an aluminum alloy which is a diffusion barrier layer and a metal wiring material on the entire surface;
전체표면상부에 질소가스의 유량을 조절하며 티타늄-리치-티타늄질화막과 질소-리치-티타늄질화막을 연속적으로 증착하여 티타늄-리치-티타늄질화막과 질소-리치-티타늄질화막의 적층구조로 반사방지막을 형성하되, 상기 티타늄-리치-티타늄 질화막은 티타늄이 질소보다 0.1 ∼ 10 % 많은 비율로 함유하고 상기 질소-리치-티타늄질화막은 질소가 티타늄보다 0.1 ∼ 10 % 많은 비율로 함유하는 공정을 포함하는 것과,Nitrogen-rich-titanium nitride film and nitrogen-rich-titanium nitride film are continuously deposited on the entire surface by controlling the flow rate of nitrogen gas to form an anti-reflection film with a laminated structure of titanium-rich-titanium nitride film and nitrogen-rich-titanium nitride film. However, the titanium-rich-titanium nitride film contains titanium in a ratio of 0.1 to 10% more than nitrogen and the nitrogen-rich-titanium nitride film comprises a process containing nitrogen in a ratio of 0.1 to 10% more than titanium,
상기 티타늄-리치-티타늄질화막과 질소-리치-티타늄질화막은 하나의 챔버에서 연속적으로 형성하는 것과,The titanium-rich-titanium nitride film and the nitrogen-rich-titanium nitride film are continuously formed in one chamber,
상기 티타늄-리치-티타늄질화막과 질소-리치-티타늄질화막은 두 개의 챔버에서 연속적으로 형성하는 것을 특징으로 한다.The titanium-rich-titanium nitride film and the nitrogen-rich-titanium nitride film are formed in two chambers in succession.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2A도 및 제2B도는 본 발명의 실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도이다.2A and 2B are cross-sectional views illustrating a method for forming metal wirings in a semiconductor device according to an embodiment of the present invention.
먼저, 반도체기판(11) 상부에 층간절연막(13)을 형성한다. 이때, 상기 층간절연막(13)은 상기 반도체기판(11) 상부에 소자분리절연막(도시안됨), 워드라인(도시안됨), 비트라인(도시안됨) 또는 캐패시터(도시안됨) 등을 형성하고 BPSG 등과 같이 유동성이 우수한 절연물로 평탄화시킨 것이다.First, an interlayer insulating film 13 is formed on the semiconductor substrate 11. In this case, the interlayer insulating layer 13 may form an isolation layer (not shown), a word line (not shown), a bit line (not shown), a capacitor (not shown), and the like on the semiconductor substrate 11. As such, the film is flattened with an insulator having excellent fluidity.
그 다음에, 상기 반도체기판(11)의 예정된 부분을 노출시키는 콘택홀(15)을 형성한다. 이때, 상기 콘택홀(15)은 콘택마스크(도시안됨)를 이용한 식각공정으로 형성한다.Next, a contact hole 15 exposing a predetermined portion of the semiconductor substrate 11 is formed. In this case, the contact hole 15 is formed by an etching process using a contact mask (not shown).
그리고, 전체표면상부에 티타늄막/티타늄질화막의 적층구조로 형성된 확산방지층(17)을 소정두께 형성한다. 이때, 상기 확산방지층(17)은 100 ∼ 2000 Å 정도의 두께로 형성한다.Then, a diffusion barrier layer 17 formed of a laminated structure of a titanium film / titanium nitride film is formed on the entire surface. At this time, the diffusion barrier layer 17 is formed to a thickness of about 100 ~ 2000 kPa.
그 다음에, 전체표면상부에 금속배선 물질인 알루미늄합금(19)을 약 500 ℃ 정도의 온도에서 형성한다. (제2A도)Next, an aluminum alloy 19, which is a metal wiring material, is formed on the entire surface at a temperature of about 500 占 폚. (Figure 2A)
그리고, 전체표면상부에 티타늄-리치-티타늄질화막(21)과 질소-리치-티타늄질화막(23)을 각각 소정두께 형성하되, 약 300 ℃ 정도의 온도에서 형성한다.Then, a titanium-rich-titanium nitride film 21 and a nitrogen-rich-titanium nitride film 23 are formed on the entire surface, respectively, at a temperature of about 300 ° C.
이때, 상기 티타늄-리치-티타늄질화막(21)과 질소-리치-티타늄질화막(23)은 티타늄질화막 증착공정시 질소가스의 유량을 변화시켜 형성하되, 상기 티타늄-리치-티타늄질화막(21)은 질소가스의 유량을 적게 하고 상기 질소-리치-티타늄질화막(23)은 질소가스와 유량을 많게 하여 형성한다.In this case, the titanium-rich-titanium nitride film 21 and the nitrogen-rich-titanium nitride film 23 are formed by changing the flow rate of nitrogen gas during the titanium nitride film deposition process, and the titanium-rich-titanium nitride film 21 is nitrogen The flow rate of gas is reduced and the nitrogen-rich-titanium nitride film 23 is formed by increasing the flow rate with nitrogen gas.
일반적으로, 티타늄질화막은 티타늄 : 질소 비를 1 : 1 로 하여 형성한 것이 가장 안정하다. 그리고, 상기 티타늄-리치-티타늄질화막(21)은 티타늄이 질소보다 0.1 ∼ 10 % 정도 많은 비율로 형성한다. 그리고, 상기 질소-리치-티타늄질화막(23)은 질소가 티타늄보다 0.1 ∼ 10 % 정도 많은 비율로 형성한다.In general, the titanium nitride film is most stable formed with a titanium: nitrogen ratio of 1: 1. In addition, the titanium-rich-titanium nitride film 21 is formed at a ratio of about 0.1 to about 10% greater than that of nitrogen. In addition, the nitrogen-rich-titanium nitride film 23 is formed in a ratio of about 0.1 to 10% more nitrogen than titanium.
그리고, 상기 티타늄-리치-티타늄질화막(21)과 질소-리치-티타늄질화막(23)은 한 개 또는 두개의 챔버 ( chamber ) 를 이용하여 연속적으로 형성한다.The titanium-rich-titanium nitride film 21 and the nitrogen-rich-titanium nitride film 23 are continuously formed using one or two chambers.
여기서, 상기 티타늄-리치-티타늄질화막(21)은 종래의 반사방지막인 티타늄질화막보다 응력이 작아 상기 알루미늄합금(19)과의 SM 특성을 향상시킨다.Here, the titanium-rich-titanium nitride film 21 has a smaller stress than the titanium nitride film, which is a conventional anti-reflection film, to improve the SM characteristics with the aluminum alloy 19.
그리고, 상기 티타늄-리치-티타늄질화막(21)의 티타늄 원자는 상기 알루미늄 합금(19)으로 확산되어 실리콘 노듈에 의한 래티스-보이드를 매립함으로써 EM 특성 저하에 따른 상기 알루미늄합금(19)의 표면 변형을 억제한다.In addition, titanium atoms of the titanium-rich-titanium nitride layer 21 diffuse into the aluminum alloy 19 to fill a lattice-void by silicon nodules, thereby modifying the surface of the aluminum alloy 19 due to the deterioration of EM characteristics. Suppress
그로 인하여, 상기 반사방지막(21,23)의 크랙을 방지하고, 후속공정인 패터닝 공정시 현상액에 의한 금속배선의 손상을 방지한다. (제2B도)Therefore, cracks of the anti-reflection films 21 and 23 are prevented, and damage to the metal wiring by the developer during the patterning process, which is a subsequent process, is prevented. (Figure 2B)
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 금속배선 형성방법은, 알루미늄합금 상부에 티타늄-리치-티타늄질화막/질소-리치-티타늄질화막 적층구조의 반사방지막을 형성하여 실리콘 노듈에 의한 래티스-보이드를 보상함으로써 상기 알루미늄합금의 표면변형을 억제하여 상기 반사방지막의 크랙의 발생을 억제하고, 후속공정인 현상공정시 현상액에 의한 금속배선의 손상을 방지할 수 있어 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 잇점이 있다.As described above, in the method for forming metal wirings of the semiconductor device according to the present invention, a lattice-void formed by silicon nodules is formed by forming an anti-reflection film having a titanium-rich-titanium nitride film / nitrogen-rich-titanium nitride film stacked structure on an aluminum alloy. By suppressing the surface deformation of the aluminum alloy to suppress the occurrence of cracks in the anti-reflection film, and to prevent damage to the metal wiring by the developer during the subsequent development process to improve the characteristics and reliability of the semiconductor device Accordingly, there is an advantage that enables high integration of the semiconductor device.
제 1 도는 종래기술에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도.1 is a cross-sectional view showing a metal wiring forming method of a semiconductor device according to the prior art.
제 2A 도 및 제 2B 도는 본 발명의 실시예에 반도체소자의 금속배선 형성방법을 도시한 단면도.2A and 2B are cross-sectional views showing a method for forming metal wirings of a semiconductor device in an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 명칭 ><Name of code for main part of drawing>
11,31 : 반도체기판 13,33 : 층간절연막11,31: semiconductor substrate 13,33: interlayer insulating film
15,35 : 콘택홀 17,37 : 확산방지층15,35 contact hole 17,37 diffusion barrier layer
19,39 : 알루미늄합금19,39: aluminum alloy
21 : 티타늄-리치-티타늄질화막21: titanium-rich-titanium nitride film
23 : 질소-리치-티타늄질화막23: nitrogen-rich-titanium nitride film
41 : 반사방지막 43 : 크랙41: antireflection film 43: crack
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100510062B1 (en) * | 1998-08-18 | 2005-11-03 | 주식회사 하이닉스반도체 | Method for forming titanium nitride layer |
| US20200235196A1 (en) * | 2019-01-17 | 2020-07-23 | Samsung Display Co., Ltd. | Display device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100510062B1 (en) * | 1998-08-18 | 2005-11-03 | 주식회사 하이닉스반도체 | Method for forming titanium nitride layer |
| US20200235196A1 (en) * | 2019-01-17 | 2020-07-23 | Samsung Display Co., Ltd. | Display device and manufacturing method thereof |
| US11793044B2 (en) * | 2019-01-17 | 2023-10-17 | Samsung Display Co., Ltd. | Display device and manufacturing method thereof |
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