KR100390451B1 - prevention structure for crack of substrate for manucture of semiconductor package in moulder - Google Patents
prevention structure for crack of substrate for manucture of semiconductor package in moulder Download PDFInfo
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- KR100390451B1 KR100390451B1 KR10-1999-0054303A KR19990054303A KR100390451B1 KR 100390451 B1 KR100390451 B1 KR 100390451B1 KR 19990054303 A KR19990054303 A KR 19990054303A KR 100390451 B1 KR100390451 B1 KR 100390451B1
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- circuit board
- floating insert
- mold
- sensor block
- coating film
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
- B29C45/00—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
- B29C45/14—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles
- B29C45/14639—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components
- B29C45/14655—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components connected to or mounted on a carrier, e.g. lead frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Mechanical Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
본 발명은 BGA(Ball Grid Array) 반도체 패키지 제조 공정용 몰딩 장비에 관한 것으로써, 몰딩 공정을 수행하기 위해 상부금형이 하부금형에 밀착할 때 반도체칩이 실장된 회로기판이 상부플로팅인서트에 직접적으로 접촉하지 않도록 함과 함께 회로기판의 전체적인 두께 편차에도 관계없이 이에 적절히 대응된 상태로 상호간의 완전한 밀착이 이루어지도록 함으로써 상기 회로기판에 형성된 각 회로패턴이 손상됨을 미연에 방지할 수 있도록 한 것이다.The present invention relates to a molding equipment for a ball grid array (BGA) semiconductor package manufacturing process, wherein a circuit board on which a semiconductor chip is mounted is directly connected to the upper floating insert when the upper mold is in close contact with the lower mold to perform the molding process. In order to prevent contact between the circuit board and the circuit pattern formed on the circuit board to be in close contact with each other in accordance with the appropriate state irrespective of the overall thickness variation of the circuit board to prevent the damage in advance.
이를 위해, 본 발명은 그 중앙에 설치된 하부센서블록(21) 및 상기 하부센서블록의 양측에 패키지의 성형을 위해 각종 회로기판(1)이 안착되도록 캐비티(22a)가 다수개 형성된 하부플로팅인서트(22)를 구비한 하부금형(20)과, 상기 하부금형에 대응된 상태로써 그 중앙에 설치된 상부센서블록(11) 및 상기 상부센서블록의 양측에 설치되는 상부플로팅인서트(12)를 구비한 상부금형(10)으로 이루어진 몰딩 장비에 있어서, 상기 상부플로팅인서트의 각 부위중 하부플로팅인서트(22)에 안착된 회로기판(1)과의 접촉이 이루어지는 부위에 탄성을 지니는 재질로 이루어진 코팅막(30)을 형성하여 상부플로팅인서트(12)의 표면과 회로기판의(1) 표면이 상기 코팅막에 의해 서로 직접적인 접촉이 방지될 수 있도록 함과 함께 회로기판(1)에 가해지는 클램프력을 완충할 수 있도록 한 것을 특징으로 하는 반도체 패키지 제조용 몰딩 장비의 회로기판 크랙 방지구조가 제공된다.To this end, the present invention provides a lower floating insert having a plurality of cavities 22a formed therein so that various circuit boards 1 are seated for forming a package on both sides of the lower sensor block 21 and the lower sensor block installed at the center thereof. A lower mold 20 having a lower mold 20, an upper sensor block 11 installed at the center thereof, and an upper floating insert 12 mounted at both sides of the upper sensor block. In the molding apparatus consisting of a mold (10), the coating film 30 made of a material having elasticity in the contact with the circuit board (1) seated on the lower floating insert 22 of the respective parts of the upper floating insert The surface of the upper floating insert 12 and the surface of the circuit board 1 may be prevented from directly contacting each other by the coating film, and the clamping force applied to the circuit board 1 may be buffered. Provided is a circuit board crack preventing structure of a molding equipment for manufacturing a semiconductor package.
Description
본 발명은 반도체 패키지 제조 공정용 몰딩 장비에 관한 것으로서, 더욱 상세하게는 하부 금형 내에 몰딩을 위한 반도체 회로기판이 안착된 상태에서 상부 금형이 점차적으로 하강하여 상, 하부 금형이 서로 밀착될 때 상기 반도체 회로기판의 크랙을 방지할 수 있도록 한 것이다.The present invention relates to a molding apparatus for a semiconductor package manufacturing process, and more particularly, when the upper mold is gradually lowered while the semiconductor circuit board for molding is seated in the lower mold, and the upper and lower molds are in close contact with each other. It is to prevent the crack of the circuit board.
일반적으로 반도체 패키지라 함은 반도체칩을 외부 환경으로부터 안전하게 보호를 행하기 위해 패키징(packaging)하여 필요한 장소에 실장가능한 형태로 구성한 것으로써, 매우 다양한 종류의 반도체 패키지가 개발되었고, 또한 현재에도 계속하여 개발중에 있다.In general, a semiconductor package is a package in which a semiconductor chip is packaged in order to safely protect it from an external environment and is mounted in a required place. A wide variety of semiconductor packages have been developed and are still It is under development.
특히, 현재에는 반도체 패키지의 고집적화, 다기능화 및 소형화하는데 주력함으로써 더욱 다양한 범위에의 적용이 가능하도록 하고 있다.In particular, the present invention focuses on high integration, multifunction, and miniaturization of semiconductor packages, thereby enabling application to a wider range.
상기와 같은 반도체 패키지중 BGA(Ball Grid Array)형 반도체 패키지로써 하나의 패키지를 통해 무수히 많은 단자를 실장할 수 있도록 구현된 형태이다.It is a BGA (Ball Grid Array) type semiconductor package of the above-described semiconductor package is implemented to mount a myriad of terminals through one package.
즉, 솔더볼(solder ball)을 이용하여 무수히 많은 단자의 실장을 구현함으로써 종래 리드프레임을 이용한 반도체 패키지의 단자에 대한 한계를 극복할 수 있게 된 것이다.That is, by implementing a myriad of terminal mounting using a solder ball (solder ball) it is possible to overcome the limitations on the terminal of the semiconductor package using a conventional lead frame.
상기와 같은 BGA형 반도체 패키지의 구성을 도시한 도 1을 참조하여 보다 구체적으로 설명하면 후술하는 바와 같다.The configuration of the BGA type semiconductor package as described above will be described in more detail with reference to FIG. 1.
일반적으로 BGA형 반도체 패키지는 솔더 마스크(solder mask)에 의해 다수의 회로패턴(도시는 생략함)이 인쇄된 회로기판(Printed Circuit Board,Substrate)(1)과, 상기 회로기판의 상면에 부착되어 골드와이어(gold wire)(2)로써 회로기판(1)의 각 회로패턴에 전기적으로 연결된 반도체칩(3)과, 상기 반도체칩 및 골드와이어를 외부 환경으로부터 보호하기 위해 회로기판(1) 상부의 일정영역에 콤파운드재(EMC:Epoxy Molding Compound)를 이용하여 봉지한 패키지 몸체(4)와, 상기 회로기판의 배면에 부착되어 외부 전극 리드로써 사용되는 다수의 솔더볼(5)로 크게 구성된다.In general, a BGA type semiconductor package is attached to a printed circuit board (Substrate) (1) printed a plurality of circuit patterns (not shown) by a solder mask, and the upper surface of the circuit board A semiconductor chip 3 electrically connected to each circuit pattern of the circuit board 1 by a gold wire 2 and an upper portion of the circuit board 1 to protect the semiconductor chip and the gold wire from an external environment. It consists of a package body 4 encapsulated using a compound material (EMC: Epoxy Molding Compound) in a predetermined region and a plurality of solder balls 5 attached to the rear surface of the circuit board and used as external electrode leads.
이 때, 상기 각 회로패턴은 각각의 솔더볼(5)과 전기적으로 통전되어 있음에 따라 반도체칩(3)의 신호가 외부 단자로 전달될 수 있게 된다.At this time, the circuit patterns are electrically connected to the respective solder balls 5, so that the signal of the semiconductor chip 3 can be transmitted to the external terminal.
한편, 도시한 도 2는 전술한 바와 같이 구성되는 BGA형 반도체 패키지의 제조 공정중 몰딩 공정을 수행하는데 사용되는 몰딩 장비를 나타낸 것으로써 상부에 위치되는 상부금형(10)과, 하부에 위치되는 하부금형(20)으로 크게 구성되어 있다.Meanwhile, FIG. 2 illustrates molding equipment used to perform a molding process in a manufacturing process of a BGA type semiconductor package configured as described above, and includes an upper mold 10 positioned at an upper portion and a lower portion positioned at a lower portion thereof. It is comprised largely by the metal mold | die 20.
이 때, 상기 상부금형에는 그 중앙에 설치된 상부센서블록(Top sensor block)(11)와, 상기 상부센서블록의 양측에 설치되는 상부플로팅인서트(Top floating insert)(12)를 구비하고 있고, 이에 대응하는 하부금형(20)에는 그 중앙에 위치하는 하부센서블록(Bottom sensor block)(21)과 상기 하부센서블록의 양측에 패키지의 성형을 위한 캐비티(22a)가 다수개 형성된 하부플로팅인서트(Bottom floating insert)(22)를 구비하고 있다.At this time, the upper mold is provided with a top sensor block 11 installed at its center and a top floating insert 12 installed at both sides of the upper sensor block. The bottom mold insert 20 has a bottom sensor block 21 positioned at its center and a bottom floating insert in which a plurality of cavities 22a are formed on both sides of the bottom sensor block. floating insert 22).
또한, 상기 상부금형내 상부플로팅인서트(12)의 상부측에는 심 플레이트(shim plate)(13)가 스프링(14)등에 의해 탄력 설치되어 있으며, 상기 상부플로팅인서트와 심 플레이트는 볼트(15)로써 상부금형(10)에 고정되는 구조를 취하고 있다.In addition, a shim plate 13 is elastically installed on the upper side of the upper floating insert 12 in the upper mold by a spring 14, and the upper floating insert and the shim plate are upper by bolts 15. The structure fixed to the metal mold | die 10 is taken.
따라서, 몰드 기기를 구성하는 하부금형(20)의 하부플로팅인서트(22)에 반도체칩이 실장된 회로기판(1)을 안착시킨 후 하부금형(20)을 상부금형(10) 측으로 상승시키면 상부플로팅인서트(12)와 하부플로팅인서트(22)가 서로 맞닿음에 따라 회로기판(1)을 적정하게 클램프(clamp)시키게 된다.Therefore, when the circuit board 1 on which the semiconductor chip is mounted is seated on the lower floating insert 22 of the lower mold 20 constituting the mold device, the upper mold 10 is raised by raising the lower mold 20 to the upper mold 10 side. As the insert 12 and the lower floating insert 22 come into contact with each other, the circuit board 1 is properly clamped.
이와 같은 상태에서 하부플로팅인서트(22)의 캐비티(22a) 내로 EMC의 공급이 이루어짐에 따라 회로기판(1)의 몰딩 영역()은 소정형태로 몰딩이 이루어지게 되는 것이다.In this state, as the EMC is supplied into the cavity 22a of the lower floating insert 22, the molding region of the circuit board 1 ( ) Is to be molded in a predetermined form.
하지만, 전술한 바와 같이 동작을 행하는 상부플로팅인서트(12)와 하부플로팅인서트(22)가 회로기판(1)에 제공하게 되는 가압력은 전체적으로 균일한 반면 이에 접촉되어 클램프되는 회로기판(1)은 전체적인 두께 편차가 심하여 클램프력이 매우 불균일하게 작용되는 현상을 발생하게 되었다.However, as described above, the pressing force applied to the circuit board 1 by the upper floating insert 12 and the lower floating insert 22, which operate as described above, is generally uniform, while the circuit board 1 that is contacted and clamped is The thickness variation is so great that the clamping force acts very unevenly.
이는, 회로기판(1)의 제조 공정상 비아홀(via hall)의 형성부분이 높아지는 현상이 두드러지기 때문으로써 이로 인해 상기 회로기판의 전체적인 두께가 균일하도록 형성하는데 많은 어려움이 있을 뿐만 아니라 상기 회로기판의 상, 하부금형을 닫았을 때에는 곧 회로기판의 표면이 깨어지는 문제점을 발생하게 된 것이다.This is because the phenomenon in which the via hole is formed in the manufacturing process of the circuit board 1 becomes prominent, which causes a great difficulty in forming the overall thickness of the circuit board as well as the difficulty of forming the circuit board. When the upper and lower molds are closed, the surface of the circuit board is broken soon.
즉, 회로기판(1)의 두께가 도시한 도 3의 1a, 1b와 같은 형상을 이루게 되는데 반해 상부플로팅인서트(12) 또는 하부플로팅인서트(22)가 전체적으로 평면을 이루도록 형성되어 있기 때문에 회로기판(1)의 두께가 비교적 두꺼운 부분(1a)에서는 클램프력이 크게 적용되어 그 무리한 힘에 의해 회로기판(1)에 형성된 각종 회로패턴의 손상을 유발시키는 문제점을 가지게 된 것이다.That is, the thickness of the circuit board 1 has the same shape as 1a and 1b of FIG. 3, whereas the upper floating insert 12 or the lower floating insert 22 is formed to form a flat surface. In the portion 1a having a relatively thick thickness, the clamp force is largely applied to cause damage of various circuit patterns formed on the circuit board 1 by the excessive force.
이에 따라 종래에는 상부플로팅인서트(12)의 상부에 구비된 심 플레이트(13)가 스프링(14)의 탄성력을 받도록 함으로써 회로기판에 가하게 되는 가압력을 완충하여 전술한 바와 같은 문제점을 해결하고자 하였다.Accordingly, in the related art, the shim plate 13 provided on the upper portion of the upper floating insert 12 receives the elastic force of the spring 14 to buffer the pressing force applied to the circuit board to solve the problems as described above.
하지만, 이 역시 각 플로팅인서트(12)(22)의 표면이 평면인 연유로 인하여 회로기판의 가장 두꺼운 부위에만 기준된 상태를 이루게 되어, 회로기판의 자체적인 각 부위 두께 편차에 대응하여 균일한 클램프력을 전달시킬 수는 없을 뿐만 아니라 일반적으로 각 플로팅인서트의 재질이 금속재임을 감안할 때 상호간의 클램프력에 의해 회로기판에 형성된 각 회로패턴의 손상은 항상 유발할 수 있게 된 문제점을 보유하게 되었다.However, this is also due to the flat surface of each floating insert (12, 22) to achieve a state based only on the thickest part of the circuit board, uniform clamp corresponding to the variation in the thickness of each part of the circuit board itself In addition, it is impossible to transmit the force, and in general, considering that the material of each floating insert is made of metal, damage to each circuit pattern formed on the circuit board due to mutual clamping forces can always be caused.
본 발명은 상기한 제반 문제점을 해결하기 위한 것으로서, 몰딩 공정을 수행하기 위해 상부금형이 하부금형에 밀착할 때 반도체칩이 실장된 회로기판이 상부플로팅인서트에 직접적으로 접촉하지 않도록 함과 함께 회로기판의 전체적인 두께 편차에도 관계없이 이에 적절히 대응된 상태로 상호간의 완전한 밀착이 이루어지도록 함으로써 상기 회로기판에 형성된 각 회로패턴이 손상됨을 미연에 방지할 수 있도록 몰딩 장비의 회로기판 크랙 방지구조를 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and when the upper mold is in close contact with the lower mold in order to perform the molding process, the circuit board on which the semiconductor chip is mounted does not directly contact the upper floating insert and the circuit board. The circuit board crack prevention structure of the molding equipment is provided to prevent the damage of each circuit pattern formed on the circuit board by making perfect close contact with each other in a state corresponding to this regardless of the overall thickness variation. There is a purpose.
도 1 은 일반적인 BGA형 반도체 패키지의 개략적인 구성을 나타낸 단면도1 is a cross-sectional view showing a schematic configuration of a typical BGA type semiconductor package
도 2 는 일반적인 BGA형 반도체 패키지 제조용 몰딩 장비를 개략적으로 나타낸 단면도Figure 2 is a schematic cross-sectional view showing a molding apparatus for manufacturing a typical BGA type semiconductor package
도 3 은 일반적인 기기가 몰딩 공정을 수행하기 위하여 상부금형과 하부금형이 상호 밀착된 상태를 나타낸 도 2의 “A”부 확대도Figure 3 is an enlarged view "A" of Figure 2 showing a state in which the upper mold and the lower mold is in close contact with each other in order to perform a molding process in a typical device;
도 4 는 본 발명에 따른 몰딩 장비를 개략적으로 나타낸 단면도Figure 4 is a schematic cross-sectional view of the molding equipment according to the present invention
도 5 는 본 발명에 따른 코팅막을 형성하였을 경우 상부금형과 하부금형이 상호 밀착된 상태를 나타낸 도 4의 “B”부 확대도Figure 5 is an enlarged view "B" of Figure 4 showing a state in which the upper mold and the lower mold is in close contact with each other when forming a coating film according to the present invention
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
10. 상부금형 12. 상부플로팅인서트10. Upper mold 12. Upper floating insert
20. 하부금형 22. 하부플로팅인서트20. Lower mold 22. Lower floating insert
30. 코팅막30. Coating film
상기한 목적을 달성하기 위한 본 발명의 형태에 따르면, 그 중앙에 설치된 하부센서블록 및 상기 하부센서블록의 양측에 패키지의 성형을 위해 각종 회로기판이 안착되도록 캐비티가 다수개 형성된 하부플로팅인서트를 구비한 하부금형과, 상기 하부금형에 대응된 상태로써 그 중앙에 설치된 상부센서블록 및 상기 상부센서블록의 양측에 설치되는 상부플로팅인서트를 구비한 상부금형으로 이루어진 몰딩 장비에 있어서, 상기 상부플로팅인서트의 각 부위중 하부플로팅인서트에 안착된 회로기판과의 접촉이 이루어지는 부위에 탄성을 지니는 재질로 이루어진 코팅막을 형성하여서 됨을 특징으로 하는 반도체 패키지 제조용 몰딩 장비의 회로기판 크랙 방지구조가 제공된다.According to an aspect of the present invention for achieving the above object, there is provided a lower sensor block installed in the center and a lower floating insert formed with a plurality of cavities so that various circuit boards are seated for molding the package on both sides of the lower sensor block. A molding apparatus comprising a lower mold, and an upper mold having an upper sensor block installed at a center thereof and an upper floating insert installed at both sides of the upper sensor block in a state corresponding to the lower mold. Provided is a circuit board crack prevention structure of a molding apparatus for manufacturing a semiconductor package, characterized in that the coating film made of a material having elasticity is formed on a portion where contact with the circuit board seated on the lower floating insert is formed.
이하, 본 발명의 일 실시예를 첨부도면 도 4를 참조하여 보다 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
도시된 도 4는 본 발명에 따른 몰딩 장비의 를 개략적으로 나타낸 단면도로서, 본 발명은 몰딩 장비를 구성하는 상부금형(10)의 상부플로팅인서트(12)의 각 부위중 하부플로팅인서트(22)에 안착된 회로기판(1)과 접촉하는 부위에 코팅막(30)을 형성하여서 된 것이다.4 is a cross-sectional view schematically showing the molding equipment according to the present invention, the present invention is to the lower floating insert 22 of each portion of the upper floating insert 12 of the upper mold 10 constituting the molding equipment The coating film 30 is formed on a portion in contact with the seated circuit board 1.
즉, 본 발명은 패키지 성형을 위해 몰딩을 수행하는 몰딩 장비의 상부플로팅인서트(12) 표면상에 코팅막(30)을 형성함으로써 금속재질로 이루어진 상부플로팅인서트(12)와 회로기판(1)과의 직접적인 접촉에 따른 회로기판(1)의 각 회로패턴이 손상됨을 방지할 수 있도록 한 것이다.That is, the present invention forms a coating film 30 on the surface of the upper floating insert 12 of a molding apparatus for molding a package, thereby forming the upper floating insert 12 made of metal and the circuit board 1. It is to prevent damage to each circuit pattern of the circuit board (1) due to direct contact.
이 때, 상기 코팅막의 재질은 다양하게 이룰 수 있으나 상호간의 접촉에 따른 완충 역할을 수행할 수 있는 테플론(Teflon)으로 형성함으로써 상부플로팅인서트와 회로기판(1)과의 접촉에 따른 충격을 완화하여 상기 회로기판의 크랙(crack)방지를 수행할 수 있도록 함이 보다 바람직하다.At this time, the material of the coating film can be made in various ways, but by forming a Teflon (Teflon) that can act as a buffer according to the mutual contact to alleviate the impact of the contact between the upper floating insert and the circuit board (1). It is more preferable to be able to perform crack prevention of the circuit board.
상기에서 테플론으로 상부플로팅인서트(12)의 면상에 코팅막(30)을 형성하는 영역은 회로기판(1)의 전 부분에 대하여 접촉하는 부위에 모두 형성하여도 상관은 없으나 바람직하기로는 회로기판(1)의 각 부분중 각종 회로 패턴이 형성된 부위()와 접촉하는 부위에만 코팅막(30)을 형성함이 그 제조비용의 절감상 더욱 효과적이나 이에는 한정하지 않는다.In the above, the region where the coating film 30 is formed on the surface of the upper floating insert 12 by Teflon may be formed in all the portions in contact with the entire portion of the circuit board 1, but preferably the circuit board 1 In which various circuit patterns are formed Forming the coating film 30 only in contact with the c) is more effective in reducing the manufacturing cost, but is not limited thereto.
또한, 상기 코팅막의 두께는 최소 상부플로팅인서트(12)의 저면과 동일선상에 위치하여야 하며, 바람직하기로는 상기 상부플로팅인서트의 저면보다 더욱 돌출된 상태를 이룰 수 있을 정도의 두께를 이루어도록 한다.In addition, the thickness of the coating film should be located on the same line as the bottom of the minimum floating insert 12, preferably to a thickness sufficient to achieve a more protruding state than the bottom of the upper floating insert.
즉, 상부금형(10)의 저면이 하부금형(20)의 상면에 맞닿았을 때 상부플로팅인서트(12)의 코팅된 부위가 하부금형(20)의 하부플로팅인서트(22)에 안착된 회로기판(1)과 완전히 밀착된 상태를 이룰 수 있도록 회록기판(1)의 두께 편차를 고려하여 돌출될 수 있도록 형성함이 보다 바람직한 것이다.That is, when the bottom surface of the upper mold 10 is in contact with the upper surface of the lower mold 20, the coated portion of the upper floating insert 12 is seated on the lower floating insert 22 of the lower mold 20 It is more preferable to form it so that it can protrude in consideration of the thickness variation of the memoirs board | substrate 1 so that it may come in close contact with (1).
이는, 코팅막(30)의 재질이 소정의 탄성을 지니고 있는 테플론임을 감안할 때 회로기판(1)의 두께가 전체적으로 불균일하다 하더라도 상부플로팅인서트(12)와 회로기판(1)의 접촉시 상기 회로기판이 압착되는 것이 아니라 코팅막(30)이 상기 회로기판의 표면 형상에 대응하여 변형됨으로써 상기 회로기판의 표면에 형성되는 각 회로패턴을 안전하게 보호할 수 있기 때문이다.This is because the thickness of the coating film 30 is a Teflon having a predetermined elasticity, even if the thickness of the circuit board 1 is uneven overall, the circuit board is contacted when the upper floating insert 12 and the circuit board 1 is in contact. This is because the coating film 30 is deformed to correspond to the surface shape of the circuit board instead of being compressed, thereby protecting each circuit pattern formed on the surface of the circuit board.
이하, 전술한 바와 같은 본 발명의 구성과 같이 상부플로팅인서트(12)의 면상에 테플론으로 코팅막(30)을 형성함으로써 회로기판(1)에 형성된 각종 회로패턴의 손상이 방지되는 과정을 보다 구체적으로 설명하면 후술하는 바와 같다.Hereinafter, as described above, the process of preventing damage to various circuit patterns formed on the circuit board 1 by forming the coating film 30 on the surface of the upper floating insert 12 with Teflon in more detail. It will be described later.
우선, 몰드 기기를 구성하는 하부금형(20)의 하부플로팅인서트(22)에 회로기판(1)을 안착시킨 후 상기 하부금형을 상부금형(10) 측으로 상승시키면 상부금형(10)의 저면과 하부금형(20)의 상면이 점차적으로 맞닿게 된다.First, when the circuit board 1 is seated on the lower floating insert 22 of the lower mold 20 constituting the mold device, and the lower mold is raised to the upper mold 10 side, the bottom and the bottom of the upper mold 10 are lowered. The upper surface of the mold 20 gradually comes into contact.
이에 따라 상기 하부금형을 구성하는 하부플로팅인서트(22)에 안착된 회로기판(1)이 상부플로팅인서트(12)의 저면에 점차적으로 밀착되는데, 이 때 상기 상부플로팅인서트의 저면인 회로기판(1)과의 접촉부위에는 테플론으로 코팅이 이루어진 코팅막(30)이 형성되어 있음에 따라 실질적으로는 상기 코팅막과 회로기판과의 밀착이 이루어지면서 회로기판(1)의 압착이 이루어지게 된다.Accordingly, the circuit board 1 seated on the lower floating insert 22 constituting the lower mold is gradually in close contact with the bottom of the upper floating insert 12. At this time, the circuit board 1, which is the bottom of the upper floating insert. As a coating film 30 formed of Teflon coating is formed at the contact portion of the c), the circuit board 1 is pressed while the adhesion between the coating film and the circuit board is substantially achieved.
이와 같은 과정에서 회로기판(1)의 전체적인 두께가 불균일함을 감안할 때 상기 회로기판의 각 부위중 비교적 두께가 두꺼운 부분(1a)은 상부플로팅인서트(12)에 형성된 코팅막(30)과 많은 밀착이 이루어지게 되고, 상기 회로기판의 각 부위중 비교적 두께가 얇은 부분(1b)은 상기 코팅막과 적은 밀착이 이루어지게 된다.Considering that the overall thickness of the circuit board 1 is nonuniform in this process, the relatively thick portion 1a of each portion of the circuit board 1 has a lot of close contact with the coating film 30 formed on the upper floating insert 12. The relatively thin portion 1b of each part of the circuit board is made to be in close contact with the coating film.
하지만, 상기와 같이 회로기판(1)의 두께가 얇은 부분(1b)과 코팅막(30)과의 밀착이 적게 이루어진다 하더라도 상기 회로기판의 전면적에 대하여서는 완전한 밀착을 이룰 수 있게 된다.However, even if the contact between the thin portion 1b of the circuit board 1 and the coating film 30 is less formed as described above, complete contact with the entire area of the circuit board can be achieved.
즉, 테플론으로 이루어진 코팅막(30)의 전체적인 두께(t)가 회로기판(1)의 전부분에 대하여 완전한 밀착을 행할 수 있을 정도로 충분히 두꺼울 뿐 아니라 상기 테플론의 재질적인 특성상 소정의 탄력을 지니고 있음에 따라 도시한 도 5와 같이 코팅막(30)은 불균일한 표면을 가지는 회로기판(1)의 전 면적에 따른 형상에 대응하여 변형됨으로써 고른 밀착이 이루어질 수 있게 되는 것이다.That is, the overall thickness (t) of the coating film 30 made of Teflon is not only thick enough to be in close contact with the entire portion of the circuit board 1, but also has a predetermined elasticity due to the material properties of the Teflon. Accordingly, as shown in FIG. 5, the coating film 30 may be deformed in correspondence to the shape of the circuit board 1 having a non-uniform surface so as to achieve even contact.
또한, 이 때에는 상호간의 밀착에 따른 클램프력을 코팅막(30)에 의해 거의 흡수됨에 따라 회로기판(1)으로 전달되는 클램프력은 극히 미미한 상태가 되어 상기 회로기판에 형성된 각종 회로패턴의 손상을 방지할 수 있게 된다.In addition, at this time, as the clamp force due to close contact with each other is almost absorbed by the coating film 30, the clamp force transmitted to the circuit board 1 becomes extremely insignificant to prevent damage to various circuit patterns formed on the circuit board. You can do it.
이는, 회로기판(1)과 접촉되는 부분이 금속재질로 이루어진 상부플로팅인서트(12)의 표면이 아니라 비교적 유연한 성분의 테플론으로 코팅된 코팅막(30)임에 따라 가능하다.This is possible because the part in contact with the circuit board 1 is not the surface of the upper floating insert 12 made of a metal material, but the coating film 30 coated with Teflon of a relatively flexible component.
결국, 전술한 바와 같은 상태에서 하부플로팅인서트(22)의 캐비티(22a) 내로 EMC를 공급함으로써 회로기판(1)의 몰딩 영역()에 대한 소정 형태로의 몰딩이 원활히 이루어지게 된다.As a result, in the above-described state, by supplying EMC into the cavity 22a of the lower floating insert 22, the molding region of the circuit board 1 ( Molding into a predetermined shape is smoothly performed.
이상에서 설명한 바와 같이 본 발명은 상부금형을 구성하는 상부플로팅인서트의 표면상인 회로기판과 접촉을 행하는 부위에 테플론 재질을 코팅한 코팅막을 형성함으로써 상부플로팅인서트의 표면과 회로기판과의 직접적인 접촉을 방지할 수 있게 되어 회로기판에 형성된 각종 회로패턴의 손상(crack)을 방지할 수 있게 된 효과가 있다.As described above, the present invention prevents direct contact between the surface of the upper floating insert and the circuit board by forming a coating film coated with a Teflon material on a portion that makes contact with the circuit board on the surface of the upper floating insert constituting the upper mold. It is possible to prevent the damage (crack) of the various circuit patterns formed on the circuit board.
또한, 상부플로팅인서트에 형성된 코팅막이 회로기판의 두께 편차에 관계없이 상기 회로기판의 전 면적에 대하여 완전한 밀착을 행할 수 있게 되어 몰딩시 콤파운드재(EMC)의 외부 누출을 방지할 수 있게 되어 몰딩 성능을 향상시킬 수 있는효과 역시 있다.In addition, the coating film formed on the upper floating insert can be in close contact with the entire area of the circuit board regardless of the thickness variation of the circuit board to prevent the external leakage of the compound material (EMC) during molding molding performance There is also an effect that can improve.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1999-0054303A KR100390451B1 (en) | 1999-12-01 | 1999-12-01 | prevention structure for crack of substrate for manucture of semiconductor package in moulder |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1999-0054303A KR100390451B1 (en) | 1999-12-01 | 1999-12-01 | prevention structure for crack of substrate for manucture of semiconductor package in moulder |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010053791A KR20010053791A (en) | 2001-07-02 |
| KR100390451B1 true KR100390451B1 (en) | 2003-07-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-1999-0054303A KR100390451B1 (en) | 1999-12-01 | 1999-12-01 | prevention structure for crack of substrate for manucture of semiconductor package in moulder |
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| Country | Link |
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| KR (1) | KR100390451B1 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6414946A (en) * | 1987-07-09 | 1989-01-19 | Toshiba Corp | Method and apparatus for forming lead of semiconductor device |
| US5923959A (en) * | 1997-07-23 | 1999-07-13 | Micron Technology, Inc. | Ball grid array (BGA) encapsulation mold |
| KR100219577B1 (en) * | 1997-06-27 | 1999-09-01 | 한효용 | Correction apparatus of semiconductor chip package |
| KR20010027015A (en) * | 1999-09-10 | 2001-04-06 | 마이클 디. 오브라이언 | mold for manufacturing semiconductor package |
-
1999
- 1999-12-01 KR KR10-1999-0054303A patent/KR100390451B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6414946A (en) * | 1987-07-09 | 1989-01-19 | Toshiba Corp | Method and apparatus for forming lead of semiconductor device |
| KR100219577B1 (en) * | 1997-06-27 | 1999-09-01 | 한효용 | Correction apparatus of semiconductor chip package |
| US5923959A (en) * | 1997-07-23 | 1999-07-13 | Micron Technology, Inc. | Ball grid array (BGA) encapsulation mold |
| KR20010027015A (en) * | 1999-09-10 | 2001-04-06 | 마이클 디. 오브라이언 | mold for manufacturing semiconductor package |
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| Publication number | Publication date |
|---|---|
| KR20010053791A (en) | 2001-07-02 |
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