KR100390449B1 - Chip selection apparatus of memory device - Google Patents

Abstract

PURPOSE: A chip selection apparatus of a memory device is provided to prevent current consumption and to improve speed according to chip selection. CONSTITUTION: A chip selection apparatus includes an address buffer part(21), a free decoder part(22), a chip selection buffer part(23) for temporally storing a selection signal, a main decoder part(24), an external power sense part(25), and a switching part(26). The address buffer part(21) stores temporally a plurality of address. The addresses decodes firstly by the free decoder part(22). The switching part(26) further includes an inverter(26a) for inverting outputs of the external power sense part, the first transfer gate(26b) for outputting the selection signal to the address buffer part, and the second transfer gate(26c) for outputting the selection signal to the main decoder part.

Description

Chip selector of memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a chip selection control apparatus for high speed and low power SRAM.

Hereinafter, a chip selector of a conventional memory device will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a chip selector of a conventional memory device.

As shown in FIG. 1, a chip selector of a conventional memory device includes an address buffer unit 11 for temporarily storing a plurality of addresses input through a pad, and a pre decoder unit 12 for distinguishing and decoding the plurality of addresses. And a chip select buffer unit 13 for temporarily storing a select signal of a chip to be selected, and a chip select signal output from the chip select buffer unit 13 and an output of the pre decoder unit 12 together. The main decoder unit 14 outputs word lines.

The operation description of the chip selector of the conventional memory device configured as described above is as follows.

As shown in FIG. 1, when a plurality of addresses are input to the address buffer unit 11 through the address pad, the address buffer unit 11 temporarily stores them.

The decoder is decoded by the predecoder 12. The predecoder 12 decodes the pre-decoder 12 in advance when a plurality of input addresses are decoded at once.

At this time, when the chip select signal is output from the chip select buffer unit 13, the main decoder unit 14 decodes the output of the pre decoder unit 12 and the left output of the chip select buffer unit 13 to the word line. The output will select the desired chip.

However, the chip selector of the conventional memory device as described above has the following problems.

That is, although the chip select signal is connected to the decoder to advance the chip select time, when the standby current and the address frequency are maximum, a large current flows.

In other words, it is not a problem when the address frequency or the standby current is small, but when the configuration as in the prior art has a problem that the processing speed is increased but the current is consumed unnecessarily.

An object of the present invention is to provide a chip selector for a memory device suitable for preventing the consumption of unnecessary current by detecting an external voltage and controlling an address buffer when the voltage is high.

1 is a block diagram illustrating a chip selector of a memory device according to the related art.

2 is a block diagram of a chip selector of a memory device according to the present invention;

Explanation of symbols for main parts of the drawings

21: address buffer section 22: pre decoder section

23: chip select buffer section 24: main decoder section

25: external power detection unit 26: switching unit

The chip selector of the memory device of the present invention for achieving the above object comprises: an address buffer section for temporarily storing a plurality of addresses input through a pad, a pre decoder section for first decoding the plurality of addresses, and a selection; A chip select buffer unit for temporarily storing a select signal of a chip to be stored, a main decoder unit decoding a chip select signal output from the chip select buffer unit and an output of the pre decoder unit together and outputting a word line, and an external device to be applied And a switching unit for selectively applying a chip selection signal output from the chip selection buffer unit to the address buffer unit or the main decoder unit according to an output state of the external power detector unit.

Hereinafter, a chip selector of a memory device of the present invention will be described with reference to the accompanying drawings.

Fig. 2 is a block diagram of the chip selector of the memory device of the present invention.

As shown in FIG. 2, an address buffer 21 for temporarily storing a plurality of addresses input through a pad, a pre decoder 22 for separately decoding the plurality of addresses, and a chip to be selected A chip select buffer unit 23 for temporarily storing signals, and a main decoder unit for decoding the chip select signal output from the chip select buffer unit 23 and the output of the pre decoder unit 22 and outputting the word lines as word lines. (24), the external power detector 25 for detecting the applied external power, and the chip select signal output from the chip select buffer 23 according to the output state of the external power detector 25 in the address buffer. And a switching head 26 selectively applied to the unit 21 or the main decoder unit 24.

Here, the switching unit 26 is an inverter 26a for inverting the output of the external power source detecting unit 25, a first transfer gate 26b for determining whether to operate according to the output state of the inverter 26a, And a second transfer gate 26c having an operation determined according to the output state of the external power detection unit 25.

At this time, if the output of the external power detector 25 is at a high level, the second transfer gate 26c is turned off and the first transfer gate 26b is turned on to output the chip from the chip select buffer 23. The selection signal is applied to the address buffer unit 21.

When the output of the external power detector 25 is at a low level, the first transfer gate 26b is turned off and the second transfer gate 26c is turned on, so that the chip select signal is the main decoder unit 24. Is applied.

The operation description of the chip selector of the memory device of the present invention configured as described above is as follows.

As shown in FIG. 2, when a plurality of addresses are applied through the pad, the address buffer unit 21 buffers the input address.

Then, the output of the address buffer unit 21 is decoded and sent to the word line. When the input address is a plurality of addresses, it takes a long time to decode them at once, so that the pre-decoder unit 22 firstly decodes the output. To decode it.

In this case, when the external power applied by the external power detector 25 is detected and its value is high level, the first transfer gate 26b is turned on.

Therefore, the chip select signal output from the chip select buffer unit 23 is applied to the address buffer unit 21 through the first transfer gate 26b.

As a result, when the external power source is at a high level, the operation of the address buffer unit 21 is controlled to prevent the subsequent operation, thereby preventing unnecessary current consumption.

When the external power source is at a low level, the second transfer gate 26c is turned on and the chip select signal is applied to the main decoder unit 24 through the second transfer gate 26c.

Therefore, in the low level, only the speed according to the chip selection needs to be improved, and thus, the main decoder 24 may be controlled in the same manner as in the related art.

As described above, the chip selector of the memory device of the present invention has the following effects.

When the external power supply is at high level, the address buffer is controlled to reduce current consumption. At low level, the main decoder is controlled to improve the speed according to chip selection.

Claims (2)

An address buffer unit for temporarily storing a plurality of addresses input through the pad, A pre decoder unit for decoding the plurality of addresses primarily; A chip selection buffer unit for temporarily storing a selection signal of a chip to be selected; A main decoder unit for decoding the chip select signal output from the chip select buffer unit and the output of the pre decoder unit together and outputting the decoded word line; An external power detection unit for detecting an applied external power, An inverter for inverting the output of the external power detector, a first transfer gate for outputting a chip select signal to the address buffer according to the output states of the inverter and the external power detector, and an output state of the inverter and the external power detector; And a switching unit including a second transfer gate for outputting a chip selection signal to the main decoder unit. The method of claim 1, wherein the switching unit applies a chip select signal to the address buffer unit when the output of the external power detector is high level, and applies a chip select signal to the main decoder unit when the output of the external power detector is low level. Chip selector of memory device.