KR100427033B1 - Apparatus for driving word line of semiconductor memory device and method thereof at low voltage stably - Google Patents

Abstract

PURPOSE: An apparatus for driving a word line of a semiconductor memory device and a method thereof are provided, which operate at a low voltage stably by preventing the word line from being selected during a write operation, by disabling a word line enable signal. CONSTITUTION: According to the apparatus for driving a word line of a semiconductor memory device controlled by a number of control signals including an address signal and a data signal and a write enable signal and a chip selection signal, a decoding unit(402) decodes the address signal and generates a decode signal to determine a memory cell to access. A pulse signal generation unit(404) generates a pulse signal in response to the control signal. A sensing signal generation unit(400) is enabled by one of the control signals, and generates a sensing signal disabled in response as the write enable signal is disabled. And a word line enable signal generation unit(406) generates a word line enable signal by receiving the pulse signal and the sensing signal and a decoding signal of the address.

Description

Word line driver of semiconductor memory device and method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a word line driving apparatus and a method thereof of a semiconductor memory device, and more particularly to a word line driving apparatus and a method of a semiconductor memory device operating at a low power supply voltage (4V or less).

In general, the conventional semiconductor memory device uses 5V as its operating power supply voltage. However, as the size of individual devices in the memory device decreases due to the recent increase in integration, the operating power supply voltage is less than 4V to secure the reliability of the device. It is getting lower.

A conventional word line driver will be described with reference to FIGS. 1 to 3.

1 is a circuit diagram of an embodiment of a core portion 10 including a memory cell 100 of an SRAM that is one of semiconductor memory devices. As shown in FIG. 1, in the SRAM, two access transistors 102 and 102 'are turned on by selecting a specific word line to read and write to a selected memory cell (hereinafter referred to as "access"). ). In addition, the SRAM core unit 10 includes at least one equalizing transistor 104 and pull-up transistors 106 and 106 'in order to precharge or equalize the memory cell 100 according to a predetermined control signal. It comprises a precharge means 110 having a).

The access operation of the memory cell 100 as described above will now be described with reference to FIGS. 2 and 3. FIG. 2 is a conceptual block diagram of a conventional word line driver and related peripheral circuits for selecting a specific word line to access the memory cell 100 described above. FIG. 3 is a block diagram of the conventional word line driver of FIG. The operation timing diagram of the pulse wordline method is shown. In general, the pulse word line method refers to a word line in by multiplying a decoded signal obtained by decoding an address signal and a pulse signal having a predetermined width, in order to enable the selected word line only for a predetermined period. The generation of an enable signal (wordline).

In order to implement the pulse word line scheme as described above, the peripheral circuit unit may include an address buffer means 200 and a chip select signal csb for generating an address transition detection signal atd in response to a change in the address signal add. A chip select signal buffer means 202 for generating a chip select transition detection signal ced in response to a change in the < RTI ID = 0.0 >), < / RTI > generating a write enable transition detection signal wed in response to a change in the write enable signal web. The write enable signal buffer means 204, the data buffer means 206 for generating a data transition detection signal dtd in response to a change in the data signal din input from the outside, and each of the transition detection signals described above. Pulse sensing means 208 for generating a predetermined internal control signal comprising a precharge signal (pullupb, peqb).

In addition, the conventional word line driving apparatus includes decoding means 210 for determining a memory cell for decoding and accessing the address signal add, pulse signal generating means for generating a pulse signal having a constant length ( 212 and logical AND means 214. Here, the output signal of the pulse detecting means 208 is input to the decoder means 210 and the pulse signal generating means 212, respectively, according to the type of the output, and also the equalizing operation of the memory cell 100 It may also be input to the memory cell 100 to control.

The outputs of the decoder means 210 and the pulse signal generating means 212 are logically multiplied by the AND product 214 to generate a wordline enable signal, and the wordline enable signal A specific word line of the memory cell 100 is selected.

However, as described above, the core portion 10 of the SRAM including a plurality of memory cells, the pull-up signal (pullupb) generated by the peripheral circuit portion for the equalization operation and the pull-up operation, and the pulse detection means ( Also receives an equalize (peqb) signal by 208. That is, the core part 10 is controlled by several different control signals, respectively.

Therefore, as shown in FIG. 3, while the word line is selected by the word line enable signal, a write recovery operation in which a precharge operation or a pull-up operation of the memory cell is performed is performed. It may cause malfunction and instability. In particular, the malfunction and instability of such a memory cell is more severe as the operating power supply voltage is lowered.

Accordingly, an object of the present invention is to disable the word line enable signal in response to the write enable signal being disabled, thereby preventing the word line from being selected during the write recovery operation, and thus stably operating under a low voltage power supply. It is to provide a word line driving device of the device.

Another object of the present invention is to provide a word line driving method of a semiconductor memory device having a control system capable of operating stably.

1 is a detailed circuit diagram of a core part including memory cells of an SRAM.

2 is a conceptual block diagram of a conventional wordline driver and associated peripheral circuitry.

3 is an operation timing diagram of a pulse word line driving method of the word line driving apparatus of FIG.

4 is a conceptual block diagram of one embodiment of a word line driver of the present invention and associated peripheral circuitry.

5 is an operation timing diagram of the word line driver of FIG.

6 is a detailed circuit diagram of one embodiment of the sense signal generating means.

* Explanation of the symbols of the main parts of the drawings

10. Koabu 100. Memory Cells

102, 102 '. Access Transistor 104. Equalize Transistor

106, 106 '. Pull-up transistor 200. Address buffer means

202. Chip select signal buffer means 204. Write enable signal buffer means

206. Data buffer means 208. Pulse detection means

210. Decoding means 212. Pulse signal generating means

214. Logical means 400. Means for generating detection signals

402. Decoding means 600. Flip flop

602, 602 '. Noah gate 604.4-input ora gate

606, 608. Inverter

In order to achieve the above object, the present invention is a word line driving apparatus of a semiconductor memory device which is controlled by a plurality of control signals including an address signal, a data signal, a write enable signal and a chip select signal. Decoding means for generating a decode signal for determining a memory cell to be accessed; Pulse signal generating means for generating a pulse signal having a predetermined width in response to the control signal; Sensing signal generation means for generating a sensing signal that is enabled by any one of the first transitions of each of the control signals, and disabled in response to the write enable signal being disabled; And a word line enable signal generation means for receiving the pulse signal, the sense signal, and the decoded signal of the address to generate a word line enable signal.

In addition, the present invention provides a word line driving method of a semiconductor memory device in which a write operation and a read operation are performed in response to enabling and disabling of a write permission signal, respectively, to decode an address signal to determine a memory cell to be accessed. Doing; Generating a pulse signal having a predetermined width; And enabling the word line in the read operation for the same period as the pulse signal and in the write operation for the period from the enable of the pulse signal to the disable of the write permission signal. A word line driving method of a semiconductor memory device is provided.

An embodiment of the present invention will now be described with reference to FIGS. 4 to 6.

4 is a conceptual block diagram of an embodiment of the word line driving apparatus of the present invention and its associated peripheral circuit, and FIG. 5 is an operation timing diagram of the word line driving apparatus of FIG. As shown in FIG. 4, the word line driving apparatus of the present invention decodes an address signal add input from the address buffer 200 through the pulse sensing means 208 to generate a decode signal. Decoding means 402 for carrying out the operation. In addition, in order to drive a word line using the pulse word line method, a pulse signal pwl having a predetermined width in response to an internal control signal including each of the transition detection signals atd, ced, wed, and dtd. Pulse signal generating means (404) for generating a), which is enabled by any of the first transition of each of the transition detection signals (atd, ced, wed, and dtd), and the write enable signal (web). Detection signal generating means 400 for generating a detection signal which is disabled in response to being disabled and a decode signal of the pulse signal pwl, the detection signal and the address. Word line enable signal generation means 406 for receiving and generating a word line enable signal (wordline).

That is, the word line driving apparatus of the present invention is enabled by the first detection signal generated among the remaining transition detection signals atd, dtd, wed, and ced other than the write disable transition detection signal wdtdb. The word line is driven by generating a detection signal that is disabled by the disable transition detection signal wdtdb.

Referring to FIG. 6, FIG. 6 is a detailed circuit diagram of an embodiment of the sensing signal generating means 400. As shown in FIG. That is, the sensing signal generating unit 400 uses the output of the four input ora gate 604 which inputs the transition detection signals atd, dtd, wed, and ced as one side input, and the two NOR gates 602, 602 ') may be implemented as a flip flop 600. The other input of the flip flop 600 uses an inverted signal of the write disable transition detection signal wdtdb. That is, the write disable transition detection signal wdtdb is input to one input terminal of the flip-flop 600 via the inverter 606, and the transition detection signals atd, dtd, wed, and ced except for 4 are input. The input OR gate 604 is ORed and input to the other input terminal of the flip flop 600 to generate the detection signal.

Thus, by the detection signal (detection) by the detection signal generation means 400, by the decode signal (glodecode) and pulse signal generation means 404 obtained by decoding the address signal (add) by the decoding means 402. The generated pulse signal pwl is logically multiplied by the AND product 406 to generate a wordline enable signal for selecting a particular memory cell.

Accordingly, the wordline enable signal wordline has a sufficient pulse width during a read operation, and has a pulse width that is disabled at the same time as the write enable signal web is disabled during a write operation.

According to the present invention, a wordline enable signal (wordline) for accessing a specific memory cell can be controlled to be disabled at the same time as the write enable signal (web) is disabled. Accordingly, the memory cell does not malfunction or enter into an unstable state due to a pull-up operation or an equalization operation for the write recovery operation, and a stable operation can be ensured even under a low power supply.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Claims (6)

A word line driving apparatus of a semiconductor memory device controlled by a plurality of control signals including an address signal, a data signal, a write enable signal, and a chip select signal, Decoding means for decoding the address signal to generate a decode signal for determining a memory cell to be accessed; Pulse signal generating means for generating a pulse signal having a predetermined width in response to the control signal; Sensing signal generation means for generating a sensing signal that is enabled by any one of the first transitions of each of the control signals, and disabled in response to the write enable signal being disabled; And And word line enable signal generation means for receiving the pulse signal, the sense signal, and the decoded signal of the address to generate a word line enable signal. The method of claim 1, The detection signal generating means A word line driving apparatus of a semiconductor memory device, comprising a flip flop. The method of claim 2, The detection signal generating means An OR gate for inputting a plurality of control signals including the address signal, data signal, write enable signal, and chip select signal to the first input terminal of the flip flop; And And an inverter configured to supply the disable transition detection signal generated in response to the write enable signal being disabled as an input and supply the input signal to the second input terminal of the flip flop. Drive system. The method of claim 1, And said word line enable signal generating means is three input and gate. Controlled by a plurality of control signals including an address signal, a data signal, a write enable signal, and a chip select signal, and in response to enabling and disabling of the write enable signal, write and read operations are performed, respectively. In a word line driving method of a semiconductor memory device, Decoding a address signal to determine a memory cell to access; Generating a pulse signal having a predetermined width; And And driving the word line to enable the word line from the enabling of the pulse signal to the timing of disabling the write enable signal during the write operation. The method of claim 5, wherein Driving the word line Enabling a sensing signal in response to a transition of a control signal that is initially transitioned among control signals including the address signal, data signal, write enable signal, and chip select signal; Disabling the sense signal in response to the write enable signal being disabled; And And disabling the word line in response to the sensing signal being disabled.