KR100309802B1 - Semiconductor memory device for executing redundancy operati0n - Google Patents

Abstract

PURPOSE: A semiconductor memory device for executing redundancy operation is provided to reduce time necessary for activating a normal word line and a redundancy word line each connected to a normal memory cell array and a redundancy memory cell array. CONSTITUTION: A normal word line driver circuit(70) selects and drives word lines of a normal memory cell array(90) in response to an externally applied address signal. A redundant word line driver circuit(75) stores defective memory cell addresses, and outputs a redundant enable drive signal when an address appointing a defective memory cell is received. At the same time, the redundant enable drive signal drives a word line of a redundant memory cell array(85). The first sense amplifier circuit(95) reads out data from the normal memory cell array, and the second sense amplifier circuit(100) reads out data from the redundant memory cell array. A sense amplifier control circuit(80) inactivates the first sense amplifier and activates the second sense amplifier, in response to a control signal informing a redundant mode.

Description

Semiconductor memory device that performs redundancy operation {SEMICONDUCTOR MEMORY DEVICE FOR EXECUTING REDUNDANCY OPERATI0N}

1 is a schematic block diagram of a semiconductor memory device for performing a redundancy operation according to the prior art.

FIG. 2 is an operation timing diagram for performing a redundancy operation in the semiconductor memory device shown in FIG.

3 is a schematic block diagram of a semiconductor memory device for performing a redundancy operation in a preferred embodiment according to the present invention.

4 is an operation timing diagram for performing a redundancy operation in the semiconductor memory device shown in FIG.

5 shows a sense amplifier control circuit according to FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device that performs a redundancy operation to replace such defective memory cells with redundant memory cells when a defective memory cell occurs in a normal memory cell array.

In general, when a defect occurs in a normal memory cell located in a normal memory cell array, a semiconductor memory device includes a redundancy circuit that decodes an address signal designating a defective memory cell and replaces it with a redundant memory cell. By such a redundancy circuit, defective memory cells of the normal memory cell array are replaced by redundant memory cells of the redundant memory cell array. At this time, an address signal for designating a defective memory cell is used for a circuit and the like for decoding the address signal, a circuit for activating a redundant word line, and disabling the normal word line.

In general, a decoding method for replacing a defective memory cell with a redundant memory cell is performed when a defect occurs in a normal memory cell of any one of the normal memory cell arrays divided into a plurality of blocks. A method of replacing the entire block including the block with the corresponding block of the redundant memory cell is mainly used. In order to perform such an operation, a sensing device such as a fuse circuit capable of detecting a defective address and a redundant decoder for selecting a redundant word line of a redundant memory cell array from the detected defective address are required. The semiconductor memory device performing the redundancy operation must internally determine whether the normal mode or the redundant mode is performed. Techniques for this are disclosed in detail in US Pat. Nos. 4,672,581 and 4,389,715.

1 is a schematic block diagram of a semiconductor memory device performing a redundancy operation according to the related art. The configuration shown in FIG. 1 is typically used for semiconductor memory devices that perform redundancy operations. The normal memory cell array 30 and the redundant memory cell array 50 are connected to the normal word line driver circuit 25 and the redundant word line driver circuit 45, respectively. On the other hand, the normal memory cell array 30 and the redundant memory cell array 50 are commonly connected to one sense amplifier 40, and the sense amplifier 40 is connected to an external output line. In normal operation, data read from a predetermined normal memory cell in the normal memory cell array 30 is transferred to an external output line through the sense amplifier 40 and output to the outside. In addition, when a defect occurs in the normal memory cell array 30, the redundant memory cell array 50 is selected to replace the defective memory cell in the normal memory cell array 30, and data read from the redundant memory cell replaces the sense amplifier 40. It is transmitted to an external output line and output to the outside. As described above, when data is read from the normal memory cell array 30 or a defect occurs in the normal memory cell array 30, the process of reading data from the redundant memory cell array 50 and transferring the data to the external output line through the sense amplifier 40 is known in the art. It is self-evident to those of ordinary knowledge.

The operation of the semiconductor memory device for performing the redundancy operation according to the related art will be described in detail with reference to FIGS. 1 and 2. 1 is a schematic block diagram of a semiconductor memory device for performing a redundancy operation according to the prior art. FIG. 2 is an operation timing diagram for performing a redundancy operation in the semiconductor memory device shown in FIG.

Now, if the address signal Ai (i = 0 to i) is input after the row address strobe signal / RAS is input to the row address input buffer 5, the address signal Ai (i = 0 to i) is in the row address input buffer 5. After shaping at, it is supplied to the predecoder 10. When the shaped address signals RAi and / RAi are input to the predecoder 10, the predecoder 10 outputs the decoded signal? DPXi pre-decoded the shaped address signals RAi and / RAi, and the output decoded signal? DPXi is a normal word line driving circuit. And 25 to the redundant word line driver circuit 45, respectively.

The predecoder 10 also generates a predetermined activation signal for activating the Φ XE generation circuit 15. The output signal? XE of the? XE generating circuit 15 is input to the redundant word line driving circuit 15 and the? RRE generating circuit 35, respectively. The redundant word line driver circuit 45 outputs a signal ΦREDi (Reduntdant Enable Driver) (where i is an integer including ()) to the ΦRRE generating circuit 35 when the input decoding signal ΦDPXi is an address signal for selecting the redundant word line. The redundant word line selection signal Xj for activating the redundant word line is output to allow the redundant memory cell array 50 to be selected.

At this time, the signal ΦREDi output from the redundant word line driver circuit 45 is input to the RAS Redundant Enable generator (hereinafter referred to as “ΦRRE”) generation circuit 35 and then normalized by a combination with the output signal ΦXE of the ΦXE generation circuit 15. A Φ RRE signal is generated for controlling the word line driver circuit 25, and the φ RRE signal is input to the normal word line driver circuit 25. After a predetermined time has elapsed, the output signal ΦX of the ΦX generating circuit 20 is input to the normal wordline driving circuit 25 and the redundant wordline driving circuit 45, whereby the redundant wordline driving circuit 45 is activated, and the normal wordline driving circuit 25 is deactivated. do. Here, the signal ΦX has a level of boosting voltage for driving the normal word line or the redundant word line in a stable state.

As a result, data is read from the corresponding redundant memory cell in the redundant memory cell array connected to the selected redundant word line. At this time, after the sense amplifier 40 is activated by the sense amplifier control signal .phi.S, the read data is transmitted to the external output line. If the predetermined address signal applied to the redundant word line driver circuit 45 is an address signal that does not select the redundant word line, that is, in the normal mode, the redundant word line driver circuit 45 is deactivated, and the normal word line driver circuit 25 Is activated.

However, in the semiconductor memory device performing the redundancy operation according to the prior art, as shown in FIG. 2, the output signal? X of the? X generation circuit 20 is in the redundant mode by the signal? RRE for controlling the normal wordline driving circuit. Or after the normal mode is determined. That is, since the output signal ΦX of the ΦX generating circuit 20 is activated after being delayed by the time t, the redundant word line selection signal Xj is activated by being delayed by the time t in the redundant mode. As a result, unnecessary time is delayed in selecting a predetermined redundant memory cell of the redundant memory cell array.

On the other hand, according to the configuration of FIG. 1, even in the normal mode, the output signal ΦX is activated after being delayed by the time t. Therefore, an unnecessary time is delayed in selecting a predetermined normal memory cell of the normal memory cell array. In other words, in the semiconductor memory device according to the related art of FIG. 1, it takes time to determine whether it is a normal mode or a redundant mode. Therefore, there is a bad problem that the overall speed of the semiconductor memory device is reduced.

In addition, since unnecessary time is required for activating a normal word line or a redundant word line, there is a problem that the data output speed is lowered.

The present invention eliminates the determination time of the redundant mode or the normal mode, which is a problem of the prior art, and simultaneously activates the normal word line driving circuit and the redundant word line driving circuit, thereby shortening the activation time of the normal word line and the redundant word line. To increase the data output speed.

Accordingly, an object of the present invention is to provide a semiconductor memory device capable of reducing the time required to activate a normal word line and a redundant word line connected to a normal memory cell array and a redundant memory cell array, respectively.

Another object of the present invention is to provide a semiconductor memory device that performs a high speed data output operation.

Another object of the present invention is to provide a semiconductor memory device having an optimal redundancy efficiency.

An object of the present invention as described above is a semiconductor memory device for replacing a defective memory cell located in a normal memory cell array with a redundant memory cell of a redundant memory cell array, wherein the normal memory cell corresponds to an address signal input from an external source. Normal word line driving means for selecting and driving a word line of an array, and storing the defective memory cell address in itself, and providing a redundant enable drive signal when the external address signal is applied to designate the defective memory cell. Redundant word line driving means for outputting and driving word lines of the redundant memory cell array, first sense amplifier means for reading data from the normal memory cell array and transferring the data to an external output line, and the redundant memory cell array Day from Inputting a second sense amplifier means for reading and transmitting to the external output line and a control signal indicating a redundant mode from the redundant word line driving means to deactivate the first sense amplifier and to activate the second sense amplifier. It is achieved by providing a semiconductor memory device, characterized in that it comprises a sense amplifier control means.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

3 is a schematic block diagram of a semiconductor memory device for performing a redundancy operation according to the present invention. The normal word line driver circuit 70 is connected to the normal memory array 90, and the redundant word line driver circuit 75 is connected to the redundant memory cell array 85. The redundant word line driver circuit 75 stores a defective address in itself, and when an address signal specifying the redundant word line is applied, the redundant word line driver circuit 75 selects and drives the redundant word line of the redundant memory cell array, and simultaneously indicates a redundant mode. Input ΦREDi to the sense amplifier control circuit 80. In addition, the normal memory cell array 90 is connected to the first sense amplifier 95, and the redundant memory cell array 85 is connected to the second sense amplifier control circuit 100. Data read from the normal memory cell or the redundant memory cell through the first and second sense amplifier circuits 95 and 100 are transmitted to an external output line. Further, the first and second sense amplifier circuits 95 and 100 are controlled by the output signals? LANGN and? LANGS of the sense amplifier control circuit 80, respectively.

The operation of the semiconductor memory device for performing the redundancy operation according to the present invention will be described in detail with reference to FIG. 3, FIG. 4, and FIG. 5, which shows a sense amplifier control circuit 80. FIG.

Now, when the address signal Ai (i = () to i) is input to the row address input buffer 55 after the row address strobe signal / RAS having the logic " low " state in the active state as shown in FIG. 4 is inputted, the address signal Ai (i = () ~ i) is shaped in the row address input buffer 55 and then input to the predecoder 60. The predecoder 60 outputs the decoded signal? DPXi pre-decoded with the address signals RAi and / RAi, and the output decoded signal? DPXi is commonly input to the normal word line driver circuit 70 and the redundant word line driver circuit 75. In addition, the predecoder 60 outputs a predetermined drive signal for driving the? X generator 65.

The ΦX generator 65 generates a signal ΦX having a boosted voltage level in response to the signal output from the predecoder 60. The output signal? X generated from the? X generator 65 is commonly input to the normal wordline driver circuit 70 and the redundant wordline driver circuit 75. Accordingly, each of the normal word line driver circuit 70 and the redundant word line driver circuits 75 may be configured to drive the normal memory cell array 90 and the redundant memory cell array 85 by the signal φDPXi and the output signal ΦX pre-decoded from the predecoder 60. The driving signals Xi and Xj are output, respectively. In this case, when the pre-decoded signal? DPXi is an address signal for designating a defective memory cell, the redundant word line driver circuit 75 outputs a? REDi signal as a logic " high ", which is input to the sense amplifier control circuit 80. The ΦREDi signal maintains a logic " low " state when an address specifying a normal word line is input, and transitions to a logic " high " state when an address signal specifying a redundant word line is input.

The sense amplifier control circuit 80 controls the first sense amplifier 95 and the second sense amplifier 100 by inputting the sense amplifier control signal Φ S input from the outside and the signal Φ REDi output from the redundant word line driver circuit 75 to indicate the redundant mode. The signal ΦLANGN or ΦLANGS is selectively outputted.

As shown in FIG. 5, the configuration of the sense amplifier control circuit 80 includes a NAND gate 105 for inputting the control signal? S and the signal? REDi to activate the sense amplifier control circuit 80, an inverter 100 for inverting the control signal? And an NOR gate 115 through which the inverted control signals? S and? REDi are input, and an inverter 120 for inverting the output signal of the NAND gate 105. The signal? REDi output from the redundant word line driver circuit 75 is activated in a logic " high " state when an address signal specifying a redundant word line is input. Thus, in the redundancy mode, the signal " REDi " in the logic " high " state is input to the NAND gate 106 and the NOR gate 115 of the sense amplifier control circuit 80. As a result, the signal? LANGN controlling the first sense amplifier 95 is activated in a logic "low" state, and the signal? LANGS controlling the second sense amplifier 100 is activated in a logic "high" state. By the above operation, the first sense amplifier 95 is deactivated, the second sense amplifier 100 is activated, and data output from a predetermined redundant memory cell of the redundant memory cell array is transmitted to the external output line through the second sense amplifier 100. do.

On the other hand, the output signal? REDi of the redundant word line driver circuit 75 is activated in a logic " low " state when an address signal specifying a normal word line is input. As a result, the signal? LANGN controlling the first sense amplifier 95 is activated in a logic "high" state, and the signal? LANGS controlling the second sense amplifier 100 is activated in a logic "low" state. By this operation, data output from a predetermined normal memory cell of the normal memory cell array is transferred to the external output line through the second sense amplifier 95.

That is, in the semiconductor memory device of FIG. 3 according to the present invention, in the normal mode and the redundant mode, the word line of the normal memory cell array 90 and the word line of the redundant memory cell array 85 are simultaneously selected and driven, and accordingly the first sense. In the amplifier 95 and the second sense amplifier 100, data read from the memory cells of the normal memory cell array 90 and the redundant memory cell array 85 are simultaneously loaded. However, in the redundant mode, since the data read out from the normal memory cell array 90 and input to the first sense amplifier 95 are abnormal data included in the defective cell, the sense amplifier control circuit 80 deactivates the first sense amplifier 95 and removes the first sense amplifier 95. 2 Sense amplifier 100 is activated, and the defective output data is output to the external output line. Also, in the normal mode, the sense amplifier control circuit 80 activates the first sense amplifier 95 and deactivates the second sense amplifier 100 so that the data of the normal memory cell array 90 is loaded on the external output line.

The control signal .phi.S for activating the sense amplifier control circuit 80 is supplied with a predetermined time delay to start the sensing operation of the sense amplifier control circuit 80 when the access operation of the memory cell array is completed. According to the present invention, a sense amplifier control circuit 80 for complementarily operating the first sense amplifier 95 and the second sense amplifier 100 is provided by combining the control signal .phi.S with the control signal .phi.REDi indicating whether the redundant mode is used. Accordingly, in the redundancy mode, the first sense amplifier 95 is deactivated as the control signal Φ REDi is activated with a logic “high” and the sense amplifier control signal Φ S is activated with a logic “high” after a predetermined time has elapsed. Sense amplifier 100 is activated. On the other hand, in the normal mode, after the control signal Φ REDi is activated to a logic "low" and a predetermined time has elapsed, as the sense amplifier control signal Φ S is activated to a logic "high", the first sense amplifier 95 is activated, and the second The sense amplifier 100 is deactivated.

In the semiconductor memory device according to the present invention, as the word line of the normal memory cell array and the word line of the redundant memory cell array are selected and driven at the same time, the redundant mode as in the semiconductor memory device of the related art shown in FIG. Alternatively, the time delay of selecting the normal mode is not necessary at all in the present invention.

As described above, the semiconductor memory device performing the redundancy operation according to the present invention activates the normal word line driving circuit and the redundant word line driving circuit at the same time, thereby increasing the data output speed and improving the operation speed of the semiconductor memory device. It is effective to let.

Claims (1)

A semiconductor memory device in which a defective memory cell located in a normal memory cell array is replaced with a redundant memory cell of a redundant memory cell array, wherein the normal memory circuit selects and drives a word line of the normal memory cell array in response to an externally input address signal. The defective memory cell address can be stored in the word line driving means and itself, and when the input external address signal is applied to designate the defective memory cell, it generates a control signal indicating a redundant mode and simultaneously generates the control signal. Redundant word line driving means for driving a word line of a redundant memory cell array, and a first sense amplifier connected to an output terminal of the normal memory cell array to sense and amplify data output from the normal memory cell and transmit the detected data to an external output line. Wow A second sense amplifier connected to an output terminal of the redundant memory cell array for sensing and amplifying data output from the redundant memory cell and transferring the data to an external output line, and a redundant mode control signal and sense output from the redundant word line driving means; Activate at least one of the first sense amplifier and the second sense amplifiers according to an input state of an amplifier control signal, and deactivate the first sense amplifier and simultaneously deactivate the second sense amplifier when the redundant mode control signal is activated; And a sense amplifier control circuit for activating an amplifier.