JPH056690A - Dual-port memory - Google Patents

Abstract

PURPOSE:To obtain a dual-port memory having SAM which ensuring high speed access and having redundant memory bits. CONSTITUTION:A serial selector 225 for selecting addresses of serial memory (SAM) 220 is formed by a shift register 2250. Moreover, a first read bus 224, a first amplifier 223, a second read bus 234 and a second amplifier 233 are provided in the successive stage of the serial memory array 220 and serial redundant memory array 230. Output of these first and second amplifiers is selected using a control signal phi by providing a switch circuit 214 as an output to an external terminal 203.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual port memory mainly used for image processing in recent years, and more particularly to a dual port memory having a high speed operation.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing the configuration of a general conventional dual port memory. In the figure, 1 is a dual port memory chip, 101, 102, 103.
RAM (random access memory), which is a first memory described later in the dual port memory chip 1, respectively.
An external clock terminal, an external address terminal, and an external data input / output terminal for operating
Is converted to (or from) the internal signal via the buffer of.

Reference numeral 120 is a first memory array consisting of a large number of memory cells, and 121 and 122 are row decoders for selecting rows and columns of the memory array 120, respectively.
It is a column decoder. Reference numeral 130 denotes a redundant memory array that improves the manufacturing yield by replacing the memory cells in the memory array 120 with itself when a defect occurs.
A decoder 32 selects the redundant memory 130 (only column redundancy is shown in the figure).

On the other hand, 201 and 203 are SAM which is a second memory described later in the dual port memory chip 1.
An external clock terminal and an external data input / output terminal for operating (serial access memory), which are converted into (or from) internal signals via buffers 211 and 213, respectively. 220 is a second memory array, the first
The memory array 120 has a number of memory cells equal to the number of memory cells for one row. Reference numeral 222 denotes a serial selector for selecting an address of the second memory array (SAM) 220, which shifts by one address according to the SC clock input to the external clock terminal 201. Further, 230 is the redundant memory array 13 of the first memory array 1.
Like 0, it is a serial redundant memory array for replacement when a defect occurs in the first memory array 220, and is selected by the serial redundant selector 232.

Next, the operation will be described. The first memory array (RAM) 120 is usually connected to a CPU (not shown), and information necessary for an image is written in the array 120. That is, necessary information is input from the external data input terminal 103 and converted into an internal signal via the buffer 113. This internal signal is connected to the bus 124 by the write buffer 123, and is written in a predetermined one cell in the memory array 120 by the output selected by the column decoder 122 and the row decoder 121.

As for the data written in the memory array 120 as described above, the transfer circuit 300 transfers the data for one row of the memory array 120 to the serial memory array 220 at a time. Transfer is external clock terminal 101
It is defined by the combination of the timings of the clock groups input to the input terminal, and is controlled by the output of the transfer control circuit 301.

The data transferred to the serial memory array 220 is shifted one bit at a time by the output of the selector 222 by the SC clock in the buffer 211, and the data is shifted bit by bit in the memory array 2.
20 Read out. The transfer start circuit 301 determines the read start at this time, and the column address at the time of transfer is sent as it is to the serial selector 222 as the read start address of the serial access memory 220.

The data read out to the outside of the memory array 220 as described above is input to the holding amplifier 223 through the read bus 244, amplified and held, and further to the external data input / output terminal 203 via the buffer 213 in the subsequent stage. Appearing, this serial output is connected to the display via the CRT controller and becomes the image information.

By using the dual port memory in this way, one memory port can be dedicated for writing and the other port can be dedicated for reading, so that image data can be obtained much faster than using a normal RAM. it can.

Next, the redundant memory array 13 for RAM is used.
The operation of the redundant memory array 230 for 0 and SAM will be described. Redundant memory arrays 130 and 230 are RAM
When a defect occurs in the array of 120 and SAM220 in manufacturing, a part of the defect is replaced.
Reference numeral 2 is a RAM redundant selection decoder, and 232 is a redundant serial selector. The above configuration will be described in detail with reference to FIG.
Reference numeral 1200 is a memory cell of the RAM 120 which is the first memory, 1210 is a word line for selecting a row, and 12 is a word line.
Reference numeral 20 is a bit line (/ bit line) for performing column selection. 300 is a transfer gate (data transfer circuit) between the RAM 120 and the SAM 220. By opening this gate, data transfer between the RAM 120 and the SAM 220 becomes possible. Reference numeral 2200 denotes a memory cell of the SAM 220, which receives a read address designation by the output of the serial selector 222 and transmits information to the read bus 224.

Further, 1300 is a column redundant memory cell of the redundant memory array 130 for the RAM 120, which is also connected to the redundant memory cell 2300 for the SAM 220 via the transfer gate 300. Reference numeral 400 is a fuse that determines whether the output of the serial selector selects the memory cell 2200 in the memory array 220 or does not select it due to a defect or the like. If the fuse 400 is not blown, the fuse of the serial selector is directly used. As the output, the memory cell 2200 is selected, and the written "1" or "0" information is connected to the read bus 224. Then, a small amount of read information appearing on the read bus 224 is amplified at high speed by the amplifier 223, and passes through the buffer 213 to the external data input / output terminal 20.
It reaches 3. Further, reference numeral 1201 denotes a defective memory cell of the memory cells forming the RAM 120. When such a defect occurs, this defective cell is transferred to the serial redundant memory 1300.
Replace with and use. This method is 256K (D) RAM
Since then, it has already been adopted and is one of the important means for improving the manufacturing yield.

By the way, the serial selector 222 shown in FIG. 3 usually has a decoder 1221 and a counter 12 as shown in FIG. 4, as is known from Japanese Patent Laid-Open No. 60-72020.
22 and 22. Further, ψ is an internal signal formed by converting the external SC signal, and serves as a trigger for the counter 1222. The output of the counter 1222, which counts up one by one by the internal signal ψ, is decoded by the serial decoder 1221 and the address of the SAM 220 is selected. When a defect occurs in the memory cell 2200 of the SAM 220, the redundant cell 23 of the serial redundant memory array 230
Replaced with 00. In this case, the serial decoder 122
The fuse 400 which is the output of No. 1 is blown, and conversely, the address to be replaced by using as a redundancy selection signal is predecoder 40.
If you program in 1 and the defective address is selected,
The redundant bit is selected via the redundant serial decoder 1231. As another example, there is a method of configuring the serial selector 222 with a shift register. In this case, the address is selected only by shifting 1 bit at a time, so the speed will be faster unlike a counter or decoder, but the shifting direction is determined to be 1 bit from left to right or from right to left. It is impossible to jump the selected address to the redundant bit at once by using the bit, and the redundant memory cannot be provided, which causes a production problem such as yield.

[0013]

Since the conventional dual port memory having a serial selector is constructed as described above, it is necessary to construct a selector using a counter and a decoder in order to have redundant bits. However, there is a problem that it is difficult to obtain a high-speed access operation as compared with a shift register.

The present invention has been made in order to solve the above problems, and provides a dual port memory which has a redundant bit and has a good productivity while performing high speed access using a serial selector of a shift register system. The purpose is to get.

[0015]

In a dual port memory according to the present invention, a selection circuit for selecting a second memory array is constructed by using a shift register, and
Read means is provided in each of the memory array and the redundant memory array for the second memory array, and the output of these two read means is switched and output by the output switching means.

[0016]

In the present invention, since the selection circuit for selecting the second memory array is composed of the shift register, high speed operation can be performed, and the second memory array and the second memory array Since the reading means is provided in each of the redundant memory arrays and these outputs are appropriately selected and output, the redundant memory array can be provided to repair the defect in the normal memory array.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a dual port memory according to an embodiment of the present invention, in which the same reference numerals as those in FIG. It is composed of a shift register in which ψ is a trigger.
234 is a second read bus, and 233 is a second read bus.
Of the serial redundant array 230, and is independently provided in the latter stage of the SAM 220 (first).
The output of the read bus 224 and the (first) amplifier 223 and the output of the second amplifier 233 are switched by the switching circuit 214 and output to the external data input / output terminal 203 via the buffer 231. .. And φ
Controls the switching circuit 213, and the normal cell (SAM2
20) of the read data from the group or redundant memory cells (of the serial redundant memory array 230)
Is a control signal for determining whether to output read data from the memory. In this case, the address replaced with the redundant memory cell is used as the control signal φ.

By the way, in the dual port memory, the RAM 120 and the SAM 2 are connected by the transfer gate 300.
Since the column addresses of 20 must match, when the defective cell 1201 is replaced with the redundant cell 1300, as shown in FIG. 2, even if there is no defect on the SAM memory cell side, the address corresponding to the defective cell 1201 can be obtained. Fuse 400
Is blown, and the SAM of the same column address as the defective cell 1201
The memory cell 2200 on the 220 side is also replaced with the serial redundant memory cell 2300.

The operation will be described below. In the above configuration, when reading the data transferred to the serial memory array 220, the memory cell 2200 in the SAM 220 is read.
Shifts by a shift register 2250, which constitutes the serial selector 225, sequentially in the fixed direction to the bus 24 bit by bit.
4 and is amplified and held by the subsequent amplifier 223.

On the other hand, the defective memory cell 12 of the RAM 120
Memory cell 130 of redundant memory array replaced with 01
The data of the memory cell 2300 of the serial redundant memory array to which 0 is transferred is not shifted by the shift register 225, and the data is directly transferred to the second read bus 2
The data is read out to 34, amplified and held by the amplifier 233 in the subsequent stage, and stands by in the switching circuit 214.

When the control signal φ indicating the address blown by the fuse 400 is input to the switching circuit 214, the read data from the serial redundant memory array 230 is output instead of the read data from the SAM 220. It will be. Redundant memory cells are not read using a shift register, but read in advance,
Since the data is amplified and held and the data is held by the switching circuit 213, the read speed does not become slower than that of other memory cells.

Next, an example of a circuit for obtaining the control signal φ will be described with reference to FIG. As shown in Fig. 5 (a), the external C
Using the internal CS signal equal to the phase of the S clock,
The plurality of FETs 500 having the gate inputs of the address signals A0 to An for selecting the address of 220 blow the desired fuse of the circuit connected in parallel to the node 600 via the fuse 401, thereby blowing the fuse 400. A control signal φ indicating the address is obtained. For example, if you want to replace it with address 5, fuse 4 of A0 and A3
By blowing 01, the node 600 holds the H level only at the address 5, and the NAND 700 in the output stage obtains the L level as the control signal φ only when the internal CS signal is active.

Further, as shown in FIG. 5B, the circuit shown in FIG. 5A is connected to the shift register 2250 of the serial selector 225 of FIG. The control signal φ may be used to obtain the control signal φ, which can be realized with a simpler configuration than that of the above-described embodiment.

As described above, according to this embodiment, the serial selector 225 for selecting the address of the serial memory (SAM) 220 is configured by using the shift register 2250, and the serial memory array 220 and the serial redundant memory array 230 are provided at the subsequent stage. Are provided with a first read bus 224, a first amplifier 223, and a second read bus 234 and a second amplifier 233, respectively, and the outputs of the first and second amplifiers are controlled by a switching circuit 214. Since the signal φ is used for selection and output to the external terminal 203, a redundant memory can be provided to improve the manufacturing yield, and data can be read at high speed to improve the access speed.

[0025]

As described above, according to the dual port memory of the present invention, since the selection circuit for selecting the second memory array is composed of the shift register, the access time can be improved. Further, since the reading means is provided in each of the second memory array and the redundant memory array for the second memory array and these outputs are appropriately selected and outputted, the redundant memory array is provided and the defect of the normal memory array is provided. Therefore, there is an effect that it is possible to obtain a device having a high manufacturing yield.

[Brief description of drawings]

FIG. 1 is a block diagram of a dual port memory according to an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram around a SAM of a dual-port memory according to an embodiment of the present invention.

FIG. 3 is a block diagram of a conventional dual-port memory.

FIG. 4 is a circuit configuration diagram around a SAM of a conventional dual-port memory.

FIG. 5 is a diagram showing an example of a circuit for generating a control signal of the switching circuit of the dual poe memory according to the embodiment of the present invention.

[Explanation of symbols]

1 dual port memory 101 RAM clock terminal 102 address terminal 103 RAM data input / output terminal 111 RAM clock buffer 112 address buffer 113 RAM data input / output buffer 120 RAM memory array 121 row decoder 122 column decoder 123 RAM read data Amplifying / holding / writing circuit 124 RAM read / write bus 130 RAM redundant memory array 132 RAM redundant column decoder 201 SAM clock terminal 203 SAM data input / output terminal 211 SAM clock buffer 213 SAM data input / output buffer 214 Switching circuit 220 SAM memory arrays 222 and 225 Serial selector 223 Serial reading amplification / holding circuit / writing circuit 224 Serial reading / Input bus 230 Serial redundant memory array 232 Serial redundant selector 300 Transfer circuit 301 Transfer signal generation circuit 400 Fuse 401 Predecoder 1200 RAM memory cell 1201 Defective RAM memory cell 1210 Word line 1220 Bit line 1300 RAM redundant memory cell 2200 SAM Memory cell 2220 Shift register 2300 SAM redundant memory cell

Claims (2)

[Claims] 1. A randomly accessible first memory array for storing input information from the outside, and a serially accessible second memory having the number of memory cells corresponding to one row of the first memory array. An array, a transfer unit for transferring one row of information of the first memory array to the second memory array, redundant memory arrays for the first and second memory arrays, and the second memory array. Selecting means comprising a shift register circuit for selecting memory cells of the memory array of 1 bit by 1 bit in accordance with an external input clock;
First reading means for reading information of the second memory array selected by the selecting means; second reading means for reading information of the redundant memory array for the second memory array; A dual port memory comprising: output switching means for selecting one of the outputs of the second reading means and outputting it to an external input / output terminal. 2. The output switching means receives an address signal of a cell of the first memory cell array replaced with the redundant memory array for the first memory cell array, and outputs the address signal when the signal is input. 2. The dual port memory according to claim 1, wherein the output of the second read means is selected and output instead of the output of the first read means.