KR100370952B1 - Sensing amplification circuit of memory cell - Google Patents

Abstract

PURPOSE: A sensing amplification circuit of a memory cell is provided to reduce the power consumption by performing a sensing operation through an NMOS(N-type Metal Oxide Semiconductor) sensing amplifier to transmit data to an input/output line without performing a pull-up sensing through a PMOS(P-type Metal Oxide Semiconductor) sensing amplifier. CONSTITUTION: Sensing amplifiers(11,12) sense data transmitted through bit lines(BL,BLB). NMOSs(NM5,NM6) transmit a signal sensed by the sensing amplifiers(11,12) to an input/output lines(IO,IOB) under the control of a wire selecting signal(YS). A power-saving-type driving signal output unit(31) supplies a voltage(1/2 Vcc) of a predetermined level as a sensing amplifier driving signal(PCS) when a read enable signal(RE) is driven. Input/output control units(32A,32B) are installed on the NMOSs(NM5,NM6) to discharge a precharge voltage of data to be outputted to the input/output lines(IO,IOB) at a grounding voltage level and transmit write data to the bit lines(BL,BLB) under the control of a write enable signal(WE).

Description

Memory Cell Sense Amplifier Circuit

The present invention relates to a technology for reducing the power consumption of the Sansamp when the read operation of the memory cell device, in particular, omitting the pull-up sensing by the PMOS sense amplifier, input and output data only by sensing by the NMOS sense amplifier A sense amplifier circuit of a memory cell adapted to be delivered to a line.

FIG. 1 is a schematic diagram illustrating a sense amplifier circuit of a general memory cell. Referring to FIG.

The data shown in the bit lines BL and BLS are transferred to the Sans 11 and 12 by the SHI signal, and the driving signals NCS and PCS of the sense amplifiers 11 and 12 are transmitted. Are supplied to the logic values "low" and "high", respectively, so that the weak data transferred from the bit lines BL and BLB are sensed as "high" or "low".

Thereafter, the Y-select signal YS is applied to " high " so that the sensed data of the bit lines BL and BLB is input / output lines IO and IOB through the NMOSs NH5 and NM5. Is passed on. At this time, the input / output lines IO and IOB are precharged with an initial voltage of 1/2 Vcc, and a voltage difference is generated by the data transferred from the sense amplifiers 11 and 12 to transfer data logic values. Done.

However, in the conventional sense amplifier circuit, when sensing data, both the sense amplifier of the NMOS and the sense amplifier of the PMOS are operated, so that the power consumption by the sensing operation is increased, and moreover, the Y-select signal is applied to the sense amplifier. When the two MOS transistors installed in the rear stage are opened, the 1/2 Vcc voltage precharged on the input / output line affects the sense amplifier, thereby reducing the voltage difference between the two bit lines, thereby degrading the sensing efficiency.

Accordingly, an object of the present invention is to provide a sense amplifier circuit for omitting pull-up sensing by the PMOS sense amplifier and transmitting the data to the input / output lines only by sensing by the NMOS sense amplifier.

3 is a sense amplifier circuit diagram of a memory cell of the present invention for achieving the above object, as shown therein, sense amplifiers 11 and 12 for sensing data transmitted through bit lines BL and BLB. And a memory comprising NMOS NM5 and NM6, which transmits the signals sensed by the sense amplifiers 11 and 12 to the input / output lines IO and IOB under the control of the Y select signal YS. In the sense amplifier circuit, the power-saving drive signal output unit 31 for supplying a voltage (1/2 Vcc) of a predetermined level as the sense amplifier drive signal PCS when the lead enable signal RE is driven, and It is provided on the NMOS NM5 and NM6 sides, and discharges the precharge voltage of the data output to the input / output lines IOB and IOB to the ground voltage level and under the control of the write enable signal WE. The input / output control unit 32A, 32B, which transmits the write data to the bit lines BL and BLB sides, constitutes the above. When described in detail with reference to Figure 4 attached to the operation and effects of the present invention.

The weak data shown in the bit lines BL and BLB is transmitted to the sans amplifiers 11 and 12 through the NMOSs NM1 and NM1, respectively, when the SHT signal becomes “high”.

In the read operation, the lead enable signal RE becomes " high " and the write enable signal WE becomes " low ", wherein the lead enable signal RE is " connected " Is inverted to " low " and supplied to the gate of PMOS PM21, thereby turning PMOS PM21 on.

Accordingly, the 1/2 Vcc voltage is supplied to the sense amplifier driving signal PCS through the PMOS PM21, so that the sense amplifier driving signal PCS is maintained at the 1/2 Vcs voltage. In this case, the NMOSs 23 and NM24 are turned on by the read enable signal RE to prepare for transferring data to the input / output lines IO and IOB. At the same time, the NMOS NM25 and NM26 are turned off by the light enable signal WE supplied to " low " to block the light path.

In this state, the driving signal NCS of the sense amplifier 11 is supplied as "low" and pull-down sensing of the weak data transmitted by the bit lines BL and BLB is performed, as shown in FIG. The data of the bit lines BL and BLB are spread with 1/2 Vcc and the "low" voltage.

After that, when the wire selection signal YS is supplied to " high ", the wire selection NMOSs NM5 and NM6 are turned on, so that the data whose level is increased in the bit lines BLB and BLB is turned on. The MOSs NM6 and NM5 are transferred to the gates of the NMOS NM22 and the NMOS NM21, respectively, so that they are selectively driven.

The precharge voltage (1/2 Vcc) of the input / output line IO or the input / output line IOB is discharged to the ground voltage Vss level by driving the NMOS 21 or the NMOS 22 NM21. The corresponding data of is passed.

In the write operation, the NMOS 25 and NM26 are turned on by the write enable signal WE to directly transmit data to the bit lines BL and BLB. The driving signals NCS and PCS of 12 are applied together to perform both pull-up and pull-down sensing. At this time, the NMOSs NM23 and NM24 are both turned off by the lead enable signal RE input as " low " so that the read path of the data is blocked.

As described in detail above, the present invention omits the pull-up sensing by the PMOS sense amplifier during the data read operation, and transfers the data to the input / output line only by the pull-down sensing by the NMOS sense amplifier, thereby reducing the power consumption by the sensor amplifier. Is reduced to 1/2, and since the precharge voltage (1/2 Vcc) of the input / output line does not affect the sensing operation by managing the bit line and the input / output line separately, the sensing efficiency is improved. .

1 is a sense amplifier circuit diagram of a typical memory cell.

2 is a timing diagram of each control signal operation applied to each part of FIG. 1;

3 is a sense amplifier circuit diagram of a memory cell of the present invention.

4 is a timing diagram of an operation of each control signal applied to each part of FIG. 3;

*** Explanation of symbols for main parts of drawing ***

11, 12: sense amplifier 31: drive signal output unit

32A, 32B: I / O control unit

Claims (1)

The sense amplifiers 11 and 12 sensing data transmitted through the bit lines BL and BLB, and the signals sensed by the sense amplifiers 11 and 12 control the Y select signal YS. In a sense amplifier circuit of a memory composed of NMOS NM5 and NM6, which are transferred to the input / output lines IO and IOB, the voltage of a predetermined level when the read enable signal RE is driven. A power saving driving signal output unit 31 for supplying 2 Vcc as a sense amplifier driving signal PCS; The precharge voltages of the data which are respectively provided on the NMOS NM5 and NM6 sides and output to the input / output lines IOB and IOB are discharged to the ground voltage level, and the write enable signal WE is controlled. And a input / output control unit (32A) and (32B) for transferring write data to the bit lines (BL) and (BLB) side, respectively.