KR100262666B1 - Semiconductor memory device for controlling sense amplifier - Google Patents

Abstract

PURPOSE: A semiconductor memory device for controlling a sense amplifier is provided to generate a sense amplifier control signal by receiving back the output of the sense amplifier and to precharge the positive and negative output lines of the sense amplifier in order to control the enabling and disabling of the sense amplifier accurately. CONSTITUTION: The semiconductor memory device for controlling the sense amplifier includes the sense amplifier, a precharger and a sense amplifier control signal generator. The sense amplifier is enabled and disabled by the sense amplifier control signal(SEi). The precharger precharges the positive and negative output lines of the sense amplifier with a source voltage all the time. The sense amplifier control signal generator receives back the positive output signal and the negative output signal of the sense amplifier and generates the sense amplifier control signal of inactive state when the positive output signal and the negative output signal have different logic levels. The precharger is turned on all the time to provide the source voltage to the positive and negative output lines of the sense amplifier.

Description

Semiconductor memory device for controlling sense amplifier

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier and a control circuit for sensing, amplifying and outputting data in a memory cell in a semiconductor memory device. In particular, the present invention relates to a semiconductor for accurately controlling enable and disable of a sense amplifier without malfunction. Relates to a memory device.

As is well known, a sense amplifier is used to sense and amplify data of a memory cell loaded on a bit line (data bus) during a read operation of a memory device. You must enable and disable it accordingly. To this end, a separate control signal is generated to control the sense amplifier as the signal.

1 illustrates an example of a conventional sense amplifier, in which a positive signal (DB) and a negative signal (/ DB) from a data bus are input and amplified, respectively, and then a positive output (SAOUT) and a negative output (/ SAOUT), respectively Two sense amplifier stages are output, and each sense amplifier stage is enabled and disabled by transistors 20a and 20b receiving the sense amplifier control signal SEi.

As described above, in order to control the driving of the sense amplifier, a sense amplifier control signal SEi is required, and the control signal SEi is generated in the chip by combining signals input to the chip.

2A and 2B show a conventional control circuit for generating the control signal SEi. First, FIG. 2A is generated by a clock CLOCK used as a control signal in a synchronous memory device. The pulse width of the EQ signal, which is a one-shot pulse, is arbitrarily widened (defined by the user) to represent a logic circuit section for generating a / gSE signal, which combines an inverter and a NAND gate. Is implemented by a conventional delay circuit design.

2B shows a final enable of controlling the sense amplifier by combining the / gSE signal, the write enable signal / WE, and the block select signal BLki of the sense amplifier for selecting the sense amplifier block. The logic circuit section for generating the signal SEi is shown.

As shown in Figs. 2A and 2B, when the logic circuit unit is configured, in the write state (that is, / WE = Low), the SEi signal becomes 'Low' to disable the sense amplifier and read state (/ WE = High), the BLki signal is 'High', so the SEi signal becomes 'High' only while the / gSE signal is 'Low' signal, enabling the sense amplifier.

However, since the SEi pulse width is determined by the n inverter delays in the logic circuit of FIG. 2A, which is a logic circuit for generating the / gSE signal, the SEi signal may be disabled before the sense amplification operation is completed. As a result, the sense amplifiers may be malfunctioning.

It is an object of the present invention to provide a semiconductor memory device for accurately controlling the enable and disable of a sense amplifier without malfunction.

1 is an exemplary view of a conventional sense amplifier,

2A and 2B are logic circuit diagrams showing a conventional sense amplifier control circuit.

3 is a sense amplifier circuit diagram according to a preferred embodiment of the present invention;

4 is a control signal generation circuit diagram according to the present embodiment.

In order to achieve the above object, the present invention, a sense amplifier is enabled and disabled by a control signal; Precharge means for always precharging the positive output terminal and the sub output terminal of the sense amplifier to the same logic level; And control signal generating means for receiving the positive output signal and the negative output signal of the sense amplifier and generating the control signal in an inactive state when the positive output signal and the sub output signal have different logic levels.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3 and 4.

The technical feature of the present invention is that instead of using a one-shot pulse EQ signal that provides a cause of the malfunction of the sense amplifier and a delay circuit (Fig. 2A) for increasing its pulse width, the output of the sense amplifier is The feedback signal is generated to generate a sense amplifier control signal, and for this purpose, the constant output line and the sub output line of the sense amplifier are always precharged.

That is, the sense amplifier is connected to a precharge circuit which always precharges its positive output and sub output lines, and the sense amplifier control signal generation circuit feeds back the positive output and the negative output signals of the sense amplifier and receives the positive output and negative output lines. When the output signal has a different logic level, the control signal is generated to disable the sense amplifier.

In other words, since the positive output signal and the negative output signal of the sense amplifier have different logic levels, it means that the output signal of the pre-charged sense amplifier has completed the detection and amplification of the input data. Deactivating (SEi) disables the operation of the sense amplifier.

Fig. 3 shows a sense amplifier according to the present embodiment, in which the PMOS transistors 10a and 10b which always supply the supply voltage to the positive output and the sub output lines SAOUT and / SAOUT of each sense amplifier stage are connected to each other. It can be seen that each output line is always precharged.

FIG. 4 is a control signal generation circuit diagram according to the present embodiment, and receives the positive output (SAOUT) and the negative output (/ SAOUT) of the sense amplifier stage as shown in FIG. 3 and uses the feedback as an input. A three-input NAND gate NAND1 that receives the / sub output SAOUT and / SAOUT signals and a sense amplification block selection signal BLKI from the outside, and an inverter INV1 that inverts the output of the NAND gate NAND1, NAND gate NAND2 receiving the output of the inverter INV1 and the write enable signal / WE, and an inverter INV2 inverting the output of the NAND gate NAND2 to output a sense amplifier control signal SEi. It consists of.

With this configuration, if either of the positive / negative outputs SAOUT and / SAOUT of the sense amplifier stage falls to 'Low', the output of the NAND gate NAND1 is set to 'Low' by the operation of the NAND gate NAND1. It changes to 'High', which means that sensing is completed, so that the control signal SEi is inactivated so that the sense amplifier is disabled.

The present invention accurately controls the enable and disable of the sense amplifiers without malfunction, and improves the reliability of the memory device.

Claims (3)

A sense amplifier in which enable and disable are controlled by a sense amplifier control signal, Precharge means for always precharging the positive output terminal and the negative output terminal of the sense amplifier to a supply voltage; Sense amplifier control signal generating means for receiving the positive output signal and the negative output signal of the sense amplifier and generating the sense amplifier control signal in an inactive state when the positive output signal and the sub output signal have different logic levels. A semiconductor memory device having a. The method of claim 1, And the precharge means is always turned on and comprises a transistor for supplying a supply voltage to the positive output terminal and the sub output terminal of the sense amplifier. The method according to claim 1 or 2, The sense amplifier control signal generating means, An input first NAND gate configured to receive a positive output signal, a negative output signal, and a block selection signal from the outside of the sense amplifier; A first inverter for inverting the output of the first NAND gate; A second NAND gate configured to receive an output of the first inverter and a write enable signal from the outside; And A second inverter for inverting the output of the second NAND gate and outputting the sense amplifier control signal And a semiconductor memory device.

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