JPH0329195A - Sense amplifier circuit - Google Patents

Abstract

PURPOSE:To obtain a sense amplifier circuit for a ternary semiconductor memory by providing the sense amplifier circuit with a specific circuit capable of reading out ternary information from two digit lines of a memory cell. CONSTITUTION:The sense amplifier circuit is provided with power supplies VDD, 1/2VDD, memory cell digit lines D, the inverse of D, 1st to 5th p-channel MOS transistors(TRs) 5, 6, 9 to 11, and 1st to 5th n-channel MOS TRs 7, 8, 12 to 14. The 3rd to 5th MOS TRs 9 to 11 and the 3rd to 5th MOS TRs 12, 13 are arranged and connected as shown in a diagram. Consequently, the sense amplifier circuit capable of reading out three ternaries from two digit lines D, the inverse of D of the memory cell can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sense amplifier circuit for a ternary semiconductor memory.

[Prior Art] Conventionally, since semiconductor memories have been of a binary type, sense amplifiers have also been of a binary type (mirror type etc. are common).

FIGS. 2(a) and 2(b) are a circuit diagram of a conventional general mirror type sense amplifier and a time chart of data reading timing. In this sense amplifier, the digit line D of the memory cell is "high" rVDDJ, and the digit line U is "low" r
At the time of OJ, “high゜’ rVDD is applied to the output terminal OUT.
J is output, and digit jJD is “low゜” ro
”．． When D is “high” or VDDJ, the output terminal OUT
“Low” “0” is output.

In the figure, VDD is a power supply, 5 and 6 are P-channel MOS transistors, and 7 and 8 are N-channel MOS transistors.

[Problems to be Solved by the Invention] Since the above-mentioned binary sense amplifier is exclusively used for binary semiconductor memories, 6 cannot be used for ternary semiconductor memories.

Therefore, it is necessary to develop a sense amplifier dedicated to three values for three-value semiconductor memory.

The present invention was made in view of the above-mentioned conventional requirements, and an object of the present invention is to provide a sense amplifier circuit for a ternary semiconductor memory.

[Differences between the present invention and the prior art] The present invention differs from the conventional binary-only sense amplifier described above in that ternary information can be read from two digit lines of a memory cell.

[Means for Solving the Problems] A sense amplifier circuit of the present invention includes first to fifth P-channel MOS transistors and first to fifth N-channel MOS transistors.
A sense amplifier circuit having an S transistor and reading three-value information from a three-value semiconductor memory, wherein a first P-channel MOS transistor has a drain connected to an output terminal and a gate connected to the gate and drain of a second P-channel MOS transistor. The source of the second P-channel MOS transistor is connected to the VDD power supply, and the drain and gate of the second P-channel MOS transistor are connected to the gate of the first P-channel MOS transistor, and the source is connected to the VDD power supply.
The third P-channel MOS transistor has its drain connected to the 1/2 VDD power supply, its gate connected to the drain of the fifth P-channel MOS transistor, and its source connected to the sources of the first and second N-channel MOS transistors. , the fourth P-channel MOS transistor has its drain connected to the source of the fifth P-channel MOS transistor, its gate connected to one input terminal, and its source connected to the VDD power supply terminal, and the fifth P-channel MOS transistor has its drain connected to the fourth and The gate is connected to the drain of the 50th N-channel MOS transistor, and the source is connected to the other input terminal of the 4th P-channel MOS transistor.
The first N-channel MOS transistor has its drain connected to the output terminal, its gate connected to the first input terminal, its source connected to the source of the third P-channel MOS transistor, and the second N-channel MOS transistor connected to the drain of the S transistor. The transistor has a drain connected to the gate and drain of the second P-channel MOS transistor, a gate connected to the other input terminal, and a source connected to the source of the third P-channel MOS transistor, and the third N-channel MOS transistor outputs the drain. Connect the gate to the terminal of the fifth P-channel MO
The drain and source of the S transistor are connected to ground, and the drain of the fourth N-channel MOS transistor is connected to the fifth P-channel M. The drain and gate of the OS transistor are connected to the first input terminal and the source is connected to ground, and the drain of the 50th N-channel MOS transistor is connected to the fifth PMOS transistor.
The channel MOS transistor is characterized in that its drain and gate are connected to the other input terminal, and its source is connected to ground.

[Embodiment] FIG. 1(a) is a circuit diagram of a sense amplifier circuit according to an embodiment of the present invention, and FIG. 1(b) is a time chart of data reading timing.

In the figure, VDD and 1/2VDD are the power supply, D and U are the digit lines of the memory cell, OUT is the output of the sense amplifier read from the digit lines D and U, 5, 6, 9 to 11 are P channel MOS transistors, 7, 8. 12
.about.14 are N-channel MOS transistors. Also,
Digit lines D and U can have three states as shown in the table below.

(Hereinafter, blank spaces) The operation of this embodiment will be explained according to the time chart of FIG. 1(b).

Now, if you try to read signals from digit lines D and U and open the word line of a memory cell at a certain address after precharging the digit lines, both digit lines D and H will be "low" rOJ. At times, the P-channel MOS transistors 10 and 11 are turned on, and the gate of the N-channel MOS transistor l2 is set to "high".
D" is supplied. As a result, the transistor l2 is turned on and a "low" rOJ is output to the output terminal OUT.

Similarly, when the word line of another address is opened, when the digit line D is at 1/2 VDD and the digit line D is at VDD, the N-channel MOS transistor 13 is turned on and a "low" rQJ is supplied to the gate of the P-channel transistor 9. and transistor 9 is turned on. At the same time, the N-channel MOS transistor 7 is also turned on, and the output terminal OUT is 1/1.
2VDD is output. Also, digit line D is VDD
, D are 1/2 VDD, P channel MOS transistors 9, 5 and N channel MOS transistor 8 are similarly turned on, and VDD is output to the output terminal OUT.

[Effects of the Invention] As explained above, according to the present invention, it is possible to realize a sense amplifier circuit that can read and output three values from a three-value memory cell.

[Brief explanation of drawings]

FIG. 1(a) is a circuit diagram of a sense amplifier circuit according to an embodiment of the present invention, FIG. 1(b) is a time chart explaining its operation, and FIG. 2(a) is a conventional mirror type binary circuit. The circuit diagram of the sense amplifier, FIG. 2(b), is a time chart explaining its operation. VDD, 1/2VDD...◆...Power supply, D...
...Memory cell digit line (other input terminal), F...Memory cell digit line (first input terminal), OUT...Output terminal, 5... first P-channel MOS transistor, 6.
...Second P-channel MOS transistor, 9...
- Third P-channel MOS transistor, 10... Fourth P-channel MOS transistor, 11... Fifth P-channel MOS transistor, 7... First N-channel MOS transistor, 8...・Second N-channel MOS transistor, 12...Third N-channel M
OS transistor, 13...40th N-channel MOS
Transistor, 14...50th N-channel MOS transistor.

Claims (1)

[Claims] A sense amplifier circuit having first to fifth P-channel MOS transistors and first to fifth N-channel MOS transistors and reading three-value information from a three-value semiconductor memory, the first P-channel MOS transistor connects the drain to the output terminal and the gate to the second P-channel MOS
Connect the source to the gate and drain of the transistor to VDD
The second P-channel MOS transistor has its drain and gate connected to the gate of the first P-channel MOS transistor and its source to the VDD power supply, and the third P-channel MOS transistor has its drain connected to the 1/2 VDD power supply. The gate is connected to the drain of the fifth P-channel MOS transistor, the source is connected to the sources of the first and second N-channel MOS transistors, and the fourth P-channel MOS transistor
The drain of the transistor is connected to the source of the fifth P-channel MOS transistor, the gate is connected to the first input terminal, and the source is connected to V
The fifth P-channel MOS transistor is connected to the DD power supply terminal, and the drain of the fifth P-channel MOS transistor is connected to the fourth and fifth N-channel MOS transistors.
The drain of the transistor is connected to the gate, the gate is connected to the other input terminal, and the source is connected to the drain of the fourth P-channel MOS transistor, and the drain of the first N-channel MOS transistor is connected to the output terminal, the gate is connected to the first input terminal, and the source is connected to the first input terminal. Connected to the source of P-channel MOS transistor No. 3,
The second N-channel MOS transistor has a drain connected to the second N-channel MOS transistor.
The gate and drain of the P-channel MOS transistor are connected to the other input terminal, and the source is connected to the source of the third P-channel MOS transistor, and the third N-channel MOS transistor has its drain connected to the output terminal and its gate connected to the fifth The drain and source of a fourth N-channel MOS transistor are connected to ground, the drain of a fourth N-channel MOS transistor is connected to the drain of a fifth P-channel MOS transistor, the gate is connected to the first input terminal, and the source is connected to ground, A sense amplifier circuit characterized in that the fifth N-channel MOS transistor has a drain connected to the drain of the fifth P-channel MOS transistor, a gate connected to the other input terminal, and a source connected to ground.