KR970051135A - Sense Amplifier Circuit in Memory Cells - Google Patents

Sense Amplifier Circuit in Memory Cells Download PDF

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Publication number
KR970051135A
KR970051135A KR1019950070192A KR19950070192A KR970051135A KR 970051135 A KR970051135 A KR 970051135A KR 1019950070192 A KR1019950070192 A KR 1019950070192A KR 19950070192 A KR19950070192 A KR 19950070192A KR 970051135 A KR970051135 A KR 970051135A
Authority
KR
South Korea
Prior art keywords
sense amplifier
sensing
output
nmos
driving signal
Prior art date
Application number
KR1019950070192A
Other languages
Korean (ko)
Other versions
KR100370952B1 (en
Inventor
김동균
Original Assignee
문정환
Lg 반도체 주식회사
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Publication date
Application filed by 문정환, Lg 반도체 주식회사 filed Critical 문정환
Priority to KR1019950070192A priority Critical patent/KR100370952B1/en
Publication of KR970051135A publication Critical patent/KR970051135A/en
Application granted granted Critical
Publication of KR100370952B1 publication Critical patent/KR100370952B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Abstract

본 발명은 메모리 셀 소자의 리드(Read) 동작시 센스앰프의 전력소모를 저감하는 기술에 관한 것으로, 리드 사이클에서 절전을 도모하고, 센싱효율을 향상시키기 위하여, 리드동작시 피모스 센스앰프 구동신호인 PCS를 1/2 Vcc 전압으로 유지하여 피모스 센스앰프에 의한 플업센싱을 생략하고, 엔모스 센스앰프 구동신호인 NCS를 “로우”로 인가하여 엔모스 센스엠프에 의해서만 센싱이 이루어지도록 하고, 입출력라인과 비트라인을 별도로 관리하여 입출력랑니의 프리챠지전압에 의해 센싱동작이 영향을 받지 않도록 하였다.The present invention relates to a technique for reducing power consumption of a sense amplifier during a read operation of a memory cell device. In order to save power in a read cycle and improve sensing efficiency, a PMOS sense amplifier driving signal during a read operation is provided. Maintains PCS at 1/2 Vcc to omit the up-sense sensing by the PMOS sense amplifier, apply NCS as the NMOS sense amplifier driving signal to "low" so that sensing is performed only by the NMOS sense amplifier, I / O lines and bit lines were managed separately so that the sensing operation was not affected by the precharge voltage of the I / O teeth.

Description

메모리 셀의 센스앰프 회로Sense Amplifier Circuit in Memory Cells

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명 메모리 셀의 센스앰프 회로도.3 is a sense amplifier circuit diagram of a memory cell of the present invention.

Claims (1)

비트라인(BL), (BLB)을 통해 전달하는 데이타 센싱하는 센스앰프(11), (12)와, 상기 센스앰프(11), (12)에서 센싱된 신호를 와이선택신호(YS)의 제어하에 입출력라인(IO),(IOB)측으로 전달하는 엔모스(NM5), (NM6)로 구성된 메모리의 센스앰프회로에 있어서, 리드인에이블신호(RE)가 구동될 때, 소정레벨의 전압(1/2Vcc)을 센스앰프 구동신호(PCS)로 공급하는 절전형 구동신호 출력부(31)와; 상기 엔모스(NM5), (NM6)측에 각기 설치되어 입출력라인(IO), (IOB)으로 출력되는 데이타의 프리챠지전압을 접지전압 레벨로 디스챠지시키고, 라이트인에이블신호(WE)의 제어하에 라이트데이타를 비트라인(BL), (BLB)측으로 전달하는 입출력제어부(32A), (32B)를 포함하여 구성한 것을 특징으로 하는 메모리 셀의 센스앰프 회로.The sense signals 11 and 12 for sensing data transmitted through the bit lines BL and BLB, and the signals sensed by the sense amplifiers 11 and 12 are controlled by the Y-select signal YS. In the sense amplifier circuit of the memory consisting of NMOS NM5 and NM6, which are transmitted to the input / output lines IO and IOB, the voltage of the predetermined level when the read enable signal RE is driven is lower. A power saving driving signal output unit 31 for supplying / 2Vcc as a sense amplifier driving signal PCS; The precharge voltages of the data which are respectively provided on the NMOS NM5 and NM6 sides and output to the input / output lines IOB and IOB are discharged to the ground voltage level, and the write enable signal WE is controlled. And a input / output control unit (32A) and (32B) for transmitting write data to the bit lines (BL) and (BLB) side, respectively. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950070192A 1995-12-31 1995-12-31 Sensing amplification circuit of memory cell KR100370952B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950070192A KR100370952B1 (en) 1995-12-31 1995-12-31 Sensing amplification circuit of memory cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950070192A KR100370952B1 (en) 1995-12-31 1995-12-31 Sensing amplification circuit of memory cell

Publications (2)

Publication Number Publication Date
KR970051135A true KR970051135A (en) 1997-07-29
KR100370952B1 KR100370952B1 (en) 2003-03-28

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950070192A KR100370952B1 (en) 1995-12-31 1995-12-31 Sensing amplification circuit of memory cell

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KR (1) KR100370952B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102339637B (en) * 2011-06-01 2014-07-23 北京大学 Condition-precharged sense-amplifier-based flip flop

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH081756B2 (en) * 1989-06-26 1996-01-10 日本電気株式会社 Sense amplifier circuit
KR940007751Y1 (en) * 1989-12-20 1994-10-24 금성일렉트론 주식회사 Circuit for sensing data of memory chip
JPH0474383A (en) * 1990-07-13 1992-03-09 Nec Ic Microcomput Syst Ltd Semiconductor memory
KR940007639B1 (en) * 1991-07-23 1994-08-22 삼성전자 주식회사 Data transmitting circuit having divided input/output line
KR960000892B1 (en) * 1992-12-01 1996-01-13 삼성전자주식회사 Data transmitting circuit
KR0155916B1 (en) * 1995-10-31 1998-12-01 김광호 Semiconductor memory device

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Publication number Publication date
KR100370952B1 (en) 2003-03-28

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