KR940007751Y1 - Circuit for sensing data of memory chip - Google Patents

Abstract

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Description

Data sensing circuit of memory device

1 is a conventional data sensing circuit diagram.

2 is a timing diagram in FIG.

3 is a data sensing circuit diagram according to the present invention.

4 is a timing diagram in FIG.

* Explanation of symbols for main parts of the drawings

A: memory element P1-P3: PMOS transistor

M1-M5: NMOS transistor SEP, SEN: Detection signal

The present invention relates to a data sensing circuit of a memory device, and more particularly, to a data sensing circuit of a memory device configured to shorten a sensing time by changing a precharge state.

In the conventional data sensing circuit, as shown in FIG. 1, a power supply voltage VDD is applied to a drain of a PMOS transistor P1 to which a sensing signal SEP is applied to a gate, and a source is a PMOS transistor. Sources of the NMOS transistors M2 and M3 connected to the drains of the P2 and P3 and connected in series to the PMOS transistors P2 and P3 are connected to the drains of the NMOS transistor M4 and the sensing signal. The source of the NMOS transistor M4 to which SEN is applied to the gate is ground VSS, and the bit line BIT connected to the source of the PMOS transistor P2 connected to the drain and the drain of the NMOS transistor M2 is connected to each other. The line BL is connected to the gates of the PMOS transistor P3 and the NMOS transistor M3, and is connected to the drain of the NMOS transistor M1 and the word line WL is connected to the gate. The source of M1 passes through the condenser C1. The data stored in the memory device A is connected to the source of the PMOS transistor P3 and the gate of the NMOS transistor P2 and the NMOS transistor M2 which are connected to each other. When the voltage rises to a high voltage, it flows out to the bit line BL, and senses and amplifies the voltage difference between the voltage of the bit line BL and the bit bar line ("/" indicates "bar") by the sense amplifier. .

Herein, the time Δt required for detection is as follows.

ΔQ = ΔV × C = I × Δt... … … … … … … … … … … … … … … … … … … … (One)

(Where c is the capacitance of the bit line and I is the current)

In equation (1), ΔV is (1 / 2Vcc-OV) = 1 / 2Vcc, so △ V becomes 2.5 (V) at 5 (V) power supply and the time required for detection (△ t) is △ t = △ VXC / I… … (2).

In other words, the data stored in the memory device A with the word line WL in a high voltage state with the bit line BL, the bit bar line / BL, and the connection point (l, m) previously made Vcc / 2. High is stored, for example) is distributed to the bit line BL so that the voltage of the bit line BL is different from the voltage of the bit bar line / BL. At this time, when the sensing signal SEN rises from the low state to the high state and the voltage of the point speed point m is lower than the bit voltage (/ BL) by more than the threshold voltage (Vt), the voltage of the bit line (/ BL) is sense amplifier. Begin to lower.

After that, when the detection signal SEP is changed to a high voltage state, the connection point voltage becomes higher than the bit line BL voltage, and the bit line BL voltage rises to a high voltage state to enable the detection of stored data.

However, in such a conventional technology configuration, in order to increase the sensitivity, the connection point (L, m) is sensed at a state of 1/2 Vcc (= 2.5 (V)). It takes a lot of), and only the voltage detection by the detection signal (SEN) is operated first, there is a disadvantage that can not be used to improve the detection speed according to the voltage rise by the PMOS (P MOS).

In order to improve the above-mentioned disadvantages, the present invention connects the source and the bulk BULK between the connection point l and the connection point m in the conventional data sensing circuit as shown in FIG. Connect the transistor M5 that excludes the effect of the back bias voltage at VT, and apply 1 / 2Vcc to the transistor M5 at the gate to pre-voltage the voltage between the two connection points (l, m). By adjusting, the detection speed is increased.

That is, in the present invention, the two inputs are connected to the bit line and the bit bar line, and are connected between the two terminals on the power supply side through the switching transistors P1 and M4 which are turned on and off by the enable signal, so that the voltage of the bit line and the bit bar line is reduced. A data detection circuit of a memory device having a sense amplifier for detecting a difference, and the source and drain of a MOS transistor (M5) in which a source and a bulk are connected between both connection points (ℓ, m) supplying a bit line sense amplifier. Each of them is connected to each other, and 1 / 2VCC is applied to the gate of the MOS transistor M5, thereby increasing the detection speed of the voltage difference between the bit line and the bit bar line.

Referring to the accompanying drawings, the specific technical configuration of the present invention will be described in detail the operating state and effect.

In FIG. 3, the voltage at the connection point l is Vcc (= 5 (V)) and the voltage at the connection point m is 0 (V).

At this time, if 1 / 2Vcc (= 2.5 (V)) is applied to the gate of transistor M5, the connection point m is lowered by the threshold voltage (VT = 1 (V)) from 2.5 (V) to 1.5 (V). The connection point 1 is increased by the threshold voltage to about 3.5 (V).

After that, the data stored in the memory device is caused to flow out to the bit line BL by the word line WL so that a difference between the voltage of the bit line BL and the voltage of the bit bar line / BL occurs, and at the same time, the voltage of the connection point ℓ. By setting the voltage higher than the threshold voltage and lowering the voltage at the connection point m below the threshold voltage, the voltage of the sense amplifier composed of PMOS (P1-P3) and NMOS (M2-M4) can be simultaneously pulled up and pulled up. Therefore, the amplification rate is increased to shorten the detection time.

Here, the gate-to-source voltage VGS of the NMOS transistors M2 and M3 is connected by connecting the source and the bulk of the transistor M5 to make the threshold voltage THRESHOLD VOLTAGE lower than the threshold voltages of the NMOS transistors M2 and M3. Since the threshold voltage VT is smaller than that, the transistors M2 and M3 are turned on to prevent the potential of the bit lines BL and the bit bars / BL from being lowered.

Therefore, in the data sensing circuit of the memory device according to the present invention, as shown in equation (2), the connection point (L) (m) is approximately 3.5 (V) and 1.5 (V), so that 3.5 (V) is 5 (V). As the rising voltage change and the voltage change amount that the 1.5 V is lowered to 0 (V) are 1.5 (V), the sensing speed is 1.7 times faster than the conventional sensing circuit having the change amount of 2.5 (V), and the transistor M5 By eliminating the back bias effect by connecting the source and the bulk of), the threshold voltage of the transistor M5 is lower than the threshold voltage of the sensing amplifier, thereby making it possible to detect data without mistakes.

Claims (1)

The two inputs are connected to the bit line and the bit bar line, and are connected between the two terminals on the power supply side through switching transistors P1 and M1 that are turned on and off by an in-ave signal, so as to sense a voltage difference between the bit line and the bit bar line. In a data sensing circuit of a memory device having an amplifier, a source and a drain of a MOS transistor M5 connecting a source and a bulk are respectively connected between two connection points (l, m) for supplying power to the bit line sense amplifier. And 1 / 2VCC is applied to the gate of the MOS transistor (M5), thereby increasing the detection speed of the voltage difference between the bit line and the bit bar line.