KR100367396B1 - Gate electrode formation method of flash memory device - Google Patents
Gate electrode formation method of flash memory device Download PDFInfo
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- KR100367396B1 KR100367396B1 KR10-1998-0062489A KR19980062489A KR100367396B1 KR 100367396 B1 KR100367396 B1 KR 100367396B1 KR 19980062489 A KR19980062489 A KR 19980062489A KR 100367396 B1 KR100367396 B1 KR 100367396B1
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 230000015572 biosynthetic process Effects 0.000 title abstract description 4
- 238000010438 heat treatment Methods 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 10
- 230000008021 deposition Effects 0.000 claims abstract description 8
- 239000007789 gas Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 10
- 238000009413 insulation Methods 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 238000010926 purge Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 238000007664 blowing Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 14
- 230000003647 oxidation Effects 0.000 abstract description 9
- 238000007254 oxidation reaction Methods 0.000 abstract description 9
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 239000011229 interlayer Substances 0.000 abstract description 3
- 238000005137 deposition process Methods 0.000 abstract description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
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Abstract
본 발명은 플래쉬 메모리소자의 형성 공정시 게이트를 형성한 후 산화 열처리 공정시 내부 폴리간 절연막인 ONO의 파열을 억제하기 위해 게이트를 형성한 후 CVD 산화막 증착공정을 수행하여 ONO층의 노출을 방지하여 후속 산화 열처리 공정시 산화막의 확산에 의한 파열을 억제함으로써 플레쉬 메모리 소자의 소거동작시 소거의 균일성을 향상시킬 수 있도록 한 플래쉬 메모리소자의 게이트 전극 형성 방법에 관한 것으로, 식각 공정으로 게이트를 형성한 후 후속 열처리를 수행하는 플래쉬 메모리소자의 형성 방법에 있어서, 게이트를 형성한 후 산화막 증착단계를 더 포함하여 이루어져 식각에 의해 손상받은 폴리간 절연막을 보호하여 후속 열공정시 파열되는 것을 방지할 수 있게 된다.According to the present invention, after forming a gate in the process of forming a flash memory device and forming a gate to suppress the rupture of the internal poly interlayer insulating film during the oxidation heat treatment process, a CVD oxide film deposition process is performed to prevent exposure of the ONO layer. A method of forming a gate electrode of a flash memory device which improves the uniformity of erase during an erase operation of a flash memory device by suppressing rupture caused by diffusion of an oxide film during a subsequent oxidation heat treatment process. In the method of forming a flash memory device to perform a subsequent heat treatment after the formation of a gate, the method further comprises an oxide film deposition step to protect the inter-poly insulating film damaged by etching can be prevented from being ruptured during the subsequent thermal process. .
Description
본 발명은 플래쉬 메모리소자의 게이트 전극 형성 방법에 관한 것으로서, 보다 상세하게는 플래쉬 메모리소자의 형성 공정시 게이트를 형성한 후 산화 열처리 공정시 폴리간 절연막인 ONO의 파열을 억제하기 위해 게이트를 형성한 후 CVD 산화막 증착공정을 수행하여 ONO층의 노출을 방지하여 후속 산화 열처리 공정시 산화막의 확산에 의한 파열을 억제함으로써 플레쉬 메모리 소자의 소거동작시 소거의 균일성을 향상시킬 수 있도록 한 플래쉬 메모리소자의 게이트 전극 형성 방법에 관한 것이다.The present invention relates to a method of forming a gate electrode of a flash memory device, and more particularly, to form a gate in the formation process of the flash memory device and to form a gate to suppress the rupture of ONO, which is an inter-poly insulation film, in the oxidation heat treatment process. After the CVD oxide film deposition process to prevent the exposure of the ONO layer to suppress the rupture caused by the diffusion of the oxide film in the subsequent oxidation heat treatment process flash memory device to improve the uniformity of erase during the erase operation of the flash memory device A method of forming a gate electrode.
플래쉬 메모리는 플로팅 게이트(Floating Gate)를 이용하여 프로그래밍과 소거동작을 수행하는 메모리로서 프로그래밍 동작은 아래쪽 플로팅 게이트에 전자를 주입시켜서 셀트랜지스터의 문턱전압을 증가시키는 동작이고 소거동작은 플로팅 게이트에 있는 전자를 뽑아내어 플로팅 게이트를 전자가 없는 상태로 만들어 문턱전압을 낮추는 동작이다.The flash memory is a memory that performs programming and erasing operations using a floating gate. The programming operation is to increase the threshold voltage of the cell transistor by injecting electrons into the lower floating gate. The operation is to lower the threshold voltage by extracting and making the floating gate free of electrons.
플래쉬 메모리에서의 소거동작은 셀 단위가 아닌 섹터나 블록단위로 이루어지기 때문에 셀과 셀간의 소거 시간의 균일도는 소자의 특성 및 수율증가에 중요한 영향을 미치게 된다.Since the erase operation in the flash memory is performed in units of sectors or blocks rather than units of cells, the uniformity of erase time between cells has a significant effect on the characteristics and yield of devices.
이러한 소거시간의 균일도는 콘트롤 게이트에 전압 인가시 ONO의 커패시턴스와, 터널 산화막의 커패시턴스와, 드레인측의 커패시턴스등에 의해 플로팅 게이트에 유도되는 플로팅 게이트 전압에 의해 영향을 받기 때문에 각 셀에서의 ONO 유전체의 두께 및 터널 산화막의 두께는 균일해야 한다.The uniformity of the erase time is influenced by the capacitance of the ONO when the voltage is applied to the control gate, the capacitance of the tunnel oxide film, the floating gate voltage induced in the floating gate by the capacitance on the drain side, and so on. The thickness and the thickness of the tunnel oxide film should be uniform.
도 1내지 도 2는 종래 방법에 의한 플래쉬 메모리소자의 게이트 전극 형성 방법을 나타낸 단면도들이다.1 to 2 are cross-sectional views illustrating a gate electrode forming method of a flash memory device according to a conventional method.
도 1과 같이 게이트를 형성하기 위해 기판(10)위로 터널 산화막(20)과 플로팅 게이트(30)와 폴리간 절연막(40)인 ONO층과 콘트롤 게이트(50)를 차례로 형성한 후 셀프얼라인 식각을 하여 게이트 전극을 형성한다.As shown in FIG. 1, a tunnel oxide film 20, a floating gate 30, an ONO layer, which is an inter-poly insulating film 40, and a control gate 50 are sequentially formed on the substrate 10 to form a gate. To form a gate electrode.
그런다음, 산화공정과 소스 주입공정과 열공정을 진행함에 따라 제1산화막(60)이 형성되면서 산소가 쉽게 폴리간 절연막(40)인 ONO층과 폴리실리콘의 계면으로 침투하게 되어 도 2의 'A' 부분과 같이 국부적으로 ONO층이 파열되는 현상이 발생되어 폴리간 절연막(40)의 두께가 불균일하게 된다.Then, as the oxidation process, the source injection process, and the thermal process are performed, the first oxide film 60 is formed, and oxygen easily penetrates into the interface between the ONO layer, which is the interpoly insulation film 40, and the polysilicon. A phenomenon in which the ONO layer ruptures locally occurs, such as the portion A ', resulting in an uneven thickness of the inter-poly insulating film 40.
위와 같이 폴리간 절연막(40)의 파열 현상은 셀과 셀간에도 불균일하게 일어나기 때문에 소거 동작시 각 셀의 플로팅 게이트(30)에 걸리는 전압이 서로 다르게 되어 각 셀의 소거 동작에 걸리는 시간이 다르게 된다. 즉, 특정 섹터를 소거할 때 소거 시간이 불균일하게 되어 가장 느리게 소거되는 셀이 소거되는 동안 이미 소거된 나머지 셀들은 계속해서 전압이 인가되기 때문에 과소거되어 게이트 산화막이 열화됨으로 인해 특성이 저하되고 수율감소 및 수명 단축을 일으키게 된다는 문제점이 있다.As described above, since the rupture phenomenon of the inter-poly insulating film 40 occurs non-uniformly between cells, the voltage applied to the floating gate 30 of each cell during the erase operation is different from each other, resulting in a different time taken for the erase operation of each cell. In other words, when erasing a specific sector, the erase time becomes uneven and the cells that are already erased while the slowest erased cells are erased because the remaining cells continue to be applied with voltage, resulting in deterioration of the gate oxide film and deterioration of the characteristics. There is a problem that decrease and shorten the life.
본 발명은 상기와 같은 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 목적은 플래쉬 메모리소자의 게이트를 형성한 후 셀프얼라인 식각후 식각에 의해 손상된 게이트위에 CVD방법에 의한 산화막을 증착하여 후속 열처리 공정에서 폴리 실리콘과 ONO층의 계면에서 과도하게 산화되는 것을 방지함으로써 ONO층의 파열을 억제하여 ONO층을 균일하게 형성하여 플래쉬 메모리소자의 소거동작시 각 셀에서의 소거시간을 균일하게 하여 소자의 특성을 향상시킬 수 있도록 하는 플래쉬 메모리소자의 게이트 전극 형성 방법을 제공함에 있다.The present invention has been made to solve the above problems, and an object of the present invention is to form a gate of a flash memory device, and then deposit an oxide film by a CVD method on a gate damaged by etching after self-aligned etching, and subsequently heat treatment. By preventing excessive oxidation at the interface between the polysilicon and the ONO layer in the process, the rupture of the ONO layer is suppressed to form the ONO layer uniformly, and the erase time is uniform in each cell during the erase operation of the flash memory device. The present invention provides a method of forming a gate electrode of a flash memory device capable of improving characteristics.
도 1내지 도 2는 종래 방법에 의한 플래쉬 메모리소자의 게이트 전극 형성 방법을 나타낸 단면도들이다.1 to 2 are cross-sectional views illustrating a gate electrode forming method of a flash memory device according to a conventional method.
도 3내지 도4는 본 발명에 의한 플래쉬 메모리소자의 게이트 전극 형성 방법을 설명하기 위한 단면도들이다.3 to 4 are cross-sectional views illustrating a method of forming a gate electrode of a flash memory device according to the present invention.
- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-
10 : 기판 20 : 터널 산화막10 substrate 20 tunnel oxide film
30 : 플로팅 게이트 40 : 폴리간 절연막30: floating gate 40: poly interlayer insulating film
50 : 콘트롤 게이트 60 : 제 1산화막50: control gate 60: first oxide film
상기와 같은 목적을 실현하기 위한 본 발명은 식각 공정으로 게이트를 형성한 후 후속 열처리를 수행하는 플래쉬 메모리소자의 형성 방법에 있어서, 게이트를 형성한 후 CVD법에 의한 산화막 증착 단계를 더 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method of forming a flash memory device in which a subsequent heat treatment is performed after a gate is formed by an etching process, the method further comprising an oxide film deposition step by CVD after a gate is formed. It is characterized by.
위와 같이 이루어진 본 발명의 작용을 설명하면 다음과 같다.Referring to the operation of the present invention made as described above are as follows.
식각공정으로 게이트전극을 형성할 때 손상을 받은 플로팅 게이트와 콘트롤 게이트간의 폴리간 절연막이 후속 열처리 공정시 손상을 입어 파열되는 것을 방지하기 위해 CVD법에 의해 산화막을 형성하여 보호함으로써 폴리간 절연막의 파열을 방지하여 균일한 두께의 폴리간 절연막을 얻을 수 있도록 한다.In order to prevent the inter-poly insulation film between the floating gate and the control gate, which is damaged when forming the gate electrode by the etching process, by forming and protecting an oxide film by CVD in order to prevent the inter-layer insulation film from being damaged and ruptured during the subsequent heat treatment process, the inter-poly insulation film is broken It is possible to obtain an inter-poly insulating film of a uniform thickness by preventing the film.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.
도 3내지 도4는 본 발명에 의한 플래쉬 메모리소자의 게이트 전극 형성 방법을 설명하기 위한 단면도들이다.3 to 4 are cross-sectional views illustrating a method of forming a gate electrode of a flash memory device according to the present invention.
도 3과 같이 기판(10) 상부에 터널 산화막(20)을 증착하고 플로팅 게이트(30)를 형성하고 폴리간 절연막(40)인 ONO층을 증착한 후 콘트롤 게이트(50)를 형성한 후 셀프얼라인 식각을 수행한 다음 식각에 의해 손상된 게이트 전면에 CVD 방법에 의해 제 2산화막(70)을 200Å 이하의 두께로 증착하여 후속 산화 열처리 공정에서의 폴리 실리콘과 ONO층의 계면으로의 제 1산화막(60) 확산이 과도하게 이루어지는 것을 방지함으로써 ONO 파열을 억제하도록 한다.As shown in FIG. 3, a tunnel oxide film 20 is deposited on the substrate 10, a floating gate 30 is formed, an ONO layer, which is an interpoly insulation film 40, and a control gate 50 are formed. After the phosphorus etching was performed, the second oxide film 70 was deposited to a thickness of 200 μm or less on the entire surface of the gate damaged by the etching by the CVD method, and the first oxide film to the interface between the polysilicon and the ONO layer in a subsequent oxidation heat treatment process ( 60) It is possible to suppress ONO rupture by preventing excessive diffusion.
이때 CVD에 의한 제 2산화막(70)의 증착시 노내로 웨이퍼를 로딩할 때 400℃이하의 온도에서 N2가스를 15 slpm 이상으로 웨이퍼 표면에 불어주면서 노내에 있는 산소에 의해 산화되는 것을 방지한다. 이때 로딩할 때의 온도를 룸 실내 온도로 설정함이 바람직하며, N2가스는 N2퍼지박스나 N2로딩 락 시스템을 사용하는 것이 바람직하다.At this time, when the wafer is loaded into the furnace during deposition of the second oxide film 70 by CVD, N 2 gas is blown to the surface of the wafer at 15 slpm or more at a temperature of 400 ° C. or lower to prevent oxidation by oxygen in the furnace. . At this time, it is preferable to set the temperature at the time of loading to room temperature, and it is preferable to use N 2 gas as the N 2 purge box or the N 2 loading lock system.
위와 같은 환경에서 노내로 로딩시킨 후 온도가 안정되어 증착하기 전까지 노내에 N2가스를 퍼지하면서 200 mTorr∼1 Torr의 압력을 유지한다.After loading into the furnace under the above environment, the temperature is stabilized and the pressure of 200 mTorr to 1 Torr is maintained while purging the N 2 gas in the furnace.
그런다음, 노내의 온도를 750∼850℃, 압력을 200∼800 mTorr로 유지하면서, SiH4나 SiH2Cl2등의 실리콘 소스 가스와 N2O 등의 산소 소스가스를 사용하여 300Å 의 두께로 제 2산화막(70)을 증착한다.Then, using a silicon source gas such as SiH 4 or SiH 2 Cl 2 and an oxygen source gas such as N 2 O while maintaining the temperature in the furnace at 750 to 850 ° C. and the pressure at 200 to 800 mTorr, the thickness is 300 kPa. The second oxide film 70 is deposited.
이때 증착온도는 810∼840℃로 유지하는 것이 바람직하며, 제 2산화막(70)의 증착 두께는 50∼100Å으로 증착하는 것이 바람직하다.At this time, the deposition temperature is preferably maintained at 810 ~ 840 ℃, the deposition thickness of the second oxide film 70 is preferably deposited at 50 ~ 100Å.
위와 같이 제 2산화막(70)을 증착한 후 N2가스 분위기 하에서 온도를 하강시킨 후 언로딩하게 된다.After depositing the second oxide film 70 as described above, the temperature is lowered under an N 2 gas atmosphere, and then unloaded.
그런다음, 도 3의 결과물을 산화공정, 소스 주입공정, 열공정을 수행하여 도 4와 같이 제 1산화막(60)을 증착시키게 된다.Thereafter, the resultant oxide of FIG. 3 is subjected to an oxidation process, a source injection process, and a thermal process to deposit the first oxide layer 60 as shown in FIG. 4.
이렇게 CVD법에 의해 제 2산화막(70)을 증착하여 폴리간 절연막(40)을 보호하도록 함에 따라 이후 열공정을 수행하게 됨에 따라 폴리간 절연막(40)에서 발생되는 파열을 억제할 수 있게 된다.As the second oxide film 70 is deposited by the CVD method to protect the inter-poly insulating film 40, the thermal process is subsequently performed, thereby preventing the rupture generated in the inter-poly insulating film 40.
상기한 바와 같이 본 발명은 플래쉬 메모리소자의 게이트를 형성한 후 후속 열공정에 노출되는 폴리간 절연막인 ONO층을 산화막으로 덮게 됨으로써 후속 열공정에서의 산소의 확산 정도를 조절가능하게 하여 각 셀에서 균일한 두께의 ONO층을 얻고 동일 셀내에서도 균일한 막을 유지함으로서 균일한 유전막에서 발생하는 국부적인 전계집중을 개선할 뿐만아니라 소자의 소거 동작시 소거 균일도를 개선하여 쓰기 및 소거동작의 반복적인 사이클에 따른 소자의 열화를 방지할 수 있다는 이점이 있다.As described above, the present invention covers the ONO layer, which is an interpoly insulation film exposed to a subsequent thermal process, after forming a gate of a flash memory device with an oxide film, thereby making it possible to control the degree of diffusion of oxygen in the subsequent thermal process in each cell. By obtaining an ONO layer with a uniform thickness and maintaining a uniform film even in the same cell, it not only improves local electric field concentration occurring in the uniform dielectric film, but also improves the erase uniformity during the erase operation of the device, thereby repetitive cycles of writing and erasing operations. There is an advantage that can be prevented deterioration of the device.
또한, 게이트 형성시 발생되는 플로팅 게이트와 기판 사이의 터널 산화막의 식각 손상 및 폴리간 절연막인 ONO층의 식각 손상을 후속 고온 열공정시 산화막에 의해 완화시킬 수 있다는 이점이 있다.In addition, there is an advantage that the etching damage of the tunnel oxide film between the floating gate and the substrate generated during the gate formation and the etching damage of the ONO layer, which is an inter-poly insulating film, can be alleviated by the oxide film during the subsequent high temperature thermal process.
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