KR100362911B1 - The video decoding processor using huffman code - Google Patents

Abstract

The present invention relates to a video decoding processing apparatus using Huffman code. In particular, during the decoding process, decoding by pipeline structure is performed to determine the decoding information necessary for the current step from the plurality of decoding information decoded by the plurality of size detectors and transmits the decoding information to the counter. The present invention relates to a video decoding processing apparatus having improved processing speed. In the conventional decoding process, the data selection signal generated by supplying the information decoded by the decoder unit to the control unit is retransmitted to the decoder unit to latch the information to be decoded in the next step to the decoder unit, and the data size signal from the decoder unit to the counter unit. On the other hand, the present invention is a structure in which the next decoding step is performed only after the transmission. However, the present invention converts the data size signal of the decoding information obtained by decoding Huffman code data by the plurality of size detectors to the counter unit, the control unit, and the memory / register unit. By simultaneously transmitting, when the data storage location is determined and the data is stored, the multiplexer unit selects Huffman code data and transmits the selected Huffman code data to the size detector unit. Presenting a decoding device have.

Description

The video decoding processor using huffman code}

The present invention relates to a video decoding processing apparatus using Huffman code. In particular, during the decoding process, decoding by pipeline structure is performed to determine the decoding information necessary for the current step from the plurality of decoding information decoded by the plurality of size detectors and transmits the decoding information to the counter. The present invention relates to a video decoding processing apparatus having improved processing speed.

The prior art will be described with reference to the drawings. 1 is a block diagram of a video decoding apparatus for decoding conventional Huffman code data.

Although not shown in FIG. 1, the first input bitstream is stored as a serial data and stored in a memory unit or a register unit.

The register unit 1 shown in FIG. 1 stores bit streams stored as serial data as parallel data.

The multiplexer section (2) selects Huffman code data from the register section (1) according to the data start position signal supplied from the counter section (6) to the decoder section (3). Move it.

When the decoder unit 3 decodes the Huffman code data supplied from the multiplexer unit 2, the Huffman code table is different according to the type of data to be decoded due to the characteristics of the Huffman code. The data size signal that determines the type of data to be decoded by referring to the data decoded in the previous step and the current operation status is supplied, but is configured to be decoded.

In addition, the decoder unit 3 supplies the decoded data to a memory / register unit 4 and a controller 5, respectively.

The memory / register section 4 stores the decoded data transmitted from the decoder section 3 in any one place according to the type of data in the memory or register.

Since the size of the data varies depending on the type of the length of the Huffman code and the encoded value, the control unit 5 refers to the decoded data transmitted from the decoder unit 3 and the current operation state. (3) supplies to the decoder unit 3 a data selection signal informing the Huffman code data information to be decoded in the next step. That is, if the order of the Huffman code data recorded in the bitstream is determined in the order of MBA, MBT, and CBP, the control section 5 supplies the data selection signal to the decoder section 3 to decode in the above order.

In addition, the decoder unit 3 supplies the data size signal generated by referring to the data selection signal supplied from the control unit 5 to the counter unit 6 again.

The counter unit 6 accumulates data size signals from the decoder unit 3 up to the previous stage, and receives a data size signal from the decoder unit 3 indicating the size of data to be decoded at this stage. After that, the data start position signal is supplied to the multiplexer 2 so that the multiplexer 2 can select the data to be decoded at this stage by checking the data size accumulated up to the previous stage.

Huffman code decoding of one variable length is completed by the series of processes, and Huffman code data is decoded and stored sequentially by repeating the above process.

However, the structure of the video decoding apparatus for decoding the Huffman code data, which is the conventional structure, performs the next decoding step only when the data start position signal output from the counter section 6 is supplied to the multiplexer section 2.

That is, referring to the configuration block diagram of the conventional video decoding apparatus of FIG.

The counter unit 6 calculates the size of the decoded data so as to select the Huffman code data to be decoded by the decoder unit 3, and transmits a data start position signal to the multiplexer unit 2 (S100);

The multiplexer unit 2 selects Huffman code data from the register unit 1 by the data start position signal transmitted from the counter unit 6 (S110),

Transmitting the selected Huffman code data to the decoder 3 (S120);

Decoding the transmitted Huffman code data by the decoder 3 (S130),

Storing the decoded data in the memory / register section 4 (S140),

Determining a second data selection signal based on the data decoded in step S130 (S150);

Transmitting a second data selection signal from the control section 5 to the decoder 3 section so that the decoder section 3 can decode in the next step (S160);

In step S170, the data size signal is transmitted from the decoder unit 3 to the counter unit 6 so that the data start position signal to be decoded can be selected.

In storing the decoded data of the memory or the register in any one in step S140, the storage location is determined and transmitted to the memory / register unit 4 in step S130.

In step S150, the control unit 5 is configured to determine the data selection signal to be decoded in the next step by referring to the decoded data supplied from the decoder unit 3 and an operation state indicating the current state.

Here, step S140 and step S150 are configured to be performed at the same time.

Further, in step S150, the control unit 5 supplies a data selection signal for determining the input data to be decoded in the next step by referring to the decoded information received from the decoder unit 3, The decoder unit 3 transmits the data size signal of the decoded information to the counter unit 6 with reference to the supplied data selection signal, so that other steps are periodic signals until the step S170 is completed. After the step S170 is completed, the decoding processing speed is delayed because the step is performed while synchronizing with the clock signal sequentially from the next step S100 after the step S170 is completed.

That is, the clock signal consumed for synchronization in the series of processes is the first clock signal in the Huffman code selection step in step S110, the second clock signal in the decoding step in step S130, the data storage step and step S150 in step S150. As the third clock signal in the selection signal determination step, a total of '3' clock signals are consumed until the Huffman code decoding of one variable length is completed.

The present invention is to solve the problem that the decoding processing speed is delayed, an object of the present invention is to determine the storage location of the data in the decoding process, when performing the data storage in the memory / register unit, The present invention provides a video decoding processing apparatus using a Huffman code that performs a decoding process of a next step by a pipeline structure in which a counter unit, a multiplexer unit, and a size detector unit that performs a decoding process each play a role.

According to an embodiment of the present invention, the counter unit calculates a data length to be decoded by referring to a data size signal which is a decoded information signal of a previous step, and transmits a data start position signal to a multiplexer unit. The multiplexer unit selects the Huffman code data to be decoded from the register unit according to the data start position signal transmitted from the counter unit, transmits the selected Huffman code data to the size detector unit, and the size detector unit transmits the plurality of Huffman code data. Decoding is performed using a size detector, and one piece of decoded information is transmitted to a counter unit, a control unit, and a memory / register unit, respectively, by a data selection signal supplied from a control unit among the plurality of decoded pieces of information. Decoded information sent from the detector The data start position signal is transmitted to the multiplexer unit by calculating the length of the Huffman code data to be decoded in the next step with reference to the data size signal, and the control unit also includes the data size signal and the current state as the decoded information transmitted from the size detector unit. Determining one of a memory or a register as a storage means with reference to a signal, and transmitting a data storage signal for determining a data storage location in a memory / register section, wherein the memory / register section decodes decoding information transmitted from the size detector section. The decoded data is stored with reference to the data storage signal transmitted from the controller. In this case, the size detector unit is composed of a combination which does not require the consumption of the clock signal used for synchronization, thereby reducing the consumption of the clock signal, and also transferring data from the size detector unit to the counter unit and the control unit. A video decoding processing apparatus using a Huffman code whose decoding process speed is improved by a pipe line structure that can process information on data to be decoded in a next step by a magnitude signal, according to each clock signal. do.

1 is a block diagram of a conventional video decoding apparatus.

FIG. 2 is a block diagram illustrating a process of decoding Huffman code data as an embodiment of FIG.

3 is a block diagram of a video decoding apparatus which is an essential part of the present invention;

4 is a block diagram illustrating a size detector unit, which is a main part of the present invention;

5 is a block diagram illustrating a control unit which is a main part of the present invention.

FIG. 6 is a block diagram illustrating a process of decoding Huffman code data as an embodiment of FIG.

<Description of the symbols for the main parts of the drawings>

1: register section 2: multiplexer section

3: decoder section 4: memory / register section

5: control unit 6: counter unit

7: Size detector unit 8: Memory / register unit

9 control unit 10 decoding control unit

11: current state part 12: next state part

13: State Machine

Hereinafter, with reference to the accompanying drawings, the configuration and operation of the embodiment for achieving the object of the present invention will be described.

3 below, only the components necessary for describing the embodiments of the present invention will be described, except for the description of the components having the same configuration and function as those described in FIG. 1.

3 is a block diagram illustrating a video decoding apparatus having an improved decoding processing speed by a pipeline, which is an embodiment of the present invention.

As shown in FIG. 3, the Size Detector 7 is a combination structure that does not synchronize with a clock when decoding Huffman code data supplied from the multiplexer 2. The decoded data size signal is supplied to the memory / register unit 8, the control unit 9, and the counter unit 6, respectively.

The counter section 6 supplies the data start position signal to the multiplexer section 2 so that the Huffman code data to be decoded in the next step can be selected by the data size signal supplied from the size detector 7.

The control unit 9 refers to the data size signal supplied from the size detector unit 7 and the current state signal indicating the operation status of the current state latched in the current state unit 11, and the size detector unit 7 in the next decoding step. Multiple data to be decoded by multiple size detectors And a memory for supplying a data selection signal to the size detector unit 7 so as to determine one of the plurality of data size signals, and also referring to the data size signal and the operation state of the current state. According to the type of data in the register, a data storage signal for determining any one storage location is supplied to the memory / register section 8.

The memory / register unit 8 stores the decoded data transmitted from the size detector unit 7 with reference to the data storage signal transmitted from the control unit 9.

4 is a block diagram illustrating a process of decoding Huffman code data in the size detector.

As shown in FIG. 4, when the Huffman code data is input from the multiplexer section 2 to the size detector section 7, the Huffman code data is formed by a plurality of size detectors configured in the size detector section 7. Is decoded into a plurality of decoded data and data size signals. Of the plurality of data size signals among the decoded information, the multiplexer provides one data size signal by a data selection signal supplied from the controller 9 in a previous step. Select.

The selected data magnitude signal is supplied to the control section 9 and the counter section 6, respectively.

FIG. 5 shows the supply of the data size signal to supply the data selection signal to the size detector unit and the memory unit by the interaction of the current state unit, the next state unit, the state machine, and the decoding control unit which are components of the control unit 9. It is a block diagram showing this.

As shown in FIG. 5, the data size signal supplied from the size detector unit 7 is supplied to the decoding control unit 10 and the state machine 13, respectively.

The decoding control unit 10 uses a data size signal supplied from the size detector unit 7 and a current state signal transmitted from the current state unit 11 to select any one of a memory or a register which is data storage means. The data storage signal for determining one of the signals is supplied to the memory / register section 8.

In addition, the decoding control unit 10 refers to the data size signal supplied from the size detector unit 7 and the operation status of the current state latched in the current state unit 11, and the size detector unit 7 in the next decoding step. Multiple data to be decoded by multiple size detectors And a data selection signal to the size detector unit 7 so as to determine one of the plurality of data size signals.

The state machine 13 uses the data size signal transmitted from the size detector 7 and the current state signal transmitted from the current state unit 11 to output a next state signal indicating an operation state to be decoded in the next step. Determine and supply to the next state (12).

The next state unit 12 supplies the current state unit 11 with a next state signal indicating an operation state to be decoded in the next step supplied from the state machine 13.

Here, after the current state signal of the current state unit 11 is supplied to the decoding control unit 10, the next state signal of the next state unit 12 will be configured to be supplied to the current state unit 11.

FIG. 6 is a block diagram illustrating a process of decoding Huffman code data according to an embodiment of the present invention.

The counter unit 6 refers to the data size signal which is the decoded information signal of the previous stage received from the size detector unit 7, calculates the data length to be decoded, and transmits the data start position signal to the multiplexer unit 2. Step (S200) and

The multiplexer unit 2 selects Huffman code data to be decoded from the register unit 1 by the data start position signal transmitted from the counter unit 6 (S210),

Transmitting the selected Huffman code data to the size detector unit 7 (S220);

The size detector unit 7 decodes the transmitted Huffman code data using a plurality of size detectors (S230);

The control unit 9 determines the data storage signal by referring to the data length signal transmitted from the size detector unit 7 and the current state signal transmitted from the current state unit (S240);

Storing the decoded data transmitted from the size detector 7 in one of a memory or a register with reference to the data storage signal transmitted from the controller 9 (S250);

In step S230, the control unit 9 transmits the data selection signal to the size detector unit 7 to select the information to be decoded in the next step based on the transmitted data size signal and the current state signal transmitted from the current state unit 11. The process is completed in step S260.

The information decoded in step S230 may be configured to be simultaneously supplied to the counter 6, the controller 9, and the memory / register 8.

In addition, the Huffman code data supplied in step S230 is read by a plurality of size detectors and transmitted to the counter unit 6 to determine the storage location of the decoded data, and the next stage of decoding. When selecting the information and storing the decoded data in the memory / register section 8, the multiplexer section 2 is configured to select the Huffman code data and to transmit the selected Huffman code data to the size detector section 7. will be.

That is, the decoder unit may select the Huffman code data to be decoded in the next step from the step (S100) of transmitting the data start position signal to the multiplexer unit 2 by calculating the length of the Huffman code to be decoded. While the step (S170) of transmitting the data size signal from the (3) to the counter unit 8 is completed, the process proceeds to step S100 again, while the size detector unit 7 transmits the decoding step of the present invention. In order to select the Huffman code data to be decoded by the counter unit 6 from the step S230 of decoding the Huffman code data using a plurality of size detectors, the data start position signal is supplied to the step S200 to provide a pipeline. It will be configured to improve the decoding processing speed by.

That is, the decoding process of the video decoding processing apparatus using the Huffman code, which has been conventionally implemented, can decode the Huffman code only when the periodic clock signal used for synchronization is applied. While the next decoding process is performed after application of the first clock signal in the code selection step, the second clock signal in the decoding step S130 and the third clock signal in the data selection signal determination step S150, the Huffman code of the present invention is used. The video decoding process is composed of a combination that is not related to the clock signal to be synchronized. After the first clock signal is applied in the Huffman code data selection step of step S210, decoding is performed by a size detector unit independent of the clock signal. By transmitting the data size signal of the decoded information to step S200 and then By performing the decoding process of the step, it will be configured to consume only '1' clock signal until decoding of one variable length Huffman code is completed.

As described above, in the present invention, in performing the decoding process, the size detector unit is composed of a combination that is independent of the clock signal, and the control unit refers to the data size signal and the current state signal indicating the operation status of the current state. By supplying a data selection signal to the size detector so as to determine one of the plurality of data size signals to be decoded in the next step, when decoding is performed at the size detector, the decoding process is performed without application of a clock signal. By supplying a data start position signal to the multiplexer so as to select one of the plurality of data size signals decoded by the data selection signal transmitted from the control unit so as to select Huffman code data to be decoded in the next step. Decoding process of two variable length Huffman codes It is configured to consume only '1' clock signal until the conventional decoding process of one variable length Huffman code is completed. It has the effect of improving the processing speed more than three times during the process.

In addition, the power consumption of the video decoding apparatus synchronized with the clock signal can be reduced.

Claims (4)

First storage means for converting the Huffman code data input in serial and storing in parallel; Outputting means for cutting the stored Huffman code data by a data start position signal and outputting the truncated Huffman code data; One decoded data and one decoded data by a data selection signal, among the plurality of decoded data and a plurality of decoded data size signals generated by using the plurality of decoding apparatuses, the truncated Huffman code data of the output means. Decoding means for selecting a magnitude signal; Signal generating means for generating a data start position signal in response to the decoded data magnitude signal; Second storage means for storing the decoded data in any one of at least one data storage place in response to a data storage signal; And Control means for generating a data selection signal and a data storage signal by the decoded data size signal and the current state signal for controlling a current operation state to control the decoding means and the second storage means; A video decoding processing device using a Huffman code. The video decoding processing apparatus according to claim 1, wherein the decoding means has a combination structure that is not synchronized with a clock signal. The apparatus of claim 1 or 2, wherein the data size signal generated by the decoding means is simultaneously transmitted to the control means, the second storage means, and the signal generating means. The method of claim 1, wherein the control means; A current state unit for latching a current state signal for controlling the current operation state; A decoding control unit for generating a data selection signal and a data storage signal by a data size signal supplied from the decoding means and a current state signal latched in the current state unit; A state machine for generating a next state signal for controlling a next operation state by means of a data size signal supplied from said decoating means and a current state signal supplied from a current state unit; And a next state portion for latching a next state signal generated by said state machine.