JP3254899B2 - Image decoding processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image decoding processing apparatus for decoding input code data.

[0002]

2. Description of the Related Art Conventionally, when data is transmitted, for example, by facsimile, the data is encoded at a source and decoded at a destination. Numerous schemes have been developed for encoding and decoding. As one of them, there is one using predictive coding, for example. FIG. 8 is a block diagram illustrating an example of a decoding process of code data that has been predictively encoded. In the figure, 51 is code data, 52 is a decoder, 53 is prediction error data, 54 is an inverse predictor, and 55 is image data. In the decoder 52, when the run length encoding is performed on the code data 51, the run length is decoded, and when the arithmetic encoding is performed, the inverse operation of the probability is performed.
The prediction error data 53 is generated. The prediction error data 53 is converted into image data 55 by the inverse predictor 54.
At this time, the number of prediction error data 53 and the number of image data 55 are generally the same.

[0003] However, errors may occur in transmitted code data due to noise or the like during transmission. If there is an error in the code data, the code data is received, and an error occurs when a decoding process is performed. For example, when decoding code data that has been subjected to predictive coding, if an error occurs in the code data, the number of prediction error data 53 becomes incorrect, and the number of image data converted by the inverse predictor 54 increases or decreases. However, there is a problem that a shift occurs in the obtained entire image.

When an error occurs in code data due to such a transmission error or the like, generally, decoding processing of the line is interrupted, and 0 is inserted as decoded data of the entire line in which an error has occurred, This is supported by outputting the data as it is. In addition, for example, see
As described in JP-A-345275, etc., in order to prevent image quality deterioration due to an error code, when an error is detected,
There is also a method of searching for the end code of the line and decoding from the end code side toward the error signal. However, the method described in Japanese Patent Application Laid-Open No. 4-345275 discloses a method in which the code is reversed when encoding is performed using Huffman coding, arithmetic coding, or the like, which is widely used as the coding method. It is impossible because it cannot be deciphered from.

In both the method of outputting the data of the previous line as it is and the method described in JP-A-4-345275, the decoding process must be interrupted in order to correct an error. There is a problem that processing cannot be performed. In particular, when arithmetic coding is performed, a code error cannot be detected until the end of the line, so that there is a problem that the decoding process must be interrupted when the code error is detected. As for the reproduction error correction of the arithmetic code, see, for example,
In Japanese Patent Publication No. 74, the interval between marker codes is controlled to prevent a decrease in compression or the like. However, basically, if an error occurs, means such as data retransmission must be taken, and processing cannot be performed in real time. There is a problem.

On the other hand, when decoding the code data, if the speed of the code input side of the decoding device is different from the speed of the decoded data output side, a buffer memory is inserted into the interface with the outside to prevent the speed reduction. I have. FIG. 9 is a block diagram showing an example of a conventional decoding processing device using a buffer memory. In the figure, reference numeral 51 denotes code data, 55 denotes image data, 56 denotes a memory, and 57 denotes a decoding processing unit. The decoding processing unit 57 decodes the input code data 51,
The image data 55 is output. The memory 56 temporarily stores and outputs the image data 55 output from the decoding processing unit 57. Since the memory 56 holds the image data 55 decoded by the decoding processing unit 57 to some extent, the decoding processing unit 5
Even if the processing speed of the device that receives the image data 55 is lower than the processing speed of 7, the decoding processing unit 57 can proceed without waiting until the image data 55 is received. In FIG. 8, the memory 56 is arranged after the code processing unit 57. However, the memory 56 can be arranged before the code processing unit 57, for example, as am95C71 (product name).

FIG. 10 is a block diagram showing an example of a conventional decoding processing apparatus for predictively encoded code data using a buffer memory. In the figure, the same parts as those in FIG. 8 are denoted by the same reference numerals. 56 is a memory. FIG.
Shows a case where decoding is performed on the code data subjected to the predictive coding shown in FIG. The memory 56 includes the decoding unit 5
2 and the prediction error data 53 output from the decoding unit 52 and temporarily stored between the decoding unit 52 and the inverse prediction unit 54.
Output to The memory 56 can adjust the speed when the processing speed of the decoding unit 52 and the processing speed of the inverse prediction unit 54 are different. Such a configuration is disclosed in, for example, Japanese Patent Application Laid-Open No. 5-176.
187, for example, and M65
700 (product name).

In the configuration using the buffer memory as described above, if the number of data written in the buffer memory is read out, the decoded number becomes incorrect due to a code error. There is a problem that a shift occurs in the entire image.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described circumstances, and has been made in consideration of the following problems when decoding coded data.
It is an object of the present invention to provide a decoding processing device capable of reducing the deterioration of decoded data due to a code error and performing decoding in real time.

[0010]

According to a first aspect of the present invention, there is provided an image decoding processing apparatus for decoding an input code, comprising: decoding means for decoding the input code into prediction error data; Counting means for counting the number of data of the prediction error data decoded by the means; comparison means for comparing the count value of the counting means with a specified number; prediction error data decoded by the decoding means based on the comparison result by the comparison means Control means for controlling the number of outputs and outputting predetermined prediction error data by the difference between the specified number and the count value when the count value by the counting means is smaller than a specified number; and performing reverse prediction based on the predicted error data. The present invention is characterized in that it is provided with a reverse prediction means for performing the prediction.

Further, in the invention according to claim 2,
In an image decoding processing device for decoding an input code, a decoding means for decoding the input code into prediction error data, a buffer memory for temporarily storing the prediction error data decoded by the decoding means, Counting means for counting the number of data when writing the decoded prediction error data; comparing means for comparing the count value of the counting means with a prescribed number; and reading the number of data from the buffer memory based on the comparison result by the comparing means. Control means for controlling and reading out the prediction error data from the buffer memory up to the count value when the count value by the counting means is smaller than a prescribed number, and thereafter outputting predetermined prediction error data by a difference between the prescribed number and the count value; It is characterized by comprising a reverse prediction means for performing reverse prediction based on prediction error data.

According to a third aspect of the present invention, in the image decoding processing apparatus according to the second aspect, the buffer memory comprises a plurality of memories, and detects a synchronization code in an input code. The apparatus may be configured to include switching means for switching between reading and writing of the plurality of memories.

[0013]

[0014]

According to the present invention, in the first aspect of the present invention, the number of data of the prediction error data decoded by the decoding means is counted, and the counted value is compared with a specified number, and the counted value is smaller than the specified number. In this case, predetermined data is output by the difference between the prescribed number and the count value. Thus, even if a code error occurs, predetermined prediction error data is added to the decoded data and output, and the prediction error data is inversely predicted. As a result, error processing can be performed without stopping the decoding processing, and real-time processing can be performed. In addition, by generating image data using surrounding pixels as the predetermined data, it is possible to reduce deterioration in image quality. Furthermore, by adding and outputting prediction error data,
Image data can be generated from peripheral pixels, and image quality degradation can be reduced to minimize the influence of code errors.

According to a second aspect of the present invention, the invention of the first aspect is applied to a configuration using a buffer memory. The number of prediction error data written in the buffer memory is counted and compared with a specified number. Then, when the prediction error data is insufficient, after reading the prediction error data from the buffer memory, predetermined prediction error data is added and output,
The prediction error data is inversely predicted. The buffer memory can absorb the difference in processing speed between the decoding unit and the device that receives the decoded data, and can add predetermined prediction error data without stopping the decoding unit even if a code error occurs. , It is possible to perform real-time processing.

According to the third aspect of the present invention, the buffer memory includes a plurality of memories, and switches between reading and writing of the plurality of memories by detecting a synchronization code in an input code. Can be configured. When a plurality of buffer memories are used as described above, while writing the decoded data output from the decoding means to one memory, it is possible to simultaneously select the memory to which the writing has not been performed and read the code data. it can. When the writing and reading processes are completed,
At the timing when the synchronization code is detected, the buffer memory for which reading has been completed can be used as the buffer memory for writing, and the buffer memory for which writing has been completed can be selected to read the decoded data. The decoding means and the device for receiving the decoded data read from the buffer memory can perform writing and reading according to the respective processing speeds, and can simultaneously perform writing and reading to the memory. Can be improved.

[0017]

[0018]

FIG. 1 is a schematic block diagram showing a first embodiment of a decoding apparatus according to the present invention. In the figure, 1 is code data, 2
Is a decoding processing unit, 3, 5, and 8 are decoded data, 4 is a selector, 6 is a decoded data transmission signal, 7 is an EOL signal, 9 is a control unit, and 10 is a selector switching signal. Decryption processing unit 2
Decodes the input code data 1 and outputs the decoded data 3 to the selector 4. At this time, a decoded data transmission signal 6 is transmitted to the control unit 9. Also, when an EOL indicating the end of one line is detected, an EOL signal 7 is sent to the control unit 9. The control section 9 receives the decoded data transmission signal 6 transmitted from the decoding processing section 2 and counts it by an internal counter. When receiving the EOL signal 7, the control unit 9 compares the count value of the internal counter with a predetermined value, and if the count value is smaller than the predetermined value, the control unit 9 determines the decoded data 8 as a predetermined value. And the selector switching signal 10 is changed so that the selector 4 selects the decoded data 8. The selector 4 is
Based on the selector switching signal 10 from the control unit 9, one of the decoded data 3 output from the decoding processing unit 2 and the decoded data 8 output from the control unit 9 is selected, and the decoded data 5
Output as

FIG. 2 is a flowchart showing an example of the operation of the first embodiment of the decoding apparatus of the present invention. S61
In, the number of decoded data is counted by the counter in the control unit 9 until the end of the line is detected in S62. S
In step 62, upon receiving the EOL signal 7 from the decoding processing unit 2, the process proceeds to S63. In S63, the count value of the counter is compared with a specified value. At this time, if the count value is less than the specified number, it means that the number of data has decreased due to an error in the code. Therefore, when the count value is smaller than the specified value, in S64, the control unit 9
The selector 4 transmits the selector switching signal 10 so that the decoded data 5 is selected, and transmits predetermined data, for example, 0 as the decoded data 5, and adds the insufficient decoded data. Then, the transmitted data is counted by the counter, and the process returns to S63. This process is repeated until the count value of the counter becomes equal to the specified value, that is, until the number of data in one line is reached.

In the above processing example, after detecting the EOL,
Although the count value of the counter was compared with the specified value, the count value was always compared with the specified value.
It is also possible to configure so that the control unit 9 notifies the decoding processing unit 2 to that effect and does not output decoded data of a specified value or more. With this configuration, the number of decoded data to be output is always equal to the specified value. Therefore, when the image data is encoded and transmitted, the decoded image does not shift due to the code error, and the deterioration of the image quality can be suppressed.

FIG. 3 is a schematic diagram showing a second embodiment of the decoding apparatus according to the present invention. In the figure, the same parts as those in FIG. 11 and 12 are buffer memories, and 13 is a selector. In the second embodiment, an example in which two buffer memories 11 and 12 are provided in the output stage of the decoding processing unit 2 is shown. The decoded data 3 output from the decoding processing unit 2 is stored in the buffer memories 11 and 12
Is input to The decoded data transmission signal 6 output from the decoding processing unit 2 is input to the control unit 9 and
The data is input to the buffer memories 11 and 12 and used as a memory write signal. The selector 13 selectively supplies read data from either the buffer memory 11 or 12 to the selector 4.

When one of the buffer memories 11 and 12 is in the write mode, the other is set in the read mode. For example, the buffer memory 11 is in the write mode, and the buffer memory 12 is in the read mode. At this time,
The selector 13 is switched so as to select data from the buffer memory 12. In this state, the decoded data 3 output from the decoding processing unit 2 is written to the buffer memory 11 according to the decoded data transmission signal 6. Simultaneously with the write operation to the buffer memory 11, the buffer memory 12 reads out the stored decoded data in accordance with a read request from a device (not shown) that receives the decoded data 5. At this time, the buffer memory 11
The operation of writing to and the operation of reading from the buffer memory 12 can be performed asynchronously.

When the decoding of one line is completed and the reading of the decoded data is completed, the buffer memory 11,
The mode of the buffer memory 11 is now changed.
Indicates the read mode, and the buffer memory 12 indicates the write mode. At this time, the selector 13 is switched so as to select data from the buffer memory 11. Therefore, the decoded data written to the buffer memory 11 is read, and the newly decoded data is written to the buffer memory 12.

The control unit 9 includes a buffer memory 11 or 1
While data is being written to 2, the number of written decrypted data is counted by an internal counter. And
When the EOL is detected and the writing of one line is completed, the count value of the counter is compared with a specified value to detect excess or deficiency. If excess or deficiency is detected, a code error has occurred. In the next read mode, if the count value is larger than the specified value, only the specified number of decoded data is read from the buffer memory. When the count value is smaller than the specified value, after reading all the decoded data from the buffer memory, predetermined data is output as the decoded data 8 and selector switching is performed so that the selector 4 selects the decoded data 8. A signal 10 is transmitted, and the decoded data corresponding to the shortage is output from the control unit 9. Accordingly, the number of decoded data 5 to be output always becomes a specified value. For example, even when an image is decoded and output, a position shift does not occur and deterioration of image quality can be reduced.

FIG. 4 is a block diagram showing a specific example of a control unit in a second embodiment of the decoding processing device of the present invention.
In the figure, the same parts as those in FIG. 3 are denoted by the same reference numerals. 1
4 is a counter, 15 and 16 are registers, 17 is a count value,
Reference numeral 18 is a prescribed value, 19 is a comparator (CMP), 20 is a comparison result signal, 21 is a sequencer, 22 is a memory read signal, 23 is an AND circuit, and 24 is a clear signal. In this example, the selector 4 in FIG. 3 is configured by the AND circuit 23, and does not require the selector switching signal in FIG.

The code data 1 is decoded by the decoding processing unit 2 into decoded data 3. The decoding processing unit 2 writes the image data 3 into either the buffer memory 11 or 12 using the decoded data transmission signal 6 as a write signal. The buffer memories 11 and 12 switch between a read mode and a write mode for each line.

In the counter 14, the decoded data transmission signal 6
And the count value 17 is written into the register 16 at the end of one line. The register 15 holds the prescribed number of one line of decoded data. At the end of one line, the count value 17 written in the register 16 and the specified value 18 held in the register 15 are compared by the comparator 19, and a comparison result signal 20 is sent to the sequencer 21.

When the sequencer 21 obtains the comparison result signal 20 whose count value 17 is equal to or larger than the specified value 18 based on the comparison result signal 20, the specified value 18 is taken out of the register 15 and the number indicated by the specified value 18 is obtained. The decoded data is read from the buffer memory 11 or 12 and the selector 1
3. Output as decoded data 5 via AND circuit 23. At this time, 1 is transmitted as the clear signal 24. When the count value 17 is smaller than the specified value 18, the decoded data is read from the buffer memory 11 or 12, the clear signal 24 is set to 0, and the decoded data is counted by the number of differences between the specified value 18 and the count value 17. As 5, output 0 data.

FIG. 5 is a flowchart showing an example of the operation of the sequencer 21. After the data writing for one line is completed, first, in S71, when the comparison result signal 20 satisfies the count value ≧ the specified number, in S72, the read number of the decoded data from the buffer memory 11 or 12 is set to the specified number 18. . Thereafter, in S73, data is read out one by one by the memory read signal 22. S7
It is determined whether or not the read number set in step 4 has been reached. If the number has not been reached, the process returns to step S73 to repeat data reading. When the number of readings has been reached, the process ends.

If the comparison result signal 20 satisfies the count value <specified number in S71, first, in S75, the number of reads from the buffer memory 11 or 12 is incremented by the count value 1
7, that is, the number of writes to the buffer memory 11 or 12 is set. Thereafter, in S76, data is read out from the buffer memory 11 or 12 one by one,
At 77, it is determined whether or not the read number set has been reached. While the number of readings has not been reached, the reading of the data in S76 is repeated. Once you have reached the number of reads,
In S78 and S79, the clear signal 24 is output by an amount less than the prescribed number, and the 0-value decoded data 5 is output by the AND circuit 23.

The above operation is repeatedly executed by switching the operation mode of the buffer memories 11 and 12 for each line. By such an operation, even if the decoded data becomes larger or smaller than the specified value due to a code error, decoded data of the specified number is output to the outside. Further, when the decoded data is smaller than the specified value, the error is compensated by the 0 value, so that, for example, even when the image data is decoded, the error can be made inconspicuous. The data to be supplemented is not limited to the 0 value, and a random pattern of 0 and 1 or a value at the end of decoding, or an arbitrary halftone may be output when the image is multi-valued.

In the above description of the operation, the switching of the buffer memories 11 and 12 is performed for each line. However, the present invention is not limited to this. It may be determined according to the conversion method. Further, in the above-described configuration, the case where the number of buffer memories is two is described. However, the number of buffer memories is not limited thereto, and the number of buffer memories may be three or more.

FIG. 6 is a schematic diagram showing a third embodiment of the decoding apparatus according to the present invention. In the figure, the same parts as those in FIG. 1 are denoted by the same reference numerals. 31 is a decoder, 32 is an inverse predictor, 33, 34, and 35 are prediction error data, 36 is a code memory, 37 is a code read signal, 38 is the number of error data,
9 is an AND circuit, 40 is a counter, 41 is a register,
2 is a comparator, 43 is an error data enable signal,
44 is a count value, 45 is a specified number, and 46 is a comparison signal.
This embodiment shows an example in which the present invention is applied to a decoding processing device that decodes predictively encoded code data as shown in FIG. As described with reference to FIG. 8, the decoder 31 performs the decoding process according to the code data 1 and outputs the prediction error data 33. For example, when the code data 1 is run-length encoded, the run-length decoding is performed, and when the arithmetic encoding is performed, the inverse operation of the probability is performed. In other words, this embodiment can be applied to all predictive encoded code data regardless of the encoding method. Inverse predictor 3
2 converts the prediction error data 35 into decoded data 5.

Code data is stored in the code memory 36, and the code data 1 is read out according to the code read signal 37 from the control unit 9 and sent to the decoder 31.
The decoder 31 receives the decoded data 1 and outputs the prediction error data 33 to the AND circuit 39, and also calculates the number of data of the output prediction error data 33 as the number of prediction error data 38
Is output to the control unit 9. When the EOL is received as the decoded data 1, the EOL signal 7 is sent to the control unit 9.
Output to

The control unit 9 outputs the code read signal 37 to the code memory 36, receives the error data number 38 from the decoder 31, and outputs each error data to the inverse predictor 3
2 outputs an error data enable signal 43 to be received. During normal operation, as the prediction error data 34,
1 has been sent. Therefore, the AND circuit 39 outputs the prediction error data 33 to the inverse predictor 32 as the prediction error data 35. Further, the control unit 9 receives the EOL signal 7 from the decoder 31 and the comparison signal 46 from the comparator 42, determines whether or not there is a code error, and performs processing at the time of error. At the time of a code error, 0 is output as the prediction error data 34 and the error data enable signal 43 is output, so that the inverse predictor 32
Is given as prediction error data 35.

The counter 40 receives and counts the error data enable signal 43 output from the control unit 9.
The register 41 stores a specified value. The comparator 42 has a count value 44 counted by the counter 40.
And the specified value 45 stored in the register 41, and sends a comparison signal 46 to the control unit 9.

FIG. 7 is a flowchart showing an example of the operation of the decoding apparatus according to the third embodiment of the present invention.
First, in S81, the control unit 9 sends the code memory 36
, A code read signal 37 is output, and one code is input to the decoder 31. In S82, it is determined whether or not the input code is EOL.
At the same time, the prediction error data 33 is output from the decoder 31, and at the same time, the control unit 9 outputs an error data enable signal 43 indicating that the error data has been output. The error data enable signal 43 is output from the counter 4
The number of data that is also input to 0 and output by the decoder 31 is counted.

In S84, the count value 44 counted by the counter 40 and the specified value 45 stored in the register 41
Are compared by the comparator 42. If the count value does not reach the specified number, it is determined in S85 whether or not decoding for one code has been completed. If not, the process returns to S83 and decoding for one code is repeated. Upon completion of the decoding process on one code, the process returns to S81 and
The next code is read from the code memory 36, and the same processing is performed.

Now, as a result of reading the code from the code memory 36, if EOL is detected in S82,
The process of S87 is performed. When the process proceeds to S86, the count value is not equal to the specified number in the determination of the count value in S84. From this, it can be determined that the decoding of one line has not been performed normally and the number of data has decreased. Therefore, while the count value is smaller than the specified number in S86, the error data enable signal 43 is output in S87, and 0 is output as the prediction error data 34. As a result, the prediction error data 35 becomes 0 by the AND circuit 39. This operation is repeated until the count value of the counter 40 reaches the specified number, and then ends.

Next, at S84, the count value =
When the predetermined number is reached, the processing of S88 and S89 is performed. When the process proceeds to S88, if the next code is EOL, it can be determined that decoding has been performed normally. However, if the next code is not EOL, it can be determined that decoding of one line has not been performed normally and the number of data has increased. Therefore, only the reading of the code is performed in S88 and the error data enable signal 43 is not output until the EOL is detected in S89.

With these controls, even if there is an error in the code, if the prediction error data is smaller than the specified value, 0 is output to the prediction error data, or the prediction error data larger than the specified value is deleted. , And outputs a prescribed number of prediction error data. Thus, for example, when image data is decoded, the number of pixels becomes a specified number, and it is possible to prevent a position shift or the like due to a code error and suppress a decrease in image quality. Further, since processing for a code error is performed without rereading the code memory 36, real-time decoding processing can be performed.

When there is an error in the code and normal decoding cannot be performed, 0 is given to the inverse predictor 32 as prediction error data, so that the inverse predictor 32 generates image data from neighboring pixels. Therefore, for example, when image data is decoded, deterioration of image quality is reduced. This allows
The effect of the code error can be minimized.

In FIG. 6, a line end signal indicates
Although the number of data is determined, the present invention is not limited to this. When the code uses an arithmetic coding method, every time a marker code for every several lines used in the arithmetic code is detected, The configuration may be such that the number of data is determined. Further, after detecting EOL, not only outputting 0 to the prediction error data, but also detecting an undecodable error code during decoding, detecting EOL from that point, or until reaching a specified number. , 0 as the prediction error data
Can also be output.

In the configuration shown in FIG.
It is also possible to configure the selector 9 by a selector and switch the selector 9 by a selector switching signal from the controller 9.
In this case, data other than 0 can be supplied to the inverse predictor 32 as prediction error data at the time of a code error.
Further, in the configuration shown in FIG. 6, the error data enable signal 43 is output from the control unit 9, but is output from the decoder 31, and the control unit 9, the inverse predictor 32, and the counter 40 output the error data enable signal 43. Can also be configured to receive At this time, the error data number 38 is unnecessary. Further, the code memory 36 may not be used, and the code may be directly input to the decoder 31.

FIG. 6 shows a configuration in which a buffer memory is not used. However, as shown in FIGS. 3 and 4, a plurality of buffer memories are arranged at the subsequent stage of the decoder 31, and the control unit 9 shown in FIG. It is also possible to configure such that the control described above is also performed.

[0046]

As is apparent from the above description, according to the present invention, when an error is found in a code, prediction error data is added or deleted without retransmission, and only a specified number is output and inversely performed. Since the prediction is performed, there is an effect that the processing can be performed in real time and the speed can be extremely increased. Also,
Since only the specified number is output, when the image data is decoded, it is possible to prevent the image from shifting due to an error in the number of decoded data. Further, by adding and outputting the prediction error data, image data can be generated from neighboring pixels, and the deterioration of image quality can be reduced to minimize the influence of code errors.

Particularly, in the case of a code such as arithmetic coding, Huffman coding, or the like, in which an error has occurred for the first time depending on the number of decoding when a marker code is detected, in the prior art, after detecting the marker code, Since all the decoded data must be discarded, the speed of the entire decoding process has been reduced. Moreover, if a transmission error frequently occurs, data cannot be decoded. However, according to the present invention, an image can be decoded in real time even if there is some disturbance.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing a first embodiment of a decoding processing device of the present invention.

FIG. 2 is a flowchart illustrating an example of an operation of the decoding processing device according to the first exemplary embodiment of the present invention.

FIG. 3 is a schematic configuration diagram showing a second embodiment of the decoding processing device of the present invention.

FIG. 4 is a block diagram illustrating a specific example of a control unit in a second embodiment of the decoding processing device of the present invention.

FIG. 5 is a flowchart showing an example of the operation of the sequencer 21.

FIG. 6 is a schematic configuration diagram showing a third embodiment of the decoding processing device of the present invention.

FIG. 7 is a flowchart illustrating an example of an operation of the decoding processing device according to the third exemplary embodiment of the present invention.

FIG. 8 is a block diagram illustrating an example of a decoding process of predictively encoded code data.

FIG. 9 is a block diagram illustrating an example of a conventional decoding processing device using a buffer memory.

FIG. 10 is a block diagram illustrating an example of a conventional decoding processing device for predictively encoded code data using a buffer memory.

[Explanation of symbols]

1 code data, 2 decoding processing unit, 3, 5, 8 decoded data, 4 selector, 6 decoded data transmission signal, 7 E
OL signal, 9: control unit, 10: selector switching signal, 1
1, 12 buffer memory, 13 selector, 14 counter, 15, 16 register, 17 count value, 18
Specified value, 19: comparator (CMP), 20: comparison result signal, 21: sequencer, 22: memory read signal,
23 ... AND circuit, 24 ... clear signal, 31 ... decoder,
32: inverse predictor, 33, 34, 35: prediction error data,
36 code memory, 37 code read signal, 38 error data number, 39 AND circuit, 40 counter, 41
Register, 42 ... Comparator, 43 ... Error data enable signal, 44 ... Count value, 45 ... Specified number, 46 ... Comparison signal.

Claims (3)

(57) [Claims] 1. An image decoding processing apparatus for decoding an input code, comprising: decoding means for decoding the input code into prediction error data; counting means for counting the number of prediction error data decoded by the decoding means; Comparing means for comparing the count value of the counting means with a specified number; controlling the output number of the prediction error data decoded by the decoding means based on the comparison result by the comparing means; An image decoding processing apparatus comprising: a control unit that outputs predetermined prediction error data by a difference between a prescribed number and a count value in a case; and a reverse prediction unit that performs reverse prediction based on the prediction error data. 2. An image decoding processing apparatus for decoding an input code, a decoding means for decoding the input code into prediction error data, a buffer memory for temporarily storing the prediction error data decoded by the decoding means, and a buffer memory Counting means for counting the number of data when the prediction error data decoded by the decoding means is written to the buffer memory; comparing means for comparing the count value of the counting means with a prescribed number; and the buffer memory based on the comparison result by the comparing means. And when the count value by the counting means is smaller than a specified number, reads out the predicted error data from the buffer memory up to the counted value, and then outputs predetermined predicted error data by the difference between the specified number and the count value. An image decoding method comprising: control means; and inverse prediction means for performing inverse prediction based on the prediction error data. No. processing unit. 3. The buffer memory according to claim 1, wherein the buffer memory includes a plurality of memories, and includes a switching unit that switches between reading and writing of the plurality of memories by detecting a synchronization code in an input code. Claim 2
An image decoding processing device according to item 1.