KR100362504B1 - Method for manufacturing chip size package - Google Patents
Method for manufacturing chip size package Download PDFInfo
- Publication number
- KR100362504B1 KR100362504B1 KR1019960001240A KR19960001240A KR100362504B1 KR 100362504 B1 KR100362504 B1 KR 100362504B1 KR 1019960001240 A KR1019960001240 A KR 1019960001240A KR 19960001240 A KR19960001240 A KR 19960001240A KR 100362504 B1 KR100362504 B1 KR 100362504B1
- Authority
- KR
- South Korea
- Prior art keywords
- wire
- bond pad
- semiconductor chip
- tape
- csp
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
본 발명은 반도체 칩의 실크기 정도로 제조되는 반도체 패키지인 CSP(ChipSize Package)의 제조방법에 대한 것이다.The present invention relates to a method for manufacturing a chip size package (CSP), which is a semiconductor package manufactured to a silk level of a semiconductor chip.
일반적으로 실장업계에서는 사방으로 리드(Lead)를 설치할 수 있는 납작한 형상의 반도체 패키지인 QFP(Quad Flat Package) 제조 기술이 널리 알려져 있다.In general, in the mounting industry, a technology for manufacturing a quad flat package (QFP), which is a flat semiconductor package capable of installing leads in all directions, is widely known.
그러나, 최근 전자기기의 소형화, 박형화 다기능화의 추세에 따라 반도체 칩의 고집적화가 이루어지고 그에 따라 많은 수의 리드를 갖는 초소형의 반도체 패키지가 절실히 요구되고 있는 실정이지만 위의 QFP 기술로는 리드피치(Lead Pitch) 0.3mm 이하의 가공 기술을 극복하지 못한 채 연구만을 거듭하던 중 미국에서 리드 대신 볼(Ball)을 이용하는 BGA(Ball Grid Array)기술이 출현하여 하나의 패키지를 통해 무수히 많은 출력단자를 실장할 수 있다는 장점을 가지고 반도체 시장에 투입되어 많은 화제를 일으켜 왔다. 그러나, BGA도 결국의 경우는 화제만큼 많은 채용이 이루어질 못했다. 왜냐하면 1.5mm피치(Pitch) 제품의 경우는 패키지 사이즈가 크고 게다가 두꺼워 소형, 박형으로의 다기능을 가는 전자기기에는 그 수용이 적합하지 않고, 그 밖에 가격이 높으며(QFP의 10배 이상), 내부 배선처리가 길고 방열의 문제를 쉽게 해결할 수 없는 등 실용상의 어려움이 있었다.However, with the recent trend of miniaturization and thinning of electronic devices, high integration of semiconductor chips has been achieved, and accordingly, a miniature semiconductor package having a large number of leads is desperately required. Lead Pitch) In the United States, the BGA (Ball Grid Array) technology, which uses balls instead of leads, appeared in the United States. It has been brought into the semiconductor market with the advantage of being able to do so and has caused a lot of topics. However, in the event of the BGA, as many as the topic was not adopted. Because the 1.5mm pitch product is large and thick, it is not suitable for small and thin multifunctional electronic devices, and the price is high (more than 10 times of QFP). There were difficulties in practical use such as the long processing and the problem of heat dissipation not easily solved.
특히, 반도체 칩을 실장함에 있어서의 칩의 입출력(I/O)을 외부 단자에 연결하기 위해서는 와이어본딩(Wire Bonding)이나 범핑(Bumping)공정을 거쳐야 하는 바, 이러한 와이어 본딩공정을 수반하는 패키지 제조방법을 반도체칩 패드가 반도체 칩의 주변에 위치해야 하므로 입출력(I/O)의 수가 제한을 받으며, 또한 범핑은 범프(Bump)가 상존하는 단점을 수반하게 되는 등 패키지의 제조면에 있어서도 많은 문제점을 안고 있었다.In particular, in order to connect the input / output (I / O) of the chip to an external terminal in mounting a semiconductor chip, a wire bonding or bumping process must be performed, and a package accompanying the wire bonding process is manufactured. The method is limited in the number of input / output (I / O) because the semiconductor chip pad should be located around the semiconductor chip, and also bumping is accompanied with the disadvantage that the bump (existing bump) is present, many problems in the manufacturing of the package. Was hugging.
한편, 이러한 시기에 새로운 연구과제로 등장하게 된 것이 CSP이다.Meanwhile, CSP emerged as a new research project at this time.
그러나, CSP는 그 크기가 칩 사이즈와 비슷하게 제조되므로 작업공간이 거의 없어 회로패턴이 인쇄된 기판(2)과 반도체 칩(1)상의 본드패드(1a)를 바로 연결(Bonding)한다는 것은 거의 불가능하다고 볼 수 있다.However, since the CSP is manufactured in the same size as the chip size, it is almost impossible to directly bond the substrate 2 on which the circuit pattern is printed and the bond pad 1a on the semiconductor chip 1 because there is little work space. can see.
따라서, 본 발명에서는 이러한 칩 사이즈 크기의 CSP를 제조함에 있어서 문제로 제기되고 있는 반도체 칩과 회로패턴이 인쇄된 기판간의 와이어본딩 문제를 쉽게 해결함으로써 CSP의 제조를 용이하게 하고, 아울러 이의 양산이 가능하도록 한 것이다.Therefore, the present invention facilitates the manufacture of the CSP by easily solving the wire bonding problem between the semiconductor chip and the circuit pattern printed substrate, which is a problem in manufacturing such a chip size CSP, and mass production thereof is possible. I did it.
이하, 본 발명의 제조방법을 비한정의 첨부 예시 도면에 의거 상세히 설명하면 다음과 같다.Hereinafter, the manufacturing method of the present invention will be described in detail with reference to the accompanying non-limiting example drawings.
먼저 회로패턴이 인쇄된 기판(2)에 와이어(3)를 연결한다.First, the wire 3 is connected to the substrate 2 on which the circuit pattern is printed.
와이어(3)가 연결된 기판(2) 위에 일정간격으로 두고 반도체 칩(1)의 본드패드(1a) 부위가 밑으로 가도록 배치한다.It is placed on the substrate 2 to which the wire 3 is connected at a predetermined interval so that the portion of the bond pad 1a of the semiconductor chip 1 faces downward.
이때 와이어(3)가 반도체 칩(1) 상의 본드패드(1a)밑을 지나가도록 프로그램에 의한 배선을 하여 준비된 테이프(4)에 가본딩을 실시한다. (기존의 와이어 본딩설비 이용가능)At this time, temporary bonding is performed to the prepared tape 4 by wiring by program so that the wire 3 passes under the bond pad 1a on the semiconductor chip 1. (Existing wire bonding equipment available)
그리고 반대로 로딩시켜 반도체 칩(1)의 본드패드(1a)위로 배선된 와이어(3)를 쐐기본딩(Wedge Bonding)시켜 본드패드(1a)와 연결시킨다.In addition, the wire 3 wired on the bond pad 1a of the semiconductor chip 1 is loaded by wedge bonding and connected to the bond pad 1a.
그 다음 반도체 칩(1)과 회로패턴이 인쇄된 기판(2) 사이를 수지(5)로 밀봉 충전한다. 그리고 나서, 가본딩된 테이프(필름테이프)를 제거하고, 기판(2)의 회로출력에 솔더볼(6)을 부착하게 되면 제3도 도시의 본 발명의 CSP가 완성되는 것이다.Then, sealing filling is performed between the semiconductor chip 1 and the substrate 2 on which the circuit pattern is printed with resin 5. Then, when the bonded tape (film tape) is removed and the solder balls 6 are attached to the circuit output of the substrate 2, the CSP of the present invention shown in FIG. 3 is completed.
여기서 가본딩된 테이프(4)를 제거함에는 수지(5)의 충전 전에 실시할 수도 있고, 충전 후에 실시할 수도 있다.The removal of the temporarily bonded tape 4 may be performed before filling the resin 5 or after filling.
이와 같이, 본 발명의 CSP 제조방법에 의하면 회로패턴이 인쇄된 기판(2)과 반도체 칩(1)상의 본드패드(1a)를 와이어(3)로 연결함에 있어, 테이프(4)를 사용하여 가본딩 후 쐐기본딩 수단에 의한 와이어(3)와 본드패드(1a)간의 접속이 이루어지도록 하는 새로운 와이어 본딩방법을 채용함으로써, 반도체 칩의 디자인 패턴에 관계없이 작업이 가능하며, 또한 기존의 와이어 본딩 설비를 이용할 수 있고, 로딩방법이 용이해짐으로써 제품의 대량생산이 가능해질 수 있는 것이다.As described above, according to the CSP manufacturing method of the present invention, when the substrate 2 on which the circuit pattern is printed and the bond pad 1a on the semiconductor chip 1 are connected with the wire 3, the tape 4 is used. By adopting a new wire bonding method that allows the connection between the wire 3 and the bond pad 1a by the wedge base unit after bonding, work can be performed regardless of the design pattern of the semiconductor chip, and existing wire bonding facilities It can be used, the mass loading of the product can be enabled by the easy loading method.
제1도는 본 발명에 있어서, 와이어를 테이프에 가본딩시킨 상태를 보여주는 예시도.1 is an exemplary view showing a state in which the wire is bonded to the tape in the present invention.
제2도는 제1도의 상태에서 반도체 칩 상의 본드패드 위를 지나는 와이어를 쐐기본딩한 예시도.FIG. 2 is an exemplary diagram in which the wires passing over the bond pads on the semiconductor chip in the state of FIG.
제3도는 제2도에서 반도체 칩과 회로패턴이 인쇄된 기판 사이를 수지로 밀봉한 전후 가본딩용 테이프를 제거시킨 상태로 본 발명에 의해 제조된 반도체 패키지 구성도.FIG. 3 is a schematic view of a semiconductor package manufactured by the present invention in a state in which the tapes for front and back bonding in which the semiconductor chip and the circuit pattern printed circuit board are sealed with resin in FIG.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1 ; 반도체 칩 1a ; 본드패드One ; Semiconductor chip 1a; Bond pad
2 ; 기판 3 ; 와이어2 ; Substrate 3; wire
4 ; 테이프 5 ; 수지4 ; Tape 5; Suzy
6 ; 솔더볼6; Solder ball
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960001240A KR100362504B1 (en) | 1996-01-22 | 1996-01-22 | Method for manufacturing chip size package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960001240A KR100362504B1 (en) | 1996-01-22 | 1996-01-22 | Method for manufacturing chip size package |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019950053425 Division | 1995-12-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970053642A KR970053642A (en) | 1997-07-31 |
| KR100362504B1 true KR100362504B1 (en) | 2003-01-29 |
Family
ID=37490744
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960001240A KR100362504B1 (en) | 1996-01-22 | 1996-01-22 | Method for manufacturing chip size package |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100362504B1 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4771330A (en) * | 1987-05-13 | 1988-09-13 | Lsi Logic Corporation | Wire bonds and electrical contacts of an integrated circuit device |
| JPH03240248A (en) * | 1990-02-19 | 1991-10-25 | Fujitsu Ltd | Semiconductor device |
| KR950015272A (en) * | 1993-11-16 | 1995-06-16 | 배순훈 | How to schedule recording of V seed |
-
1996
- 1996-01-22 KR KR1019960001240A patent/KR100362504B1/en not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4771330A (en) * | 1987-05-13 | 1988-09-13 | Lsi Logic Corporation | Wire bonds and electrical contacts of an integrated circuit device |
| JPH03240248A (en) * | 1990-02-19 | 1991-10-25 | Fujitsu Ltd | Semiconductor device |
| KR950015272A (en) * | 1993-11-16 | 1995-06-16 | 배순훈 | How to schedule recording of V seed |
Also Published As
| Publication number | Publication date |
|---|---|
| KR970053642A (en) | 1997-07-31 |
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