KR100358175B1 - Method of fabricating tungsten bit line of semiconductor device - Google Patents
Method of fabricating tungsten bit line of semiconductor device Download PDFInfo
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- KR100358175B1 KR100358175B1 KR1019980058568A KR19980058568A KR100358175B1 KR 100358175 B1 KR100358175 B1 KR 100358175B1 KR 1019980058568 A KR1019980058568 A KR 1019980058568A KR 19980058568 A KR19980058568 A KR 19980058568A KR 100358175 B1 KR100358175 B1 KR 100358175B1
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- Prior art keywords
- bit line
- tungsten
- layer
- silicon layer
- sacrificial silicon
- Prior art date
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 title claims abstract description 39
- 229910052721 tungsten Inorganic materials 0.000 title claims abstract description 39
- 239000010937 tungsten Substances 0.000 title claims abstract description 39
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 41
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 41
- 239000010703 silicon Substances 0.000 claims abstract description 41
- 239000010410 layer Substances 0.000 claims abstract description 35
- 238000000034 method Methods 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 230000008569 process Effects 0.000 claims abstract description 21
- 239000012790 adhesive layer Substances 0.000 claims abstract description 18
- 239000011229 interlayer Substances 0.000 claims abstract description 11
- 230000004888 barrier function Effects 0.000 claims abstract description 10
- 238000009792 diffusion process Methods 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 5
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 239000010936 titanium Substances 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 239000010941 cobalt Substances 0.000 claims description 2
- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- 238000005240 physical vapour deposition Methods 0.000 claims description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 2
- 230000006866 deterioration Effects 0.000 abstract description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 abstract 2
- 239000004408 titanium dioxide Substances 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 229920005591 polysilicon Polymers 0.000 description 11
- 238000000206 photolithography Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 2
- 229910008486 TiSix Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76858—After-treatment introducing at least one additional element into the layer by diffusing alloying elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 소정영역에 활성영역을 구비한 반도체기판상에 층간절연막을 형성하는 단계와, 상기 층간절연막을 선택적으로 식각하여 상기 활성영역을 노출시키는 비트라인 콘택을 형성하는 단계, 상기 비트라인 콘택을 포함한 기판 전면에 희생실리콘층을 형성하는 단계, 텅스텐 비트라인을 위한 접착층과 확산방지막을 상기 희생실리콘층상에 형성하는 단계, 상기 비트라인 콘택이 매립되도록 기판 전면에 텅스텐을 증착하는 단계, 상기 텅스텐막을 패터닝하여 텅스텐 비트라인을 형성하는 단계, 및 상기 희생실리콘층이 상기 활성 영역을 대신해서 상기 접착층과 반응하여 상기 희생실리콘층이 모두 소진되어 금속실리사이드로 형성되도록 열공정을 실시하는 단계를 포함하여 구성되는 텅스텐 비트라인 제조방법을 제공함으로써 후속 열공정시에 상기 희생실리콘층이 활성영역의 실리콘을 대신해서 접착층인 타이타늄과 반응함으로써 실리콘 기판 활성 영역의 손실을 억제하여 후속 열공정을 거친 후에도 비트라인 콘택 전기적 특성의 저하를 방지한다.The present invention provides a method of forming an interlayer insulating film on a semiconductor substrate having an active region in a predetermined region, selectively etching the interlayer insulating layer to form a bit line contact to expose the active region, and forming the bit line contact. Forming a sacrificial silicon layer on the entire surface of the substrate, forming an adhesive layer and a diffusion barrier layer on the sacrificial silicon layer, depositing tungsten on the entire surface of the substrate so that the bit line contacts are embedded, and the tungsten film Patterning to form a tungsten bitline, and performing a thermal process such that the sacrificial silicon layer reacts with the adhesive layer in place of the active region so that the sacrificial silicon layer is exhausted to form metal silicide. By providing a method for manufacturing a tungsten bit line that Sacrificial silicon layer is to prevent the deterioration of the adhesive layer of titanium dioxide by reaction with bit line contact electrical characteristic after to suppress the loss undergone subsequent thermal processing of the silicon substrate in place of the silicon active region of the active area.
Description
본 발명은 반도체소자 제조방법에 관한 것으로, 특히 소자의 동작속도 향상을 목적으로 하는 텅스텐 비트라인 제조공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly to a tungsten bit line manufacturing process for the purpose of improving the operation speed of the device.
종래의 DRAM소자의 텅스텐 비트라인은 도 1c에 도시한 바와 같이 실리콘 기판의 활성영역(1)과 접촉하고 있는 플러그 폴리실리콘(Plug Polycrystalline Silicon, 4)위에 텅스텐층(7)이 형성된 구조를 갖는다. 이의 제조공정을 도 1a 내지 1c를 참조하여 설명하면 다음과 같다.The tungsten bit line of the conventional DRAM device has a structure in which a tungsten layer 7 is formed on a plug polycrystalline silicon 4 which is in contact with the active region 1 of the silicon substrate as shown in FIG. 1C. The manufacturing process thereof will be described with reference to FIGS. 1A to 1C.
먼저, 도 1a에 도시한 바와 같이 실리콘기판상에 게이트절연막을 개재하여 워드라인(2)을 형성한 후, 그 전면에 층간절연막(3)을 형성하고 이를 사진식각공정을 통하여 선택적으로 식각하여 비트라인 콘택을 형성한다.First, as shown in FIG. 1A, a word line 2 is formed on a silicon substrate through a gate insulating film. Then, an interlayer insulating film 3 is formed on the entire surface thereof, and the bit is selectively etched through a photolithography process. Form a line contact.
이어서 도 1b를 참조하면, 기판 전면에 폴리실리콘을 증착한 후, 식각 혹은 화학·기계적 연마(CMP; Chemical Mechanical Polishing)공정을 통해서 상기 층간절연막(3) 표면상에 형성된 상기 폴리실리콘층을 제거하고 비트라인 콘택내에 폴리실리콘 플러그(4)를 형성한다.1B, after depositing polysilicon on the entire surface of the substrate, the polysilicon layer formed on the surface of the interlayer insulating film 3 is removed by etching or chemical mechanical polishing (CMP) process. A polysilicon plug 4 is formed in the bit line contact.
다음에 도 1c를 참조하면, 상기 층간절연막(3) 및 폴리실리콘 플러그(4) 상부에 접착층(Glue Layer, 5)과 확산방지막(Diffusion Barrier Layer, 6)을 차례로 형성한 후, 이 위에 텅스텐을 증착하고 사진식각 공정을 통해서 텅스텐 비트라인(7)을 형성한다.Next, referring to FIG. 1C, an adhesive layer (Glue Layer) 5 and a diffusion barrier layer (6) are sequentially formed on the interlayer insulating film 3 and the polysilicon plug 4, and then tungsten is deposited thereon. The tungsten bit line 7 is formed through deposition and photolithography.
상기와 같은 종래의 방법은 텅스텐(7)과 실리콘 기판의 활성 영역(1)이 직접적으로 접촉한 상태에서 후속 열공정을 거칠 때 발생하는 전기적 특성의 저하를 방지하기 위해 그 사이에 플러그 폴리실리콘(4)을 삽입하였다. 이 방법은 폴리실리콘 증착공정과 식각 혹은 화학·기계적 연마 공정이 추가되어 공정 비용이 높다는 단점뿐만 아니라 텅스텐 비트라인이 상대적으로 높은 비저항을 갖는 플러그 폴리실리콘(4)을 사이에 두고 실리콘 기판 활성 영역(1)접촉하고 있다는 점에서 소자 속도 향상 측면에서 불리하다.The conventional method as described above uses a plug polysilicon between the tungsten 7 and the active region 1 of the silicon substrate to prevent deterioration of the electrical characteristics that occur when the thermal process is subsequently performed. 4) was inserted. This method is not only disadvantageous in that the process cost is high due to the addition of polysilicon deposition process and etching or chemical and mechanical polishing process, but also the active area of the silicon substrate with the plug polysilicon 4 having the relatively high resistivity of the tungsten bit line. 1) It is disadvantageous in terms of device speed improvement in that it is in contact.
종래의 텅스텐 비트라인 공정에서 플러그 폴리실리콘(4) 공정을 생략하고 텅스텐(7)을 실리콘 기판 활성영역(1)에 직접 접촉하기 위해서 해결해야 할 문제는 후속 열공정에 따른 실리콘 기판 활성 영역(1)의 손실을 최대한 억제하는 것이다. 실리콘 활성영역(1)의 손실은 텅스텐의 접착층(5)으로 사용되는 타이타늄(Titanium, Ti)이 후속 열 공정에서 타이타늄 실리사이드(Titanium Silicide; TiSix)로 상 전이(Phase Transition)하면서 실리콘 기판 활성 영역(1)을 침투하여 발생하는 것이다.In the conventional tungsten bit line process, the problem to be solved in order to omit the plug polysilicon 4 process and directly contact the tungsten 7 to the silicon substrate active region 1 is to solve the silicon substrate active region 1 according to a subsequent thermal process. ) As much as possible. The loss of the silicon active region 1 is due to the phase transition of titanium (Ti) used as the adhesive layer 5 of tungsten to titanium silicide (TiSix) in a subsequent thermal process. 1) It is caused by penetration.
본 발명은 상술한 문제를 해결하기 위한 것으로, 희생층 실리콘을 타이타늄과 실리콘 기판 활성 영역사이에 삽입하여 후속 열공정시에 활성영역의 실리콘을 대신해서 타이타늄과 반응함으로써 실리콘 기판 활성 영역의 손실을 억제하여 후속 열공정을 거친 후에도 비트라인 콘택 전기적 특성의 저하를 방지할 수 있도록 하는 반도체소자의 텅스텐 비트라인 제조방법에 관한 것이다.The present invention is to solve the above-described problem, by inserting the sacrificial layer silicon between the titanium and the silicon substrate active region to suppress the loss of the silicon substrate active region by reacting with titanium instead of the silicon of the active region during the subsequent thermal process The present invention relates to a method for manufacturing a tungsten bit line of a semiconductor device which can prevent the degradation of bit line contact electrical properties even after a subsequent thermal process.
상기 목적을 달성하기 위한 본 발명의 반도체소자의 텅스텐 비트라인 제조방법은 소정영역에 활성영역을 구비한 반도체기판상에 층간절연막을 형성하는 단계와, 상기 층간절연막을 선택적으로 식각하여 상기 활성영역을 노출시키는 비트라인 콘택을 형성하는 단계, 상기 비트라인 콘택을 포함한 상기 반도체기판 전면에 희생실리콘층을 형성하는 단계, 상기 희생실리콘층상에 텅스텐 비트라인을 위한 접착층과 확산방지막을 순차적으로 형성하는 단계, 상기 비트라인 콘택이 매립되도록 상기 반도체기판 전면에 텅스텐을 증착하는 단계, 상기 텅스텐을 패터닝하여 텅스텐 비트라인을 형성하는 단계, 및 상기 희생실리콘층이 상기 활성 영역을 대신해서 상기 접착층과 반응하여 상기 희생실리콘층이 모두 소진되어 금속실리사이드로 형성되도록 열공정을 실시하는 단계를 포함하여 구성된다.A method of manufacturing a tungsten bit line of a semiconductor device of the present invention for achieving the above object comprises the steps of forming an interlayer insulating film on a semiconductor substrate having an active region in a predetermined region, and selectively etching the interlayer insulating film to form the active region. Forming an exposed bit line contact, forming a sacrificial silicon layer on the entire surface of the semiconductor substrate including the bit line contact, sequentially forming an adhesive layer and a diffusion barrier layer on the sacrificial silicon layer for tungsten bit lines; Depositing tungsten on the entire surface of the semiconductor substrate so that the bit line contacts are buried, patterning the tungsten to form a tungsten bitline, and the sacrificial silicon layer reacts with the adhesive layer in place of the active region to provide the sacrificial layer All of the silicon layers are exhausted to form metal silicide It is configured to include the step of conducting.
도 1a 내지 1c는 종래기술에 의한 반도체소자의 텅스텐 비트라인 제조방법을 도시한 공정순서도,1A to 1C are process flowcharts showing a tungsten bit line manufacturing method of a semiconductor device according to the prior art;
도 2a 내지 2f는 본 발명에 의한 반도체소자의 텅스텐 비트라인 제조방법을 도시한 공정순서도.2A to 2F are process flowcharts showing a tungsten bit line manufacturing method of a semiconductor device according to the present invention;
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
1.활성영역 2.워드라인1.Active Area 2.Wordline
3.층간절연막 4.폴리실리콘 플러그3. Interlayer insulating film 4. Polysilicon plug
5.접착층 6.확산방지막5.Adhesive layer 6.Diffusion barrier
7.텅스텐층 8.희생실리콘층7.Tungsten layer 8.Sacrifice silicon layer
9.금속실리사이드9.metal silicide
도 2a 내지 2f에 본 발명에 의한 플러그 폴리실리콘을 사용하지 않는 직접 접촉 텅스텐 비트라인을 형성하는 방법을 나타내었다.2A to 2F illustrate a method of forming a direct contact tungsten bit line without using plug polysilicon according to the present invention.
먼저, 도 2a를 참조하면, 소정영역에 활성영역(1)을 구비한 반도체기판상에 게이트절연막을 개재하여 워드라인(2)을 형성한 후, 그 전면에 층간절연막(3)을 형성하고 이를 사진식각 공정을 통해서 선택적으로 식각하여 상기 활성영역(1)을 노출시키는 비트라인 콘택을 형성한다.First, referring to FIG. 2A, a word line 2 is formed on a semiconductor substrate having an active region 1 in a predetermined region through a gate insulating film. Then, an interlayer insulating film 3 is formed on the entire surface thereof. The photolithography process may selectively etch a bit line to expose the active region 1.
이어서 도 2b를 참조하면, 상기 비트라인 콘택을 포함한 기판 전면에 희생실리콘층(8)을 형성한다. 희생실리콘층(8)은 비정질 또는 결정질실리콘으로 형성하며, 그 두께는 100-500Å정도로 형성한다. 또한 희생실리콘층(8)은 물리적 기상증착법 또는 화학적기상증착법으로 형성하는 것이 바람직하다.Next, referring to FIG. 2B, a sacrificial silicon layer 8 is formed on the entire surface of the substrate including the bit line contact. The sacrificial silicon layer 8 is formed of amorphous or crystalline silicon, the thickness of which is formed to about 100-500Å. In addition, the sacrificial silicon layer 8 is preferably formed by physical vapor deposition or chemical vapor deposition.
다음에 도 2c를 참조하면, 텅스텐 비트라인을 반도체기판에 접착시키기위한 접착층(5)과 확산방지막(6)을 상기 희생실리콘층(8)상에 형성한다. 상기 접착층은 타이타늄(Ti), 코발트(Co), 텅스텐(W) 또는 몰리브덴(Mo)으로 형성할 수 있으며, 확산방지막은 타이타늄질화막(TiN)이나 탄탈륨 질화막(TaN)으로 형성할 수 있다. 상기 접착층(5)과 확산방지막(6) 형성후 고온 열처리를 행하지 않는다.Next, referring to FIG. 2C, an adhesive layer 5 and a diffusion barrier 6 for attaching a tungsten bit line to a semiconductor substrate are formed on the sacrificial silicon layer 8. The adhesive layer may be formed of titanium (Ti), cobalt (Co), tungsten (W) or molybdenum (Mo), and the diffusion barrier may be formed of a titanium nitride film (TiN) or a tantalum nitride film (TaN). After the adhesive layer 5 and the diffusion barrier 6 are formed, a high temperature heat treatment is not performed.
이어서 도 2d를 참조하면, 상기 비트라인 콘택이 매립되도록 기판 전면에 텅스텐(7)을 증착한다.2D, tungsten 7 is deposited on the entire surface of the substrate to fill the bit line contact.
다음에 도 2e를 참조하면, 상기 텅스텐막(7)과 확산방지막(6) 및 접착층(5)을 사진식각공정을 통해 소정의 비트라인 패턴으로 패터닝하여 텅스텐 비트라인(7)을 형성한다.Next, referring to FIG. 2E, the tungsten film 7, the diffusion barrier 6, and the adhesive layer 5 are patterned into a predetermined bit line pattern through a photolithography process to form a tungsten bit line 7.
이어서 도 2f를 참조하면, 후속 열공정시 상기 희생실리콘층(8)이 활성 영역(1)의 실리콘을 대신해서 상기 접착층(5)과 반응하도록 함으로써 금속실리사이드(9)를 형성한다. 상기 후속 열공정은 커패시터 제조공정시의 열공정이다.Referring next to FIG. 2F, the metal silicide 9 is formed by causing the sacrificial silicon layer 8 to react with the adhesive layer 5 in place of the silicon in the active region 1 in a subsequent thermal process. The subsequent thermal process is a thermal process in the capacitor manufacturing process.
본 발명은 상술한 바와 같이 희생실리콘층(8)을 접착층(5)과 실리콘기판의 활성영역(1) 사이에 삽입하여 후속 열공정시에 활성영역(1)의 실리콘을 대신해서 접착층인 Ti와 반응하게 한다. 즉, 실리콘기판 활성영역(1)의 손실을 억제함으로써 후속 열공정을 거친 후에도 비트라인콘택의 전기적특성의 저하를 방지한다.As described above, the present invention inserts the sacrificial silicon layer 8 between the adhesive layer 5 and the active region 1 of the silicon substrate and reacts with Ti, which is an adhesive layer, in place of the silicon of the active region 1 during the subsequent thermal process. Let's do it. That is, the loss of the silicon substrate active region 1 is suppressed to prevent the deterioration of the electrical characteristics of the bit line contacts even after the subsequent thermal process.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
본 발명에 의하면, 텅스텐 비트라인이 플러그 폴리실리콘과 연결되는 일 없이 순수하게 텅스텐만으로 구성됨으로써 소자의 동작속도 향상이 기대된다. 그리고 비트라인을 실리콘 기판 활성 영역(1)에 직접적으로 접촉시킬 수 있어 주변 영역(Peripheral Region)에서 비트라인을 금속콘택 패드로도 이용할 수 있는데, 이는 DRAM 소자의 크기 감소에 따른 금속콘택 공정의 여러 가지 문제점(예, 금속 콘택 깊이 증가에 따른 건식 식각 공정의 어려움, 증가된 종횡비(Aspect Ratio)에 따른 콘택내의 금속 매립의 어려움 등)을 사전에 제거할 수 있다.According to the present invention, since the tungsten bit line is purely composed of tungsten without being connected to the plug polysilicon, the operation speed of the device is expected to be improved. In addition, the bit line can be directly in contact with the silicon substrate active region 1, so that the bit line can also be used as a metal contact pad in the peripheral region. Problems (eg, difficulty in dry etching due to increasing metal contact depth, difficulty in embedding metal in contacts due to increased aspect ratio, etc.) can be eliminated in advance.
Claims (6)
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| KR100911674B1 (en) * | 2002-12-26 | 2009-08-10 | 매그나칩 반도체 유한회사 | Method for manufacturing an embedded memory devices with a tungsten bit line |
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| JPH01189919A (en) * | 1988-01-26 | 1989-07-31 | Seiko Epson Corp | Semiconductor device and manufacture thereof |
| JPH09153468A (en) * | 1995-11-30 | 1997-06-10 | Sharp Corp | Semiconductor device and manufacture thereof |
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| JPH01189919A (en) * | 1988-01-26 | 1989-07-31 | Seiko Epson Corp | Semiconductor device and manufacture thereof |
| JPH09153468A (en) * | 1995-11-30 | 1997-06-10 | Sharp Corp | Semiconductor device and manufacture thereof |
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