KR100353554B1 - Bit line contact in a semiconductor device and fabricating method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit line contact of a semiconductor device and a method of manufacturing the same. In particular, a sidewall spacer is formed on an side of a bit line contact plug connected to a landing pad to prevent a short circuit between a capacitor and a storage electrode node. The present invention relates to a COB (capacitor over bit line) structure bit line contact of a semiconductor device which improves normal memory cell operation by eliminating errors in data processing. A bit line contact of a semiconductor device according to the present invention penetrates a semiconductor substrate including a transistor including a first conductive region and a second conductive region, a first interlayer insulating layer covering the semiconductor substrate, and a first interlayer insulating layer. And first and second landing pads electrically connected to the first and second conductive regions, the second interlayer insulating layer formed on the first interlayer insulating layer, and the second interlayer insulating layer. A bit line contact plug in electrical contact with a landing pad, a first sidewall spacer made of an insulating material and interposed between the bit line contact plug and the second interlayer insulating layer, and an upper surface of the bit line contact plug. A bit line formed on the second interlayer insulating layer in contact with the third interlayer insulating layer, a third interlayer insulating layer formed on the second interlayer insulating layer to cover the bit line, and the third and second interlayer insulating layers. A through and comprises the second landing pad and the storage node electrode are electrically connected. A method of manufacturing a bit line contact in a semiconductor device according to the present invention includes a first step of forming a first interlayer insulating layer on a semiconductor substrate on which a word line including a first conductive region, a second conductive region, a gate, and the like is formed; A second step of forming a first and a second landing pad made of a conductive material through the first interlayer insulating layer and electrically connected to the first and second conductive regions, respectively; and a second interlayer on the first interlayer insulating layer. A third step of forming an insulating layer, a fourth step of removing a predetermined portion of the second interlayer insulating layer to form a first via hole for opening an upper surface of the first landing pad, and an inside of the first via hole. A fifth step of forming a first sidewall spacer with an insulating material on a side surface, a sixth step of forming a long bit line on the second interlayer insulating layer filling the first via hole, and the bit line; A seventh step of forming a third interlayer dielectric layer on the second interlayer dielectric layer, and removing a predetermined portion of the third and second interlayer dielectric layers to expose an upper surface of the second landing pad. And a ninth step of forming a conductive plug filling the second via hole.

Description

Bit line contact in semiconductor device and fabrication method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit line contact of a semiconductor device and a method of manufacturing the same. In particular, a sidewall spacer is formed on an side of a bit line contact plug connected to a landing pad to prevent a short circuit between a capacitor and a storage electrode node. The present invention relates to a COB (capacitor over bit line) structure bit line contact of a semiconductor device which improves normal memory cell operation by eliminating errors in data processing.

One of the difficulties in the next generation of highly integrated device formation process is to prevent a short circuit between an upper conductive layer such as a bit line and a storage electrode node of a capacitor through a plug.

For example, in order to pattern the bit line, a damaged pattern remains in the bit line contact portion during the etching process, and then the remaining conductive layer is short-circuited with the bit line contact during the etching process of the conductive layer for forming the storage electrode node. Defect occurs.

In general, a memory cell is a landing pad connected to one capacitor and a bit line for signal transmission, a bit line contact plug connected to the bit line, and a bit line contact plug to electrically connect to a source / drain of a transistor. pad), a word line that is spaced apart from the bit line, and serves as a switch of the memory cell.

In this case, when the capacitor is configured above the bit line, a capacitor over bit line (COB) structure is formed, and when the capacitor is located below the bit line, a capacitor under bit line (CUB) structure is formed.

In the prior art, in order to form a bit line, an insulating film is formed on the entire surface of the substrate including the upper portion of the contact plug, and then the insulating film of the contact portion is removed to expose the contact plug surface, and then a conductive layer is formed on the insulating film to cover the plug surface. The patterning is then completed to complete the bit line and the subsequent process forms the storage electrode of the capacitor.

1 is a layout illustrating a bit line contact and a storage electrode node contact of a semiconductor device according to the related art.

Referring to FIG. 1, a transistor (not shown) including an impurity diffusion region or the like is formed on a silicon substrate 20, which is a semiconductor substrate, and a first landing pad (not shown) electrically connected to each impurity diffusion region. And a second landing pad (not shown) are formed.

A bit line contact plug 25 is formed on an upper surface of the first landing pad, and the upper surface of the bit line contact plug 25 is connected to a bit line 26 that runs long in a first direction that is horizontal in the drawing. .

On the other hand, sidewall spacers 30 made of an insulating film such as a nitride film are formed on the side of the bit line 26.

An interlayer insulating film (not shown) is formed over the substrate to cover the structures, and a storage electrode node 28 penetrating the interlayer insulating film and connected to the second landing pad is formed.

At this time, the conductive material 280 for forming the storage electrode node remains on the damaged portion during the patterning of the bit line 26 and the bit line contact plug 25, so that the residue 280 is formed of the storage electrode node 28 and the bit line. This causes a short circuit between the contact plugs 25.

2A to 2C are cross-sectional views illustrating a method of forming a bit line contact in a semiconductor device according to the prior art, in which FIGS. 2A and 2B are along the cutting line I-I ′ of FIG. 1 and FIG. 2C is a cutaway view of FIG. It is sectional drawing along the line II-II '.

Referring to FIG. 2A, after fabricating a transistor (not shown) including a gate (not shown), an impurity diffusion region (not shown), and the like on a silicon substrate 20, which is a semiconductor substrate, a first interlayer covering the entire surface of the substrate The insulating layer 21 is formed by depositing an insulating layer such as an oxide film by a method such as chemical vapor deposition (CVD).

A predetermined portion of the first interlayer insulating layer 21 is removed by photolithography to form contact holes in which the landing pad for the bit line contact and the landing pad for the storage electrode node contact are formed. In this case, only the contact hole where the landing pad for the bit line contact is to be formed by the cutting line is shown.

Then, a conductive material such as polysilicon, tungsten, or the like doped with a first landing pad 220 for bit line contact filling the contact holes and a second landing pad for storage electrode node contact (not shown, shown in FIG. 2C). Form into material.

The etch stop layer 23 made of an insulating material such as a nitride film and the second interlayer insulating layer 24 made of an insulating material such as an oxide film are formed on the upper surfaces of the first and second landing pads and the first interlayer insulating layer 21. ) Is deposited by a method such as CVD.

Next, predetermined portions of the second interlayer insulating layer and the etch stop layer are sequentially removed by photolithography to form a first via hole for opening the upper surface of the first landing pad 220.

Referring to FIG. 2B, a method of sputtering a conductive layer, such as aluminum or an impurity-doped polysilicon, onto a second interlayer insulating layer to a thickness capable of sufficiently filling the first via hole and ensuring a bit line thickness. It is formed by vapor deposition.

Then, the conductive layer is patterned by photolithography to simultaneously form the bit line 26 and the bit line contact plug 25 made of the remaining conductive layer. At this time, the conductive layer patterning is performed by anisotropic etching such as dry etching, and the conductive layer residue (not shown) remains on the second interlayer insulating layer 24.

Next, sidewall spacers (not shown) are formed on the side of the bit line 26 by a nitride film or the like.

A third interlayer insulating layer 27 is formed by depositing an intermetal dielectric on the second interlayer insulating layer 24 to cover the bit line.

Referring to FIG. 2C, predetermined portions of the third interlayer insulating layer 27, the second interlayer insulating layer 24, and the etch stop layer 23 are removed by photolithography using anisotropic etching such as dry etching. A second via hole is formed to expose the top surface of the second landing pad 221.

Then, a conductive layer such as polysilicon or tungsten, which is doped to fill the second via hole, is deposited on the third interlayer insulating layer 27, and the conductive layer remains only in the second via hole by a process such as etch back. The storage electrode node 28 is formed. In this case, the storage electrode node 28 and the bit line contact plug 25 are electrically shorted by the conductive residue 28.

Subsequently, although not shown, a capacitor including a storage electrode / dielectric film / plate electrode or the like is formed to contact the upper surface of the storage electrode node 28 to complete a COB structure memory cell.

However, the above-described bit line contact and manufacturing method of the semiconductor device according to the related art have a problem that an electrical short circuit may occur between the bit line contact plug and the storage electrode node during the formation of the bit electrode contact plug. .

Accordingly, an object of the present invention is to form a sidewall spacer with an insulating material on the side of the bit line contact plug connected to the landing pad, to prevent short circuits with the storage electrode node of the capacitor, thereby eliminating an error in the data processing process, thereby preventing a normal memory cell. The present invention provides a COB (capacitor over bit line) structure bit line contact and a method of manufacturing the same for improving the operation.

A bit line contact of a semiconductor device according to the present invention for achieving the above objects is a semiconductor substrate having a transistor including a first conductive region and a second conductive region, a first interlayer insulating layer covering the semiconductor substrate, First and second landing pads penetrating a first interlayer insulating layer and electrically connected to the first and second conductive regions, respectively, a second interlayer insulating layer formed on the first interlayer insulating layer, and the second interlayer insulating layer. A bit line contact plug penetrating a layer and in electrical contact with the first landing pad, a first sidewall spacer made of an insulating material and interposed between the bit line contact plug and the second interlayer insulating layer, and the bit line A bit line formed on the second interlayer insulating layer in contact with the upper surface of the contact plug, and a third interlayer insulating layer formed on the second interlayer insulating layer to cover the bit line. And comprises the third, the second through the interlayer insulating layer and the second landing pad and the storage node electrode are electrically connected.

A bit line contact manufacturing method of a semiconductor device according to the present invention for achieving the above objects is to form a first interlayer insulating layer on a semiconductor substrate formed with a word line including a first conductive region, a second conductive region, a gate, etc. A first step and a second step of forming a first and a second landing pad made of a conductive material through the first interlayer insulating layer and electrically connected to the first and second conductive regions, respectively; A third step of forming a second interlayer insulating layer on the insulating layer, a fourth step of removing a predetermined portion of the second interlayer insulating layer to form a first via hole for opening an upper surface of the first landing pad; Forming a first sidewall spacer with an insulating material on an inner side surface of the first via hole, and forming a bit line having a long running shape on the second interlayer insulating layer while filling the first via hole; A sixth step of forming a third interlayer insulating layer on the second interlayer insulating layer to cover the bit line; and removing a predetermined portion of the third and second interlayer insulating layers to remove the second landing pad. And an eighth step of forming a second via hole exposing an upper surface of the second electrode, and a ninth step of forming a conductive plug filling the second via hole.

1 is a layout illustrating a bit line contact and a storage electrode node contact of a semiconductor device according to the related art.

2A to 2C are cross-sectional views illustrating a method of forming a bit line contact in a semiconductor device according to the prior art, in which FIGS. 2A and 2B are along the cutting line I-I ′ of FIG. 1 and FIG. 2C is a cutaway view of FIG. Sectional view along line II-II '

3 is a layout illustrating a bit line contact and a storage electrode node contact of a semiconductor device according to the present invention.

4A through 4D are cross-sectional views illustrating a method of forming a bit line contact in a semiconductor device according to the present invention. FIGS. 4A through 4C are taken along the cutting line III-III ′ of FIG. 3, and FIG. 4D is taken along the line of FIG. 3. Cross section along line IV-IV '

The present invention forms a sidewall spacer made of an insulating material such as a nitride film in the via hole where a bit line contact is to be formed, and then forms a bit line contact plug for filling the via hole, thereby securing isolation of the bit line contact plug and subsequently storing the storage electrode node. Even if the forming conductive material remains, an electrical short circuit is essentially prevented between the bit line contact plug and the storage electrode node. Therefore, the present invention can improve the reliability of the device by preventing the error caused by the capacitor operation failure in the process of reading and writing data during the memory cell operation.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a layout illustrating a bit line contact and a storage electrode node contact of a semiconductor device according to the present invention.

Referring to FIG. 3, a transistor (not shown) including an impurity diffusion region or the like is formed on a silicon substrate 40, which is a semiconductor substrate, and a first interlayer insulating layer (not shown) is formed on the substrate to cover the structure. A first landing pad (not shown) and a second landing pad (not shown) electrically connected to respective impurity diffusion regions are formed through the first interlayer insulating layer.

A bit line contact plug 46 is formed on an upper surface of the first landing pad, and a first sidewall spacer 45 made of an insulating material such as a nitride film is formed on the side of the bit line contact plug 46 to form a bit line contact plug ( The short circuit between the 46 and the storage electrode node 49 is prevented.

The upper surface of the bit line contact plug 46 is connected to the bit line 47 which runs long in the first direction, which is horizontal in the drawing. At this time, the bit line 47 is formed on the first interlayer insulating layer.

On the other hand, a second sidewall spacer 50 made of an insulating film such as a nitride film is formed on the side of the bit line 47.

A third interlayer insulating layer (not shown) is formed on the entire surface of the substrate to cover the structures, and a storage electrode node 49 is formed through the third interlayer insulating layer and connected to the second landing pad.

In this case, the bit line contact plug 46 may be formed even if the conductive material 490 for forming the bit line or forming the storage electrode node remains on the damaged portion during patterning of the bit line 47 and the bit line contact plug 47. It is electrically insulated by the sidewall spacers to prevent short circuits between them.

4A through 4D are cross-sectional views illustrating a method of forming a bit line contact in a semiconductor device according to the present invention. FIGS. 4A through 4C are taken along the cutting line III-III ′ of FIG. 3, and FIG. 4D is taken along the line of FIG. 3. It is sectional drawing along the line IV-IV '.

Referring to FIG. 4A, after a transistor (not shown) including a gate (not shown), an impurity diffusion region (not shown), or the like is manufactured on a silicon substrate 40, which is a semiconductor substrate, a first interlayer covering the entire surface of the substrate is illustrated. The insulating layer 41 is formed by depositing an insulating layer such as an oxide film by a method such as chemical vapor deposition (CVD).

A predetermined portion of the first interlayer insulating layer 41 is removed by photolithography to form contact holes in which the first landing pad for the bit line contact and the second landing pad for the storage electrode node contact are formed. In this case, only the contact hole in which the first landing pad for the bit line contact is formed by the cutting line is shown.

Then, polysilicon, tungsten, or the like doped with a first landing pad 420 for bit line contact and a second landing pad (not shown, shown in FIG. 2C, 421) for contacting the storage electrode node. It is formed of a conductive material.

The etch stop layer 43 made of an insulating material such as a nitride film and the second interlayer insulating layer 44 made of an insulating material such as an oxide film are formed on the upper surfaces of the first and second landing pads and the first interlayer insulating layer 41. ) Is deposited by a method such as CVD.

Next, predetermined portions of the second interlayer insulating layer and the etch stop layer are sequentially removed by photolithography to form a first via hole for opening the upper surface of the first landing pad 420.

Referring to FIG. 4B, a first interlayer insulating layer forming material and an insulating material having a high etching selectivity are formed on the second interlayer insulating layer 44 so as to cover the inner surface of the first via hole to a predetermined thickness. In this case, the insulating material is formed by depositing a nitride film by CVD.

Then, the back surface of the second interlayer insulating layer 44 is exposed to the insulating material, and the first sidewall spacer 45 is formed by leaving the insulating material only on the side surface of the first via hole. In this case, the first sidewall spacer 45 ensures electrical insulation between the bit line contact plug and the storage electrode node formed thereafter.

Referring to FIG. 4C, a conductive layer such as aluminum or an impurity-doped polysilicon is formed between the second layer to a thickness capable of sufficiently filling the first via hole 450 formed at the side and securing a bit line thickness. It is formed by depositing on the insulating layer 44 by a method such as sputtering or CVD.

Then, the conductive layer is patterned by photolithography to simultaneously form a bit line 47 and a bit line contact plug 46 made of the remaining conductive layer. At this time, the conductive layer patterning is performed by anisotropic etching such as dry etching, and the conductive layer residue (not shown) may remain on the second interlayer insulating layer 44.

Next, a second sidewall spacer (not shown) is formed on the side of the bit line 47 by a nitride film or the like.

The third interlayer dielectric layer 48 is formed by depositing an intermetal dielectric on the second interlayer dielectric layer 44 so as to cover the bit line.

Referring to FIG. 4D, predetermined portions of the third interlayer insulating layer 48, the second interlayer insulating layer 44, and the etch stop layer 43 are removed by photolithography using anisotropic etching such as dry etching. A second via hole is formed to expose the top surface of the second landing pad 421.

Then, a conductive layer such as polysilicon or tungsten, which is doped to fill the second via hole, is deposited on the third interlayer insulating layer 48, and then the conductive layer remains only in the second via hole by a process such as etch back. The storage electrode node 49 is formed. In this case, it is shown that even if the conductive residue 490 is present between the storage electrode node 49 and the bit line contact plug 46, an electrical short is prevented by the first sidewall spacer 45.

Subsequently, although not shown, a capacitor including a storage electrode / dielectric film / plate electrode or the like is formed to contact the upper surface of the storage electrode node 49 to complete a COB structure memory cell.

Accordingly, the present invention fundamentally prevents an electrical short circuit between the bit line contact plug and the storage electrode node, thereby improving reliability of the device by preventing an error caused by a capacitor malfunction during data reading and writing during memory cell operation. There is an advantage.

Claims (10)

A semiconductor substrate having a transistor including a first conductive region and a second conductive region; A first interlayer insulating layer covering the semiconductor substrate; First and second landing pads penetrating the first interlayer insulating layer and electrically connected to the first and second conductive regions, respectively; A second interlayer insulating layer formed on the first interlayer insulating layer; A bit line contact plug penetrating the second interlayer insulating layer and in electrical contact with the first landing pad; A first sidewall spacer made of an insulating material and interposed between the bit line contact plug and the second interlayer insulating layer; A bit line in contact with an upper surface of the bit line contact plug and formed on the second interlayer insulating layer; A third interlayer dielectric layer formed on the second interlayer dielectric layer so as to cover the bit line; And a storage electrode node penetrating the third and second interlayer insulating layers and electrically connected to the second landing pad. The method according to claim 1, And the first sidewall spacer is formed of a material having a high etching selectivity with the second interlayer insulating layer. The method according to claim 1, And a second sidewall spacer formed of an insulator and formed on a side of the bitline. The method according to claim 1, The bit line contact of the semiconductor device, further comprising a storage electrode, a dielectric layer, and a plate electrode electrically connected to the storage node contact. The method according to claim 1, And the semiconductor device is a memory cell including the transistor and a capacitor. A first step of forming a first interlayer dielectric layer on a semiconductor substrate having a word line including a first conductive region, a second conductive region, a gate, and the like; Forming a first and a second landing pad made of a conductive material through the first interlayer insulating layer and electrically connected to the first and second conductive regions, respectively; Forming a second interlayer dielectric layer on the first interlayer dielectric layer; Removing a predetermined portion of the second interlayer insulating layer to form a first via hole for opening an upper surface of the first landing pad; A fifth step of forming a first sidewall spacer with an insulating material on an inner side surface of the first via hole; A sixth step of filling the first via hole and forming a long bit line on the second interlayer insulating layer; Forming a third interlayer dielectric layer on the second interlayer dielectric layer so as to cover the bit line; An eighth step of removing a predetermined portion of the third and second interlayer insulating layers to form a second via hole exposing an upper surface of the second landing pad; And a ninth step of forming a conductive plug filling the second via hole. The method according to claim 6, The fifth step, Forming an insulating layer having a high etch selectivity with the second interlayer insulating layer on the second interlayer insulating layer including the first via hole; And performing an etch back using the surface of the second interlayer insulating layer as an etch stop layer to form the first sidewall spacer made of the remaining insulating film. Contact manufacturing method. The method according to claim 7, And wherein said second interlayer insulating layer is formed of an oxide film and said insulating film is formed of a nitride film. The method according to claim 6, After the ninth step, And forming a capacitor electrically connected to the conductive plug. The method according to claim 6, And forming a second sidewall spacer with an insulating material on a side surface of the bit line.