KR20060135194A - Method for manufacturing a semiconductor device - Google Patents

Abstract

A method for fabricating a semiconductor device is provided to avoid influence on a bitline even if chemicals penetrate an interlayer dielectric in a cleaning process performed after an interlayer dielectric for forming a contact plug is etched, by interposing a material having different etch selectivity from that of the interlayer dielectric between a conductive layer and an interlayer dielectric formed under the conductive layer. A substrate(110) having an underlying layer is prepared. A first interlayer dielectric(112) is deposited on the substrate. A barrier layer(115) having different etch selectivity from that of the first interlayer dielectric is deposited on the first interlayer dielectric. A conductive layer is formed on the barrier layer. The barrier layer exposed to both sides of the conductive layer is etched. A second interlayer dielectric(114) is deposited on the resultant structure. The second interlayer dielectric and the first interlayer dielectric are etched to expose a part of the underlying layer, made of a material having the same etch selectivity.

Description

Semiconductor device manufacturing method {METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE}

1 is a plan view showing a conventional DRAM cell array.

FIG. 2 is a cross-sectional view taken along the line X-X 'of FIG. 1;

3 to 5 are process cross-sectional views showing a semiconductor device manufacturing process according to a preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

110: semiconductor substrate

111: device isolation film

112, 114, 119: interlayer insulating film

113: landing plug

115: barrier film

116: bit line

117, 121: hard mask

118: spacer

120: etch stop film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a DRAM (DRAM).

Currently, semiconductor memory devices can be broadly classified into read / write memory (RAM) and read only memory (ROM). In particular, RAM is divided into dynamic RAM (DRAM) and static RAM (SRAM). DRAM is a device that is one of the most advanced in the integration of one transistor (transistor) and one capacitor unit cell (unit cell).

FIG. 1 is a plan view illustrating a conventional DRAM cell array, and FIG. 2 is a cross-sectional view taken along the line X-X 'of FIG. 1, that is, the word line WL (see FIG. 1).

Hereinafter, a general DRAM device manufacturing method will be described with reference to FIG. 2.

First, a first interlayer dielectric film (ILD: Interlayer Dilectric) 12 having a contact plug 13 (hereinafter referred to as a landing plug) is formed on the semiconductor substrate 10 on which the device isolation layer 11 is formed. A second interlayer insulating film 14 is deposited on the first interlayer insulating film 12 including the plug 13. In this case, the landing plug 13 is formed between a plurality of word lines (not shown) formed on the substrate 10. Thereafter, a bit line 15 having a hard mask 16 and a spacer 17 is formed on the top and both side walls of the second interlayer insulating film 14, respectively.

Subsequently, after the third interlayer insulating layer 18 is deposited on the entire structure on which the bit line 15 is formed, the etch stop layer 19 and the hard mask 20 are deposited on the third interlayer insulating layer 18. Then, after the hard mask 20 is patterned, the etch stop layer 19, the third interlayer dielectric layer 18, and the second interlayer dielectric layer between the bit lines 15 are patterned using the patterned hard mask 20. (14) is sequentially etched. As a result, a hole (not shown) for exposing the landing plug 13 is formed.

Subsequently, the cleaning process is performed using a chemical such as HF to remove the native oxide formed on the landing plug 13 exposed by the etching process for forming the storage node contact plug 21. ).

Subsequently, the plug material is deposited to planarize the hole, and then planarized to form the storage node contact plug 21 connecting the lower electrode (or the storage node) of the capacitor with the landing plug 13.

However, according to the related art, since the chemical penetrates into the second interlayer insulating film 14 and is attacked to the bit line 15 during the cleaning process, the bit line 15 may be damaged. Will wear. The damage of the bit line 15 causes a short between the storage node contact plug 21 and the bit line 15 when the storage node contact plug 21 is formed. Therefore, since the defect rate of the semiconductor device is increased, a large problem occurs that the reliability of the product is lowered.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of suppressing a short circuit between a bit line and a storage node contact plug of a DRAM device.

According to an aspect of the present invention, there is provided a substrate on which an underlayer is formed, depositing a first interlayer insulating film on the substrate, and forming the first interlayer insulating film on the first interlayer insulating film. Depositing a barrier film having a different etching selectivity from the interlayer insulating film, forming a conductive layer on the barrier film, etching the barrier film exposed to both sides of the conductive layer, and including the conductive layer And depositing a second interlayer dielectric layer over the structure, and etching the second interlayer dielectric layer and the first interlayer dielectric layer to expose a portion of the underlayer.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. Also, throughout the specification, the same reference numerals denote the same components.

Example

3 to 5 are process cross-sectional views illustrating a semiconductor device manufacturing process according to an exemplary embodiment of the present invention. For convenience of description, a cross-sectional view of a process of cutting a word line in a stretched direction in a DRAM cell array formed according to a preferred embodiment of the present invention will be described.

First, as shown in FIG. 3, a plurality of gate electrodes (not shown) functioning as word lines are formed on the semiconductor substrate 110 on which the device isolation layer 111 is formed. In this case, the device isolation layer 111 may be formed by performing a conventional shallow trench isolation (STI) process, and may be formed of an HDP (High Density Plasma) oxide film having excellent gap-fill characteristics.

Subsequently, a first interlayer insulating film 112 is deposited on the substrate 110 to cover the gate electrode. In this case, the interlayer insulating film 112 is formed of an oxide film-based material. For example, HDP (High Density Plasma) oxide film, BPSG (Boron Phosphorus Silicate Glass) film, PSG (Phosphorus Silicate Glass) film, PETEOS (Plasma Enhanced Tetra Ethyle Ortho Silicate) film, PECVD (Plasma Enhanced Chemical Vapor Deposition) film, USG It is formed as a single layer film or a laminated film in which these layers are formed using any one of an un-doped silicate glass (FSG) film, a fluorinated silicate glass (FSG) film, a carbon doped oxide (CDO) film, and an organic silicate glass (OSG) film.

Subsequently, the first interlayer insulating layer 112 is etched to form a hole (not shown) that exposes the substrate 110 between the gate electrodes. Then, the plug material is deposited to fill the hole, and then a planarization process such as a chemical mechanical polishing (CMP) process is performed to planarize it. As a result, a landing plug 113 embedded in the hole is formed.

Subsequently, a second interlayer insulating layer 114 is deposited on the first interlayer insulating layer 112 including the landing plug 113. In this case, the second interlayer insulating film 114 is deposited with an oxide-based material having the same etch selectivity as the first interlayer insulating film 112 to a thickness of 1700 Å.

Subsequently, a barrier layer 115 is deposited on the second interlayer insulating layer 114. In this case, the barrier layer 115 deposits a nitride layer-based material having a different etching selectivity from the first and second interlayer insulating layers 112 and 114 to a thickness of 150 to 200 Å.

Subsequently, as illustrated in FIG. 4, a conductive layer (not shown) such as tungsten (W) is deposited on the barrier film 115, and then a hard mask 117 is deposited on the conductive layer. In this case, the hard mask 117 is formed of a nitride film-based material.

Subsequently, after applying a photoresist (not shown) on the hard mask 117, a photoresist pattern (not shown) is formed by performing an exposure and development process using a photomask (not shown). Then, an etching process using the same as an etching mask is performed to etch the hard mask 117 and the conductive layer. As a result, the bit line 116 having the hard mask 117 is formed thereon. Here, the etching process may be performed by a dry or wet etching process.

Subsequently, a strip process is performed to remove the photoresist pattern. In this case, when etching the bit line 116, a hard mask scheme using an etched hard mask 117 as an etch mask may be used.

Subsequently, a nitride film (not shown) having the same etching selectivity as the barrier layer 115 is deposited along the step of the entire structure including the bit line 116. At this time, the nitride film is deposited to a thickness within 300 kPa, preferably 200 kPa.

Subsequently, a dry etching process is performed to etch the nitride film, thereby forming spacers 118 on both sidewalls of the bit line 116 and the hard mask 117. In this case, since the barrier film 115 has the same etching selectivity as the spacer 118, the barrier layer 115 is etched together during the etching process for forming the spacer 118. As a result, the barrier layer 115 exposed to both sides of the spacer 118 is removed, and the second interlayer insulating layer 114 between the bit lines 116 is exposed.

Subsequently, a third interlayer insulating layer 119 is deposited on the entire structure including the bit line 116 and the spacer 118. In this case, the third interlayer insulating layer 119 is formed to cover the hard mask 117 on the bit line 116 and is formed of an oxide-based material. Preferably, it is formed of an HDP oxide film.

Subsequently, as shown in FIG. 5, the etch stop layer 120 and the hard mask 121 are sequentially deposited on the third interlayer insulating layer 119.

Subsequently, a photoresist (not shown) is coated on the hard mask 121, and then a photoresist pattern (not shown) is formed by performing an exposure and development process using a photomask (not shown).

Subsequently, the hard mask 121 is etched by performing an etching process using the photoresist pattern as an etching mask. At this time, the etching is once stopped on the etch stop layer 120. Then, a strip process is performed to remove the photoresist pattern.

Subsequently, an etching process using the etched hard mask 121 as an etch mask is performed to sequentially etch the etch stop layer 120, the third interlayer insulating layer 119, and the second interlayer insulating layer 114. As a result, an opening is formed to open an area where the storage node contact plug is to be formed. Here, the storage node contact plug serves to electrically connect the substrate 110 and the storage node that is the lower electrode of the capacitor through the landing plug 113.

Subsequently, although not shown in the drawing, a cleaning process is performed using a chemical such as HF to remove the native oxide film formed on the landing plug 113 exposed by the etching process for forming the storage node contact plug.

Subsequently, a plug material, for example, polysilicon is deposited on the hard mask 121 including the opening, followed by an etch-back or CMP process to form a storage node contact plug in which the inside of the opening is buried.

Subsequently, the capacitor is formed in accordance with a conventional DRAM capacitor formation process.

That is, according to a preferred embodiment of the present invention, an interlayer insulating film for forming a storage node contact plug is formed between a bit line and an interlayer insulating film formed on the bottom of the bit line by interposing a barrier film made of a material having a different etch selectivity, for example, a nitride film. In the cleaning process performed after the etching process, the penetration of the chemical into the interlayer insulating film does not affect the bit line.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the interlayer insulating film is etched between the conductive layer and the interlayer insulating film formed on the bottom of the conductive layer by interposing a barrier film made of a material having a different etch selectivity, for example, a nitride film. In the cleaning step performed after the step, even if the chemical penetrates into the interlayer insulating film, the bit line can be prevented. Therefore, it is possible to significantly reduce the defective rate of the semiconductor device to improve the reliability of the product.

Claims (9)

Providing a substrate on which an underlayer is formed; Depositing a first interlayer dielectric film on the substrate; Depositing a barrier layer on the first interlayer insulating layer, the barrier layer having a different etching selectivity from the first interlayer insulating layer; Forming a conductive layer on the barrier film; Etching the barrier layer exposed to both sides of the conductive layer; Depositing a second interlayer insulating film over the entire structure including the conductive layer; And Etching the second interlayer insulating layer and the first interlayer insulating layer to expose a portion of the underlayer. Semiconductor device manufacturing method comprising a. The method of claim 1, The barrier film is a semiconductor device manufacturing method of forming a nitride film-based material. The method of claim 1, The second interlayer dielectric layer is formed of a material having the same etching selectivity as the first interlayer dielectric layer. The method according to claim 1 or 3, The first and second interlayer insulating film is formed of an oxide film-based material. The method according to claim 1 or 2, And forming spacers on both sidewalls of the conductive layer after the conductive layer is formed. The method of claim 5, And the spacer is formed of the same material as the barrier layer. The method according to claim 1 or 2, And the conductive layer functions as a bit line. The method of claim 1 or 2, wherein after etching the first and second interlayer insulating films, Depositing a plug material to cover the second interlayer dielectric layer on the exposed underlying layer; And Planarizing the plug material to form a contact plug Semiconductor device manufacturing method further comprising. The method according to claim 1 or 2, The underlayer of the exposed portion is a semiconductor device manufacturing method consisting of a contact plug.

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