KR20020024376A - Method of forming contacts in semiconductor devices - Google Patents

Abstract

PURPOSE: A method for fabricating a contact of a semiconductor device is provided to improve a write/read margin of a memory cell and a refresh characteristic, by additionally doping high density ions to a landing pad to reduce contact resistance of the landing pad and a plug in contact with the landing pad. CONSTITUTION: A plurality of gate lines are formed on a semiconductor substrate(30) by interposing a gate insulation layer(32). An impurity diffusion region is formed in the substrate at both side surfaces of the gate line positioned in an active region. A sidewall spacer is formed on the side surface of the gate line of the active region. The first landing pad(371) for a storage electrode node contact and the second landing pad(370) for a bit line contact are made of doped polysilicon. The first and second landing pads are doped. The first interlayer dielectric(380) is formed on the substrate including the first and second landing pads. The second interlayer dielectric is formed on the substrate. The second via hole exposing the upper surface of the second landing pad is formed. The second via hole is filled with a conductive material, and a bit line is formed on the second interlayer dielectric. The third interlayer dielectric is formed on the second interlayer dielectric to cover the bit line. The first via hole exposing the upper surface of the first landing pad is formed. The first via hole is filled with a conductive material to form a plug.

Description

Method of forming contacts in semiconductor devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact in a semiconductor device. In particular, when a polysilicon plug is formed in a stacked structure using a landing pad to form a polysilicon plug electrically connecting a storage electrode node to an impurity diffusion region of a transistor, The present invention relates to a method of forming a storage electrode node contact of a semiconductor device, by further doping the landing pad with ion implantation to reduce contact resistance with a plug in contact with the landing pad, thereby improving read / write margins and refresh characteristics of the memory cell.

One of the difficulties in the next generation of highly integrated device formation process is the problem of patterning holes of 0.2 μm or less. It is difficult to meet the resolution and design overlay margin required by the photo processing equipments currently used.

The method used to overcome this problem is a method of forming a self-aligned contact. By using the etching process with a large etching selectivity of the oxide film / nitride film in the cell contact forming process in which the silicon nitride barrier film is formed, the overlay margin can be increased, and the etch profile is inclined to form a maximum critical dimension of 0.2 μm or less. have.

However, when forming a memory cell having a capacitor on bit line (COB) structure, a self-aligned contact (SAC) formation process is performed using doped polysilicon, and the SAC structure forms a substructure of the contact. It consists of a landing pad and a plug forming a superstructure. At this time, both the landing pad and the at least one plug are made of doped polysilicon and the resistance at the contact portion between them increases.

That is, as compared with the case where the storage node contact is directly formed as a conductor in the impurity diffusion region of the substrate, the landing pads and plugs formed at different process steps are structurally clean or connected at the process step. The contact resistance is increased due to a defect or the like.

In addition, the alignment margin between the landing pad and the plug is poor, further increasing the contact resistance.

As such, the increase in contact resistance of the storage electrode reduces the read / write margin of the memory cell and degrades the refresh characteristics. That is, as the density of memory increases and the number of memory cells increases, the amount of current consumption increases, which makes the refresh period longer.

1A to 1D are cross-sectional views illustrating a method of forming a storage electrode node contact and a bit line contact of a semiconductor device according to the related art.

Referring to FIG. 1A, a trench insulating field oxide layer 11 defining an active region and a field region is formed on a silicon substrate 10, which is a semiconductor substrate, to form a gate oxide layer 12 as a thermal oxide layer, and then doping for gate formation. Formed by depositing the formed polysilicon layer and then depositing the nitride film 14 with a capping insulating film thereon, and then performing a photolithography process to form an etch mask (not shown) on the nitride film 14. By removing the portions not protected by the etch mask of the nitride film, the polysilicon layer, and the gate insulating film, the gate line 13 as a word line is patterned.

Next, a low concentration impurity diffusion region 15, which is a source / drain, is formed in the active region of the substrate by ion implantation using the word line 13, and then sidewall spacers are formed on the entire surface of the substrate 10 including the word line 13. The nitride film is deposited by chemical vapor deposition using an insulating film for the purpose of chemical vapor deposition.

Next, the nitride film is etched back to form a word line sidewall spacer 16 made of the remaining nitride film.

In addition, a high concentration impurity diffusion region 15 is formed in the active region of the substrate around the gate 13 by a high concentration of ion implantation, thereby completing a source / drain 15 having a lightly doped drain structure. In the figure, a high concentration impurity diffusion region and a low concentration impurity diffusion region are simultaneously displayed, and the LED structure is optional.

Thus, a transistor having an LDD structure is formed and a word line connecting the transistor is formed.

Referring to FIG. 1B, an interlayer insulating layer 17 is formed by depositing an oxide film by chemical vapor deposition on an entire surface of a structure formed on a substrate including a transistor.

Next, a contact hole for exposing the substrate active region 15 of the contact portion where the contact plug to be connected to the bit line and the node plug of the capacitor storage electrode is to be formed is formed by photolithography removing a predetermined portion of the interlayer insulating layer 17. do.

In order to form the node plug of the contact plug and the capacitor storage electrode to be connected to the bit line, the polysilicon layer 18 doped on the entire surface of the interlayer insulating layer 17 to a thickness sufficient to fill the contact hole is CVD method. It is formed by vapor deposition.

Referring to FIG. 1C, the doped polysilicon layer 18 is etched back to expose the upper surface of the interlayer insulating layer 17 so that the polysilicon remains only in the contact hole. At this time, the remaining polysilicon becomes the contact plug 181 to be connected to the bit line and the node plug 180 or the landing pad 180 of the capacitor storage electrode.

Referring to FIG. 1D, after forming the insulating film 19, the surface of the plug 181 of the bit line contact portion is opened to form the bit line 20, and then the insulating film 21 is formed on the entire surface, and then the storage is performed. The upper surface of the electrode node plug 180 is opened by removing predetermined portions of the insulating layers 19 and 21, and then the storage electrode 22 is formed.

However, in the above-described conventional method for forming a contact of a semiconductor device, increasing the contact resistance of the storage electrode reduces the read / write margin of the memory cell and also degrades the refresh characteristics. That is, the amount of current consumption increases as the memory density increases and the number of memory cells increases, which causes a long refresh period.

Accordingly, an object of the present invention is to form a polysilicon plug electrically connecting a storage electrode node and an impurity diffusion region of a transistor in a stacked structure using a landing pad to form a landing pad at a high concentration by ion implantation after the landing pad is formed. The present invention provides a method of forming a storage electrode node contact of a semiconductor device, which further improves read / write margins and refresh characteristics of a memory cell by reducing contact resistance with a plug in contact with a landing pad.

According to an aspect of the present invention, there is provided a method of forming a contact for a semiconductor device, the method comprising: forming a plurality of gate lines having a cap insulating layer interposed through a gate insulating layer on a semiconductor substrate having a field region and an active region defined therein; Forming an impurity diffusion region in the substrate on both lower sides of the gate line positioned at the gate line; forming a sidewall spacer on the side of the active region gate line to expose a part of the impurity diffusion region as an insulator; Forming a first landing pad for contacting the storage electrode node and a second landing pad for the bit line contact and a doped polysilicon in contact with the region and filling the gap between the gate lines of the active region and spaced apart from each other; Doping the first and second landing pads to form a substrate, the substrate comprising the first and second landing pads. Depositing a first interlayer dielectric layer on the substrate, chemically polishing the interlayer dielectric layer to expose the cap dielectric layer, forming a second interlayer dielectric layer on the front surface of the substrate, and forming a second interlayer dielectric layer. Removing a predetermined portion to form a second via hole exposing the top surface of the second landing pad, filling the second via hole with a conductive material and forming a bit line on the second interlayer insulating layer; Forming a third interlayer insulating layer on the second interlayer insulating layer so as to cover and forming a first via hole exposing a top surface of the first landing pad by removing predetermined portions of the third and second interlayer insulating layers; And forming a plug for filling the first via hole with a conductor.

1A to 1D are cross-sectional views illustrating a method for forming a contact in a semiconductor device according to the related art.

2A through 2D are cross-sectional views illustrating a method for forming a contact in a semiconductor device according to the present invention.

The present invention manufactures a transistor comprising a gate and a gate sidewall spacer, a capping insulating film, an impurity diffusion region, and the like, and then forms a landing pad made of polysilicon doped between the gates so as to contact the impurity diffusion region. Only the landing pads of the storage electrode node contact and the bit line contact portion remain, and all remaining landing pads are removed.

Then, an insulating film such as an oxide film is formed on the entire surface of the substrate including the landing pad upper surface, and then a CMP (cheemical mechanical polishing) process is performed on the insulating film to expose the capping insulating film on the gate. Therefore, the upper surface of the substrate is composed of an insulating film to be coated, a landing pad, and an insulating film surface.

Then, ion implantation is performed to increase the doping concentration of the landing pad made of polysilicon doped on the front surface of the substrate.

Then, the interlayer insulating layer, the bit line contact plug, the bit line, and the like which contact the landing pad for the bit line contact are formed through a predetermined process, and then the interlayer insulating layer is formed again, and the landing pad for the storage electrode node contact is formed. After forming a contact plug for a storage electrode node, a capacitor including a storage electrode / dielectric film / plate electrode is manufactured to complete a memory cell.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2D are cross-sectional views illustrating a method for forming a contact in a semiconductor device according to the present invention.

Referring to FIG. 2A, a trench insulating field oxide layer 31 defining an active region and a field region is formed on the silicon substrate 30, which is a semiconductor substrate. Formed by depositing the formed polysilicon layer and then depositing a nitride film 34 with a capping insulating film thereon, and then performing a photolithography process to form an etch mask (not shown) on the nitride film 34. Thus, the nitride film 34, the gate 33, and the gate insulating film 32 are formed by removing the nitride film, the polysilicon layer, and a portion not protected by the etching mask of the gate insulating film.

Next, a low concentration impurity diffusion region 35 as a source / drain is formed in the active region of the substrate by ion implantation using the capping nitride film 34 and the gate 33, and then the entire surface of the substrate 30 including the gate pattern. A nitride film is deposited by chemical vapor deposition with an insulating film for forming sidewall spacers.

Next, the nitride film is etched back to form a word line sidewall spacer 36 made of the remaining nitride film.

In addition, the source / drain 35 having the lightly doped drain structure is formed by partially overlapping the low concentration impurity diffusion region 35 in the active region of the substrate around the gate 13 by the high concentration ion implantation. To complete. In the figure, a high concentration impurity diffusion region and a low concentration impurity diffusion region are simultaneously displayed, and the LED structure is optional.

Thus, a transistor having an LDD structure is formed and a word line connecting the transistor is formed.

In order to form a landing pad to be connected to the bit line contact plug and the capacitor storage electrode node plug, a polysilicon layer doped on the front surface of the substrate to a sufficient thickness to fill a gap between the word lines made of a gate or the like. Is deposited by CVD.

Then, the polysilicon layer is etched back or CMP so that the upper surface of the capping nitride film 34 is exposed, so that the polysilicon layer remains only in the gap between the word lines.

Then, the remaining polysilicon layer is patterned again by photolithography so as to remain in only one cell region and at the same time to be isolated from the remaining polysilicon of neighboring transistors. At this time, all the remaining polysilicon of the peripheral circuit portion is removed.

Accordingly, the first landing pad 371 for the storage electrode node contact and the second landing pad 370 for the bit line contact are formed of the remaining polysilicon separated from each other.

Referring to FIG. 2B, an oxide film is deposited by chemical vapor deposition on an entire surface of a structure formed on a substrate including a transistor to form a first interlayer insulating layer 38.

Referring to FIG. 2C, the first interlayer insulating layer 380 is subjected to CMP to expose the surface of the capping nitride film 34 and the surfaces of the first landing pad 371 and the second landing pad 370. ) Is left in the gap between the word line of the portion where the landing pads 371 and 370 are not formed and the remaining peripheral circuit portion.

Therefore, at least the impurity diffusion regions of all the transistors of the cell region and the peripheral circuit portion are covered with the remaining first interlayer insulating layer 380, and the capping nitride film 34 and the first and second landing pads 371 and 370 are formed. The top surface is exposed.

In addition, impurity ion implantation is performed on the entire surface of the exposed substrate to increase the doping concentrations of the exposed first landing pad 371 and the second landing pad 370, thereby reducing self-resistance.

Referring to FIG. 2D, after the nitride film and the second interlayer insulating layer 40 oxide are deposited on the entire surface of the substrate by the etch stop layer 39, a predetermined portion of the second interlayer insulating layer and the etch stop layer is formed by photolithography. A second via hole exposing the upper surface of the second landing pad 370 to be removed, and then depositing a conductive layer on the entire surface of the second interlayer insulating layer 40 with polysilicon or the like, and then patterning the bit line. To form 41. Although only a part of the bit line is shown in the drawing, the bit line 41 is formed to run long in the vertical direction with the word line.

Then, an oxide film is deposited on the second interlayer insulating layer 40 including the bit lines by the third interlayer insulating layer 42, and then the third and second interlayer insulating layers 42 and 40 are formed by photolithography. ) And a predetermined portion of the etch stop layer 39 are removed to form a first via hole.

Thereafter, a conductive layer is deposited on the third interlayer insulating layer so as to sufficiently fill the first via hole, and then the contact plug 43 for the storage electrode node is formed by remaining only in the first via hole by a method such as etch back.

Therefore, since the first landing pad 371 is made of polysilicon further doped with high concentration, not only the contact resistance but also the overall storage electrode node contact resistance at the interface with the plug 43 in contact therewith is reduced.

The storage electrode 44 is formed on the third interlayer insulating layer 42 to contact the plug 43 with a conductive material.

Subsequently, although not shown, a dielectric film and a plate electrode are sequentially formed on the exposed surface of the storage electrode 44 to complete a memory device including a capacitor.

Therefore, when the polysilicon plug is electrically connected between the storage electrode node and the impurity diffusion region of the transistor to form a stacked structure using the landing pad, the doping pad is additionally doped by ion implantation after the landing pad is formed. By reducing the contact resistance of the plug in contact with the landing pad, the read / write margin and refresh characteristics of the memory cell are improved.

Claims (5)

A first step of forming a plurality of gate lines having a cap insulating film interposed through the gate insulating film on a semiconductor substrate having a field region and an active region defined therein; A second step of forming an impurity diffusion region in the substrate at lower ends of both sides with respect to the gate line positioned in the active region; Forming a sidewall spacer, the sidewall spacer exposing a portion of the impurity diffusion region, on the side surface of the active region gate line as an insulator; The first landing pad for the storage electrode node contact and the second landing pad for the bit line contact are formed of doped polysilicon in contact with the exposed impurity diffusion region and filling the gap between the gate line of the active region and spaced apart from each other. With the fourth step, Doping the first and second landing pads to increase conductivity; Forming a first interlayer dielectric layer on the substrate including the first and second landing pads; A seventh step of chemically mechanically polishing the interlayer insulating layer to expose the cap insulating film; An eighth step of forming a second interlayer insulating layer on an entire surface of the substrate; A ninth step of forming a second via hole exposing a top surface of the second landing pad by removing a predetermined portion of the second interlayer insulating layer; A tenth step of filling the second via hole with a conductive material and forming a bit line on the second interlayer insulating layer; An eleventh step of forming a third interlayer dielectric layer on the second interlayer dielectric layer so as to cover the bit line; Removing a predetermined portion of the third and second interlayer dielectric layers to form a first via hole exposing an upper surface of the first landing pad; And forming a plug for filling the first via hole with a conductor. The method according to claim 1, And the insulating material, the cap insulating film, and the sidewall spacer are formed of an insulating material having a high etching selectivity with the first and second interlayer insulating layers. The method according to claim 1, And said fifth step is performed by implanting impurity ions. The method according to claim 1, After the thirteenth step, And forming a capacitor including a storage electrode in contact with the plug on the third interlayer insulating layer to manufacture a DRAM cell. The method according to claim 1, And the plug is formed of doped polysilicon.