KR20080032517A - Semiconductor memory cell having a recessed landing pad and method of fabricating the same - Google Patents

Abstract

A semiconductor memory cell having a recessed landing pad, and a method of fabricating the same are provided to prevent a metal silicide film and the second landing pad from being exposed during the process of forming node contact holes, by making upper surfaces of the metal silicide film and second landing pad have levels that are lower than that of the first landing pad, thereby preventing short-circuit between node contact plugs and second landing pad. A semiconductor memory cell having a recessed landing pad comprises a lower interlayer insulation film(120), the first landing pad(116), the second landing pad(118), an intermediate interlayer insulation film(122), a conductive line(133), and a metal silicide film(118s). The lower interlayer insulation film covers a semiconductor substrate(100). The first landing pad comes in contact with the semiconductor substrate by passing through the lower interlayer insulation film. The second landing pad has an upper surface whose level is lower than that of the first lading pad within the lower interlayer insulation film and comes in contact with the semiconductor substrate as being spaced away from the first landing pad. The intermediate interlayer insulation film covers the first landing pad and the lower interlayer insulation film. The conductive line is disposed on the intermediate interlayer insulation film and is electrically connected to the second landing pad as penetrating the lower interlayer insulation film and the intermediate interlayer insulation film. The metal silicide film is disposed between the second landing pad and the conductive line and has an upper surface whose level is lower than that of the first landing pad. The metal silicide film is covered by the lower interlayer insulation film.

Description

Semiconductor memory cell having a recessed landing pad and a method of manufacturing the same {Semiconductor memory cell having a recessed landing pad and method of fabricating the same}

1 and 2 are cross-sectional views illustrating a method of manufacturing a conventional semiconductor memory cell.

3 is a plan view of semiconductor memory cells in accordance with an embodiment of the present invention.

4 is a cross-sectional view taken along line II ′ of FIG. 3.

5 to 9 are cross-sectional views taken along the line II ′ of FIG. 3 to explain a method of manufacturing a semiconductor memory cell according to an embodiment of the present invention.

TECHNICAL FIELD The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor memory cell having a recessed landing pad and a method of manufacturing the same.

BACKGROUND Semiconductor devices, such as dynamic random access memory (DRAM), have MOS transistors, capacitors, and wirings. The MOS transistor has a source region and a drain region. The capacitor may be electrically connected to the source region. In addition, the wiring line, for example, the bit line may be electrically connected to the drain region. The capacitor and the bit line are connected to the source region and the drain region through respective contact plugs. Each of the contact plugs may not be directly connected, but may be in contact with landing pads positioned on the source region and the drain region. However, as the semiconductor devices are highly integrated, the distance between the landing pads is decreasing. Therefore, it is increasingly difficult to align the contact plugs precisely with the corresponding landing pads, respectively.

1 to 2 are cross-sectional views illustrating a method of manufacturing a conventional semiconductor memory cell.

Referring to FIG. 1, an isolation layer 13 defining an active region 12 is formed in a semiconductor substrate 11. A lower interlayer insulating film 15 is formed on the entire surface of the semiconductor substrate 11 having the device isolation film 13. First and second landing pads 16 and 17 penetrate the lower interlayer insulating layer 15 to contact the active region 12. The landing pads 16 and 17 may be formed of a polysilicon film. Here, the upper surfaces of the landing pads 16 and 17 and the lower interlayer insulating layer 15 are located on substantially the same plane.

An intermediate interlayer insulating layer 25 is formed on the entire surface of the semiconductor substrate 11 having the landing pads 16 and 17. A bit line contact hole 19 is formed through the intermediate interlayer insulating layer 25 to expose the second landing pad 17. Plug spacers 21 are formed on sidewalls of the bit line contact holes 19.

Subsequently, a metal film is formed to fill the bit line contact hole 19 and cover the intermediate interlayer insulating film 25. The metal film may be formed of a tungsten film. The metal film is patterned to form bit lines 29. As a result, a bit line plug 23 is formed in the bit line contact hole 19. The bit line 29 is electrically connected to the second landing pad 17 through the bit line plug 23. Bit line spacers 27 are formed on sidewalls of the bit lines 29. In this case, the bit line 29 may not cover the entire upper portion of the second landing pad 17 in the process of patterning the metal layer. That is, the bit line 29 may not exactly overlap the upper portion of the second landing pad 17.

An upper interlayer insulating layer 35 is formed on the entire surface of the semiconductor substrate 11 having the bit line 29.

Referring to FIG. 2, the upper interlayer insulating layer 35 and the intermediate interlayer insulating layer 25 are successively patterned to form storage node contact holes 37 exposing the first landing pad 16. Subsequently, the storage node contact holes 37 may be extended using an isotropic etching process.

During the expansion of the storage node contact holes 37, the intermediate interlayer insulating layer 25 may be partially etched to cover the top surface of the edge S of the second landing pad 17. As a result, a portion of the upper surface of the second landing pad 17 is exposed. In addition, the lower interlayer insulating layer 15 may be partially etched and recessed downward. Accordingly, sidewalls of the edge S of the second landing pad 17 may be exposed.

Thereafter, conductive patterns such as node contact plugs 41 filling the extended storage node contact holes 37 are formed. The node contact plugs 41 are in contact with the exposed edge S. FIG. In FIG. 2, node contact plugs 41 are formed inside the node contact holes 37. Alternatively, conductive patterns such as storage node electrodes (not shown) may be formed. In this case, the storage node electrodes may contact the exposed edge S.

As described above, when the bit line 29 and the second landing pad 17 do not exactly overlap with each other, according to the manufacturing method of the conventional semiconductor memory cell, the node contact holes 37 may form the second landing. The edge S of the pad 29 may be exposed. As a result, a short circuit between the conductive patterns and the exposed edge S may cause a malfunction of the semiconductor memory cell.

It is an object of the present invention to provide a semiconductor memory cell having a recessed landing pad and preventing a short circuit between the landing pad and a conductive pattern adjacent thereto, and a method of manufacturing the same.

According to an aspect of the present invention for achieving the above technical problem, a semiconductor memory cell is provided. The semiconductor memory cell has a lower interlayer insulating layer covering the semiconductor substrate. The semiconductor substrate is in contact with the first landing pad through the lower interlayer insulating layer. An upper surface having a lower level than an upper surface of the first landing pad is disposed in the lower interlayer insulating layer, and spaced apart from the first landing pad to contact the semiconductor substrate and the second landing pad. An intermediate interlayer insulating layer covers the first landing pad and the lower interlayer insulating layer. An electrically conductive line is disposed on the intermediate interlayer insulating layer and is electrically connected to the second landing pad through the intermediate interlayer insulating layer and the lower interlayer insulating layer.

In some embodiments of the present disclosure, the semiconductor device may further include a metal silicide layer interposed between the second landing pad and the conductive line and having a top surface of a lower level than the top surface of the first landing pad. The lower interlayer insulating layer may cover the metal silicide layer.

In example embodiments, the lower interlayer insulating layer may include a lower insulating layer covering the lower sidewalls of the semiconductor substrate and the first and second landing pads. An upper insulating layer may be provided on the lower insulating layer to cover an upper sidewall of the first landing pad, an upper surface of the second landing pad, and an upper sidewall of the second landing pad. The upper insulating layer may be a material layer having an etch selectivity with respect to the intermediate interlayer insulating layer.

In another embodiment, an upper interlayer insulating layer covering the intermediate interlayer insulating layer and the conductive line may be provided. A node contact plug or a storage node electrode may be provided through the upper interlayer insulating layer and the intermediate interlayer insulating layer to be electrically connected to the first landing pad.

According to another aspect of the present invention for achieving the above technical problem, a method of manufacturing a semiconductor memory cell is provided. The method of manufacturing a semiconductor memory cell includes forming a preliminary lower insulating film on a semiconductor substrate, wherein the preliminary lower insulating film is formed to have first and second openings spaced apart from each other while exposing the semiconductor substrate. First and second landing pads are formed in the first and second openings, respectively, wherein the first landing pad is formed to have an upper surface at the same level as an upper surface of the preliminary lower insulating layer, and the second landing pad. Is formed to have an upper surface of a lower level than an upper surface of the preliminary lower insulating layer to provide a recessed region on the second landing pad. An upper insulating layer is formed in the recessed area to cover the second landing pad. An intermediate interlayer insulating layer covering the first landing pad and the upper insulating layer is formed. A conductive line electrically connected to the second landing pad is formed on the intermediate interlayer insulating layer through a contact hole penetrating through the intermediate interlayer insulating layer and the upper insulating layer.

In some embodiments of the present disclosure, forming the second landing pad may form a buried conductive layer pattern in the second opening. A photoresist pattern having an opening for exposing the buried conductive layer pattern may be formed on the preliminary lower insulating layer. A portion of the buried conductive layer pattern may be etched using the photoresist pattern as an etch mask. The photoresist pattern may be removed.

In other embodiments, after the contact hole is formed, a metal silicide layer may be formed under the contact hole, and the metal silicide layer may have an upper surface lower than an upper surface of the first landing pad.

In still other embodiments, forming the upper insulating layer may include forming the lower insulating layer by etching the preliminary lower insulating layer on the whole surface to expose the upper sidewalls of the first and second landing pads. An upper insulating layer may be formed to cover an upper surface of the second landing pad and upper sidewalls of the exposed first and second landing pads.

In another embodiment, after the conductive line is formed, the intermediate interlayer insulating film and the upper interlayer insulating film covering the conductive line may be formed. The node contact plug may be formed to penetrate the upper interlayer insulating layer and the intermediate interlayer insulating layer to be in contact with the first landing pad.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout. Also, an element or layer is referred to as "on" or "on" of another element or layer by interposing another layer or other element in the middle as well as directly above the other element or layer. Include all cases.

First, a semiconductor memory cell according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3 and 4. 3 is a plan view of semiconductor memory cells according to an exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along line II ′ of FIG. 3.

3 and 4, an isolation layer 104 may be provided in the semiconductor substrate 100 to define the active region 102. The semiconductor substrate 100 may be a silicon wafer. The device isolation layer 104 may be an insulating film such as a high density plasma oxide (HDP oxide). Structures such as word lines 101 crossing the active region 102 may be disposed, but will be omitted for simplicity.

A lower interlayer insulating layer 120 is provided on the semiconductor substrate 100. The lower interlayer insulating layer 120 may include a lower insulating layer 110 and an upper insulating layer 119. The upper and lower insulating layers 119 and 110 may be sequentially stacked on the semiconductor substrate 100. The upper and lower insulating layers 119 and 110 may use the same material layer or different material layers. When using different material films, the lower insulating film 110 may be a silicon oxide film, and the upper insulating film 119 may be a silicon nitride film.

First landing pads 116 penetrate the lower interlayer insulating layer 120 to contact the semiconductor substrate 100. In addition, a second landing pad 118 spaced apart from the first landing pads 116 and contacting the semiconductor substrate 100 is disposed in the lower interlayer insulating layer 120. The second landing pad 118 has a top surface at a lower level than the top surfaces of the first landing pads 116. The lower insulating layer 110 may cover upper sidewalls of the semiconductor substrate 100 and the first and second landing pads 116 and 118. The upper insulating layer 119 may cover an upper sidewall of the first landing pads 116, an upper surface of the second landing pad 118, and an upper sidewall of the second landing pad 118. The landing pads 116 and 118 may be polysilicon layers. Top surfaces of the first landing pads 116 and the lower interlayer insulating layer 120 may be positioned on substantially the same plane.

A metal silicide layer 118s may be interposed between the second landing pad 118 and the upper insulating layer 119. The metal silicide layer 118s may have a top surface having a lower level than top surfaces of the first landing pads 116. The metal silicide layer 118s may include tungsten silicide layer WSi, titanium silicide layer TiSi, cobalt silicide layer CoSi, nickel silicide layer NiSi, molybdenum silicide layer MoSi, zirconium silicide layer ZrSi, It may be one material film selected from the group consisting of a platinum silicide layer (PtSi), an iridium silicide layer (IrSi), and a tantalum silicide layer (TaSi).

An intermediate interlayer insulating layer 122 is disposed on the first landing pads 116 and the lower interlayer insulating layer 120. The intermediate interlayer insulating layer 122 may be a material layer having an etching selectivity with respect to the upper insulating layer 119, for example, a silicon oxide layer. A conductive line 133 electrically connected to the second landing pad 118 through the contact hole 124 penetrating through the intermediate interlayer insulating layer 122 and the upper insulating layer 119 on the intermediate interlayer insulating layer 122. ) Is placed. The conductive line 133 may include a contact plug 128 filling the inside of the contact hole 124 and a wiring pattern 132 disposed on the contact plug 128. The contact plug 128 may be a bit line contact plug, and the wiring pattern 132 may be a bit line. The conductive line 133 may be a metal film such as tungsten. In addition, a plug spacer 126 may be disposed to surround sidewalls of the contact plug 128. The plug spacer 126 may be a titanium nitride layer TiN. The capping layer pattern 134 may be disposed on the conductive line 133. The capping layer pattern 134 may be a silicon nitride layer. Bit line spacers 136 may be disposed on sidewalls of the wiring pattern 132 and the capping layer pattern 134.

The conductive line 133 may be electrically connected to the semiconductor substrate 100 through the metal silicide layer 118s and the second landing pad 118. Here, the metal silicide layer 118s serves to reduce the contact resistance between the conductive line 133 and the second landing pad 118.

An upper interlayer insulating layer 140 may be provided to cover the conductive line 133 and the intermediate interlayer insulating layer 122. The upper interlayer insulating layer 140 may be a silicon oxide layer. In this case, the bit line spacer 136 may be a material film having an etch selectivity with respect to the upper interlayer insulating layer 140. For example, the bit line spacer 136 may be a silicon nitride layer.

 Conductive patterns such as node contact plugs 146 may contact the first landing pads 116 through the upper interlayer insulating layer 140 and the intermediate interlayer insulating layer 122. Sidewalls of the node contact plugs 146 may be surrounded by node contact spacers 144. The node contact spacer 144 may be a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. In another embodiment, storage node electrodes (not shown) may be formed in direct contact with the first landing pads 116 instead of the node contact plugs 146 in the conductive patterns.

Hereinafter, a method of manufacturing a semiconductor memory cell according to an embodiment of the present invention will be described with reference to FIGS. 3 to 9. 5 to 9 are cross-sectional views taken along the line II ′ of FIG. 3 to explain a method of manufacturing a semiconductor memory cell according to an embodiment of the present invention.

3 and 5, an isolation layer 104 may be formed in the semiconductor substrate 100 to define the active region 102. The device isolation layer 104 may be formed of an insulating film such as a high density plasma oxide (HDP oxide). Structures such as word lines 101 crossing the active region 102 may be formed, but will be omitted for simplicity.

The preliminary lower insulating layer 110a is formed on the entire surface of the semiconductor substrate 100 having the device isolation layer 104. The preliminary lower insulating layer 110a is patterned to form first openings 112 and second openings 114 spaced apart from each other while exposing the semiconductor substrate 100. The preliminary lower insulating layer 110a may be formed of a silicon oxide layer. The first openings 112 may be storage node landing pad holes, and the second opening 114 may serve as a bit line landing pad hole.

A landing pad conductive layer may be formed to fill the first and second openings 112 and 114 and cover the entire surface of the semiconductor substrate 100. The landing pad conductive layer may be formed of a polysilicon layer. The landing pad conductive layer may be planarized to form first landing pads 116 and a buried conductive layer pattern 117 in contact with the active region 102 in the first and second openings 112 and 114. The first landing pads 116 have an upper surface at the same level as the upper surface of the preliminary lower insulating layer 110a. The first landing pads 116 may be storage node landing pads. The planarization of the landing pad conductive layer may be performed by a chemical mechanical polishing (CMP) process or an etch back process using the preliminary lower insulating layer 110a as a stop layer.

3 and 6, a portion of the buried conductive layer pattern 117 is removed to form a second landing pad 118. The process of forming the second landing pad 118 may be as follows. A photoresist pattern 50 having an opening 52 exposing the buried conductive layer pattern 117 may be formed on the semiconductor substrate 100 having the preliminary lower insulating layer 110a. An upper portion of the buried conductive layer pattern 117 may be etched using the photoresist pattern 50 as an etching mask. Thereafter, the photoresist pattern 50 is removed. In this case, the buried conductive layer pattern 117 may be removed to a thickness of 10 Å to 500 Å. As a result, the second landing pad 118 has a lower level than the upper surface of the first landing pad 116 at a level lower than the upper surface of the preliminary lower insulating layer 110a. That is, the second landing pad 118 is recessed downward and has an area recessed above the second landing pad 118. The second landing pad 118 may be a bit line contact pad.

Referring to FIGS. 3 and 7, the preliminary lower insulating layer 110a may be etched entirely to expose the upper sidewalls of the first and second landing pads 116 and 118 to form the lower insulating layer 110. Can be. In this case, the etching may be performed by isotropic etching.

Subsequently, an upper insulating layer 119 covering an upper surface of the second landing pad 118 and upper sidewalls of the exposed first and second landing pads 116 and 118 on the lower insulating layer 110. To form. The upper insulating layer 119 may use the same material film as that of the lower insulating film 110 or a different material film. When the upper and lower insulating layers 119 and 110 are different material layers, the lower insulating layer 110 may be a silicon oxide layer, and the upper insulating layer 119 may be a silicon nitride layer. The upper insulating layer 119 may be formed by a planarization process. For example, a silicon nitride layer may be formed to cover the entire surface of the semiconductor substrate 100 having the partially exposed first and second landing pads 116 and 118. The upper insulating layer 119 may be formed by planarizing the silicon nitride layer using the first landing pads 116 as a stop layer. As a result, a lower interlayer insulating film 120 having the upper and lower insulating films 119 and 110 is formed. Meanwhile, in another embodiment, the upper insulating layer 119 may be formed only on the second landing pad 118 by adjusting the depth of etching of the preliminary lower insulating layer 110a.

3 and 8, an intermediate interlayer insulating layer 122 is formed on an entire surface of the semiconductor substrate 100 having the first landing pads 116 and the lower interlayer insulating layer 120. The intermediate interlayer insulating layer 122 may be a material layer having an etching selectivity with respect to the upper insulating layer 119, for example, a silicon oxide layer.

Subsequently, the intermediate interlayer insulating layer 122 and the upper insulating layer 119 may be patterned to form a contact hole 124 partially exposing the second landing pad 118. Plug spacers 126 may be formed on sidewalls of the contact hole 124. The plug spacer 126 may be a silicon nitride film or a silicon oxynitride film.

Subsequently, a metal silicide layer 118s may be formed in the second landing pad 118 under the contact hole 124 using a silicide process. Specifically, a metal film covering the inner wall of the contact hole 124 and the intermediate interlayer insulating film 122 may be stacked. The metal film is made of tungsten (W), titanium (Ti), cobalt (Co), nickel (Ni), molybdenum (Mo), zirconium (Zr), platinum (Pt), iridium (Ir) and tantalum (Ta). It can be the one chosen from the crowd. The metal silicide layer 118s may be formed on the second landing pad 118 by heat-treating the semiconductor substrate 100 having the metal layer. Next, the metal film remaining after the reaction is removed. As a result, the metal silicide film 118s is formed of a tungsten silicide film (WSi), a titanium silicide film (TiSi), a cobalt silicide film (CoSi), a nickel silicide film (NiSi), a molybdenum silicide film (MoSi), a zirconium silicide film ( ZrSi), platinum silicide layer (PtSi), iridium silicide layer (IrSi), or tantalum silicide layer (TaSi). Here, the metal silicide layer 118s may be formed to have an upper surface having a lower level than an upper surface of the first landing pad 116.

3 and 9, a conductive line 133 may be formed on the intermediate interlayer insulating layer 122 to contact the second landing pad 118 through the contact hole 124. Specifically, a conductive film may be stacked to fill the contact hole 124 and to cover the intermediate interlayer insulating film 122. As a result, the contact plug 128 may be formed in the contact hole 124. Subsequently, a capping layer pattern 134 may be formed on the conductive layer. The wiring pattern 132 may be formed by etching the conductive layer using the capping layer pattern 134 as an etching mask. Thus, the conductive line 133 is completed. The capping layer pattern 134 may be formed by a patterning process using a photolithography process. Due to the misalignment of the photo process, the capping layer pattern 134 may overlap a portion of the second landing pad 118. As a result, as shown in FIG. 4, the wiring pattern 132 may not cover all of the second landing pads 118 and may overlap a part of the wiring pattern 132. The contact plug 128 and the wiring pattern 132 may be adopted as bit line contact plugs and bit lines, respectively.

Subsequently, bit line spacers 136 may be formed on sidewalls of the wiring pattern 132 and the capping layer pattern 134. An upper interlayer insulating layer 140 may be formed on the semiconductor substrate 100 including the conductive line 133 and the capping layer pattern 134. The upper interlayer insulating layer 140 may be formed of a silicon oxide layer.

Referring to FIGS. 3 and 4 again, node contact holes 142 are formed through the upper interlayer insulating layer 140 and the intermediate interlayer insulating layer 122 to expose the first landing pads 116. Can be. Subsequently, the node contact holes 142 may be extended using an isotropic etching process. As a result, the node contact holes 142 may expose the bit line spacer 136, the plug spacer 126, and the upper insulating layer 119. The upper insulating layer 119 may have an etching selectivity with respect to the intermediate interlayer insulating layer 122. Therefore, the metal silicide layer 118s and the second landing pad 118 are protected without being exposed during the isotropic etching process. In another embodiment, when the upper insulating layer 119 does not have an etching selectivity with respect to the intermediate interlayer insulating layer 122, the upper insulating layer 119 may be partially etched and recessed downward. However, when the upper insulating layer 119 has a thickness margin necessary for an isotropic etching process, the metal silicide layer 118s and the second landing pad 118 may be protected.

Node contact spacers 144 may be formed on sidewalls of the node contact holes 142. The node contact spacers 144 may be formed of an insulating film, such as a silicon oxide film, a silicon nitride film, or a combination thereof.

A node contact conductive layer may be formed to fill the node contact holes 142 and cover the upper interlayer insulating layer 140. The node contact conductive layer may be planarized to form conductive patterns such as node contact plugs 146. The planarization of the node contact conductive layer may be performed by a chemical mechanical polishing process or an etch back process. In another embodiment, storage node electrodes (not shown) in direct contact with the first landing pads 116 in the node contact holes 142 instead of the node contact plugs 146 with the conductive patterns. Can be formed.

According to the present invention described above, the second landing pad 118 and the metal silicide layer 118s are formed to have upper levels of lower levels than upper surfaces of the first landing pads 116. In addition, the upper insulating layer 122 is formed to cover the metal silicide layer 118s and the second landing pad 118. Accordingly, the metal silicide layer 118s and the second landing pad 118 are not exposed while the node contact holes 142 are formed. As a result, no short circuit occurs between the node contact plugs 146 and the second landing pad 118.

In addition, when the metal silicide layer 118s has an upper surface at the same level as the first landing pad 116, the metal silicide layer 118s is partially formed in the process of forming the node contact hole 142. It may be etched and only part of it may remain. The area of the remaining metal silicide layer 118s may be smaller than the designed area. Accordingly, the contact resistance between the contact plug 128 and the remaining metal silicide layer 118s increases. In the present invention, the metal silicide layer 118s is not etched to secure a contact area of the metal silicide layer 118s.

As described above, according to the present invention, the second landing pad and the metal silicide film are formed to have a top surface of a lower level than the top surface of the first landing pad. In addition, an upper insulating layer is formed to cover the metal silicide layer and the second landing pad. Accordingly, the second landing pad and the metal silicide layer are not exposed in the process of forming the node contact hole on the first landing pad. Accordingly, a short circuit is prevented between the conductive pattern filling the node contact hole and the second landing pad or between the conductive pattern and the metal silicide layer. In addition, the metal silicide layer may be protected from the isotropic etching of the node contact hole to form a contact area in contact with the conductive pattern.

Claims (12)

A lower interlayer insulating film covering the semiconductor substrate; A first landing pad penetrating the lower interlayer insulating layer to be in contact with the semiconductor substrate; A second landing pad having an upper surface having a lower level than an upper surface of the first landing pad in the lower interlayer insulating layer, the second landing pad being spaced apart from the first landing pad and in contact with the semiconductor substrate; An intermediate interlayer insulating layer covering the first landing pad and the lower interlayer insulating layer; And And conductive lines disposed on the intermediate interlayer insulating layer and electrically connected to the second landing pad through the intermediate interlayer insulating layer and the lower interlayer insulating layer. The method of claim 1, And a metal silicide layer interposed between the second landing pad and the conductive line and having a top surface of a lower level than the top surface of the first landing pad. The method of claim 2, And the lower interlayer insulating film covers the metal silicide film. The method of claim 1, wherein the lower interlayer insulating film A lower insulating film covering the lower sidewalls of the semiconductor substrate and the first and second landing pads; And And an upper insulating film formed on the lower insulating film and covering an upper sidewall of the first landing pad, an upper surface of the second landing pad, and an upper sidewall of the second landing pad. The method of claim 4, wherein And the upper insulating film is a material film having an etch selectivity with respect to the intermediate interlayer insulating film. The method of claim 1, An upper interlayer insulating layer covering the intermediate interlayer insulating layer and the conductive line; And And a node contact plug or a storage node electrode electrically connected to the first landing pad through the upper interlayer insulating layer and the intermediate interlayer insulating layer. Forming a preliminary lower insulating film on the semiconductor substrate, wherein the preliminary lower insulating film is formed to have first and second openings spaced apart from each other while exposing the semiconductor substrate; First and second landing pads are formed in the first and second openings, respectively, wherein the first landing pad is formed to have an upper surface at the same level as an upper surface of the preliminary lower insulating layer, and the second landing pad. Is formed to have an upper surface of a lower level than an upper surface of the preliminary lower insulating film to provide a recessed region on the second landing pad, Forming an upper insulating film covering the second landing pad in the recessed region, Forming an intermediate interlayer insulating layer covering the first landing pad and the upper insulating layer; Forming a conductive line electrically connected to the second landing pad through a contact hole penetrating through the intermediate interlayer insulating film and the upper insulating film on the intermediate interlayer insulating film. The method of claim 7, wherein Forming the second landing pad forms a buried conductive film pattern in the second opening, Forming a photoresist pattern having an opening exposing the buried conductive film pattern on the preliminary lower insulating film, A portion of the buried conductive layer pattern is etched using the photoresist pattern as an etching mask, Removing the photoresist pattern. The method of claim 7, wherein  After forming the contact hole, a metal silicide layer is formed below the contact hole, wherein the metal silicide layer has an upper surface lower than an upper surface of the first landing pad. The method of claim 7, wherein Forming the upper insulating film to form a lower insulating film by etching the preliminary lower insulating film to the entire surface to expose the upper sidewalls of the first and second landing pads, And forming an upper insulating film covering an upper surface of the second landing pad and on upper sidewalls of the exposed first and second landing pads. The method of claim 7, wherein And the upper insulating film is a material film having an etch selectivity with respect to the intermediate interlayer insulating film. The method of claim 7, wherein After the conductive lines are formed, an intermediate interlayer insulating film and an upper interlayer insulating film covering the conductive lines are formed; And forming a node contact plug or a storage node electrode electrically connected to the first landing pad through the upper interlayer insulating layer and the intermediate interlayer insulating layer.

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