JP2004335522A - Semiconductor storage device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method by which a semiconductor storage device, in which the contacts on a peripheral circuit are formed of a metallic material and contacts on the source and drain of a MOS transistor constituting a memory cell are made of polycrystalline silicon, can be manufactured through a smaller number of manufacturing steps. <P>SOLUTION: The method of manufacturing the semiconductor storage device includes a step of forming first MIS transistors 4 in the memory cell 100 of a semiconductor substrate 1 and a second MIS transistor 7 in a peripheral circuit section 200, a step of forming a first interlayer insulating film 14, and a step of forming a bit-line contact hole 15. The method also includes a step of forming a first polycrystalline silicon film 16, a step of forming peripheral-circuit contact holes 17 and 18, and a step of forming conductive films 19 and 20. In addition, the method also includes a step of forming first polycrystalline silicon plugs and conductive plugs by removing the first polycrystalline silicon film 16 and conductive films 19 and 20 on the outside of the bit-line contact hole 15 and peripheral-circuit contact holes 17 and 18. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a semiconductor memory device including a memory cell including a capacitor and a MIS (Metal Insulator Semiconductor) transistor and a method of manufacturing the same.
[0002]
[Prior art]
A DRAM (Dynamic Random Access Memory) and an FRAM (Ferroelectric Random Access Memory: ferroelectric memory) have a memory cell including a capacitance element and a MIS (Metal Insulator Semiconductor) transistor, which is a typical semiconductor storage device. Such a semiconductor memory device includes a memory cell portion in which memory cells are arranged in a matrix, and a peripheral circuit portion in which a peripheral circuit for reading and writing data from the memory cells is arranged.
[0003]
Since a peripheral circuit is required to operate at high speed, a contact reaching a MOS transistor constituting the peripheral circuit may be formed of a metal material. Forming the contact with a metal material having a high conductivity reduces the resistance of the contact and effectively increases the operating speed of the peripheral circuit.
[0004]
On the other hand, in order to improve the reliability of the operation of the memory cell, it is preferable that the contact reaching the source and the drain of the memory cell transistor be formed of polycrystalline silicon. Forming the contacts that reach the source and drain of the memory cell transistor with a metal material increases the junction leakage of the source and drain. An increase in the junction leak undesirably lowers the reliability of the operation of the memory cell. In order to reduce the junction leakage, it is preferable that the contacts reaching the source and the drain of the memory cell transistor are formed of polycrystalline silicon.
[0005]
Patent Document 1 discloses a method for manufacturing a semiconductor memory device in which a contact reaching a MOS transistor forming a peripheral circuit is formed of a metal material, and a contact reaching a source and a drain of a memory cell transistor is formed of polycrystalline silicon. are doing.
[0006]
In such a method for manufacturing a semiconductor memory device, it is desired that the number of manufacturing steps be reduced. The reduction in the number of manufacturing steps reduces the manufacturing cost of the semiconductor memory device and effectively improves the competitiveness of the semiconductor memory device.
[0007]
Further, in such a method of manufacturing a semiconductor memory device, it is desired that two contacts reaching the source and drain of the memory cell transistor can be reliably formed without short-circuit. Recent high integration of semiconductor memory devices requires a reduction in the interval between these two contacts. Reducing the spacing between the contacts tends to cause shorts between those contacts. For example, photolithographic failures cause shorts between contacts. It is desired that short-circuiting of the two contacts reaching the source and drain of the memory cell transistor be avoided.
[0008]
Further, in such a method of manufacturing a semiconductor memory device, it is desired that the contact (storage contact) connecting the memory cell capacitor and the source / drain of the memory cell transistor has low resistance. It is not preferable that the resistance of the storage contact is large, because the access speed of the semiconductor memory device is reduced.
[0009]
[Patent Document 1]
JP-A-11-68062
[0010]
[Problems to be solved by the invention]
An object of the present invention is to manufacture a semiconductor memory device in which a contact reaching a peripheral circuit is formed of a metal material and a contact reaching a source and a drain of a MOS transistor forming a memory cell is formed of polycrystalline silicon. An object of the present invention is to provide a technology for manufacturing in a process.
Another object of the present invention is to provide a memory for a semiconductor memory device in which a contact reaching a peripheral circuit is formed of a metal material and a contact reaching a source and a drain of a MOS transistor forming a memory cell is formed of polycrystalline silicon. It is an object of the present invention to provide a technology for facilitating a photoresist process for forming two contacts reaching a source and a drain of a MOS transistor constituting a cell.
Still another object of the present invention is a semiconductor memory device in which a contact reaching a peripheral circuit is formed of a metal material, and a contact reaching a source and a drain of a MOS transistor constituting a memory cell is formed of polycrystalline silicon. It is an object of the present invention to provide a technique for reducing the resistance of a storage contact connecting a memory cell capacitor and a source / drain of a MOS transistor.
[0011]
[Means for Solving the Problems]
The means for solving the problem will be described below using the numbers and symbols used in [Embodiments of the Invention]. These numbers and symbols are added to clarify the correspondence between the description in [Claims] and the description in [Embodiment of the Invention]. However, the added numbers and symbols must not be used for interpreting the technical scope of the invention described in [Claims].
[0012]
In one aspect, a method for manufacturing a semiconductor memory device according to the present invention includes:
(A) First MIS transistors (3, 4, 11, 12) are formed in a memory cell array section (100) of a semiconductor substrate (1), and second MIS transistors (6, 7, 13) are formed in a peripheral circuit section (200). Forming,
(B) forming a first interlayer insulating film (14) covering the first MIS transistors (3, 4, 11, 12) and the second MIS transistors (6, 7, 13);
(C) forming a bit line contact hole (15) penetrating through the first interlayer insulating film (14) and reaching one source / drain (11) of the first MIS transistor (3, 4, 11, 12); The process of
(D) forming a first polycrystalline silicon film (16) so as to cover the first interlayer insulating film (14) and bury the bit line contact (15);
(E) Peripheral circuit contact holes (17, 18) penetrating through the first interlayer insulating film (14) and the first polycrystalline silicon film (16) and reaching the second MIS transistors (6, 7, 13). ), And
(F) forming a conductive film (19, 20) that covers the first polycrystalline silicon film (16), includes a metal film (20), and fills the peripheral circuit contact holes (17, 18); When,
(G) a portion of the first polycrystalline silicon film (16) outside the bit line contact (15) and a portion of the conductive film (19, 20) outside the peripheral circuit contact hole (18). Forming a first polycrystalline silicon plug (21) for filling the bit line contact hole (15) and a conductive plug (22, 23) for filling the peripheral circuit contact hole (17, 18). When,
(H) forming a bit line (24) connected to the first polycrystalline silicon plug (21);
(I) forming a wiring (25) connected to the conductive plugs (22, 23). The semiconductor memory device manufacturing method of simultaneously forming the first polycrystalline silicon plug (21) and the conductive plugs (22, 23) effectively reduces the number of manufacturing steps.
[0013]
In the semiconductor memory device manufacturing method, a portion of the first polycrystalline silicon film (16) outside the bit line contact (15) and the peripheral circuit contact hole (17, 20) of the conductive film (19, 20). The removal of the part outside of 18) (that is, the formation of the first polycrystalline silicon plug (21) and the conductive plug (23)) is typically performed by using a CMP (Chemical Mechanical Polishing) technique. Done.
[0014]
The conductive films (19, 20) are interposed between the metal film (20) and the first polysilicon film (16), and the metal film (20) and the first polysilicon film ( It is preferable to further include a barrier metal film (19) for preventing a reaction with (16). When the metal film (20) is formed of tungsten, the barrier metal film (19) is preferably a laminated film including a titanium film and a titanium nitride film.
[0015]
The method for manufacturing a semiconductor storage device further includes:
(J) forming a second interlayer insulating film (30) covering the first interlayer insulating film (14), the bit line (24), and the wiring (25);
(K) another source / drain (12) penetrating through the first interlayer insulating film (14) and the second interlayer insulating film (30) and further comprising the MIS transistor (3, 4, 11, 12); Forming a second polycrystalline silicon plug (32) reaching
(L) forming a capacitive element (33, and a capacitor insulating film and a capacitor upper electrode, not shown) connected to the second polycrystalline silicon plug (32) and for holding data;
Is preferably provided. Such a method for manufacturing a semiconductor memory device makes it possible to form a storage contact with one polycrystalline silicon plug (32). Further, in the method for manufacturing a semiconductor memory device, the bit line contact hole (15) filled with the first polysilicon plug (21) and the contact hole (31) filled with the second polysilicon plug (32) are formed. Formed separately. This facilitates securing a photolithography margin for forming these contact holes (15, 31). Effectively reduces storage contact resistance.
[0016]
The second polycrystalline silicon plug (32) is formed so as to have a concave portion on an upper portion thereof, and one electrode (33) of the capacitive element is joined to the second polycrystalline silicon plug at the concave portion. Is preferred. Such a structure increases the contact area between the second polysilicon plug (32) and the one electrode (33), and effectively reduces the resistance of the storage contact.
[0017]
In another aspect, a semiconductor memory device according to the present invention includes a semiconductor substrate (1), and first MIS transistors (3, 4, 11, 12) formed in a memory cell array section (100) of the semiconductor substrate (1). A second MIS transistor (6, 7, 13) formed in a peripheral circuit portion (200) of the semiconductor substrate (1), the first MIS transistor (3, 4, 11, 12) and the second MIS transistor (6). , 7, 13), and a source / drain of the first MIS transistor (3, 4, 11, 12) penetrating through the first interlayer insulating film (14). A first polycrystalline silicon plug reaching the first polycrystalline silicon plug, a bit line connected to the first polycrystalline silicon plug, and the first interlayer insulating film; The conductive plugs (22, 23) reaching the second MIS transistors (6, 7, 13), and the conductive plugs (22, 23) include metal parts (22b, 23b) formed of metal. A wiring (25) connected to the plug (22, 23); a second interlayer insulating film (30) covering the first interlayer insulating film (14), the bit line (24) and the wiring (25); And penetrating through the first interlayer insulating film (14) and the second interlayer insulating film (30) and to another source / drain (12) of the first MIS transistor (3, 4, 11, 12). A second polycrystalline silicon plug (32) that reaches the device and a capacitive element (33, etc.) connected to the second polycrystalline silicon plug (32) for retaining data.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of a semiconductor memory device manufacturing method according to the present invention will be described with reference to the accompanying drawings.
[0019]
(First embodiment)
FIG. 1 is a plan view showing a first embodiment of a method for manufacturing a semiconductor memory device according to the present invention, and FIGS. 2 to 11 are sectional views showing a first embodiment of the method for manufacturing a semiconductor memory device according to the present invention. It is. FIGS. 2 to 11 show the structure of the memory cell unit 100 and the structure of the peripheral circuit unit 200 in the AA ′ section, the BB ′ section, and the CC ′ section of FIG.
[0020]
As shown in FIG. 2, the manufacturing method starts with a step of forming a MOS transistor on the surface of the semiconductor substrate 1. More specifically, the element isolation 2 is formed on the surface of the semiconductor substrate 1 by the STI technique. Subsequently, a thermal oxide film having a thickness of 10 nm, a polycrystalline silicon film having a thickness of 10 nm, a tungsten silicide film having a thickness of 10 nm, and a silicon nitride film having a thickness of 150 nm are sequentially formed. The silicon film, the tungsten silicide film, and the silicon nitride film are patterned. By this patterning, a gate insulating film 3, a gate electrode 4, and a silicon nitride layer 5 are formed in the memory cell portion 100, and a gate insulating film 6, a gate electrode 7, and a silicon nitride layer 8 are formed in the peripheral circuit portion 200. Is done. Since the gate electrode 4 provided in the memory cell portion 100 functions as a word line, it is sometimes referred to as a word line 4 below. Gate electrode 4 includes a polycrystalline silicon layer 4a and a tungsten silicide layer 4b, and gate electrode 7 includes a polycrystalline silicon layer 7a and a tungsten silicide layer 7b. The gate electrode 7 arranged in the peripheral circuit section 200 functions as a wiring on the element isolation 2 and functions as a gate of a MOS transistor on the active region. Subsequently, after a silicon nitride film is formed on the entire surface, the silicon nitride film is etched back. As a result of this etch-back, sidewalls 9 are formed on the side surfaces of the gate electrode 4 and the silicon nitride layer 5, and sidewalls 10 are formed on the side surfaces of the gate electrode 7 and the silicon nitride layer 8. Further, diffusion layers 11 and 12 are formed on the surface of the semiconductor substrate 1 in the memory cell section 100 and a diffusion layer 13 is formed in the peripheral circuit section 200 by the ion implantation technique. The diffusion layers 11 and 12 function as the source / drain of the memory cell transistor. As described later, the diffusion layer 11 is connected to a bit line, and the diffusion layer 12 is connected to a memory cell capacitor. The diffusion layer 13 of the peripheral circuit section 200 can be used as a source / drain of a MOS transistor of the peripheral circuit and other elements of the peripheral circuit.
[0021]
Subsequently, after a 800-nm-thick BPSG film is formed, the surface portion of the BPSG film is removed by about 300 nm by CMP (Chemical Mechanical Polishing) technology, and a flat interlayer insulating film 14 is formed.
[0022]
Subsequently, as shown in FIG. 3, a contact hole 15 penetrating through the interlayer insulating film 14 and reaching the diffusion layer 11 is formed by photolithography and etching. The etching of the contact hole 15 is performed under conditions where the selectivity of silicon oxide to silicon nitride is sufficiently high. For example, CHF ₃ An etching gas containing a gas and a CO gas is used. The contact hole 15 is self-aligned so as to pass between the gate electrodes 4 by being etched under the condition that the selectivity is sufficiently high (self-aligned).
[0023]
After the formation of the contact hole 10, a 200 nm-thick polycrystalline silicon film 11 is grown so as to cover the interlayer insulating film 14 and fill the contact hole 15 as shown in FIG.
[0024]
Subsequently, as shown in FIG. 5, a contact hole 17 that reaches the gate electrode 7 through the polycrystalline silicon film 16, the interlayer insulating film 14, and the silicon nitride layer 8 by photolithography and etching. Then, a contact hole 18 that reaches the diffusion layer 13 through the polycrystalline silicon film 11 and the interlayer insulating film 14 is formed in the peripheral circuit portion 200. The contact holes 17 and 18 are formed, for example, by C ₄ F ₈ The etching is performed by using an etching gas containing a gas and a CO gas.
[0025]
As shown in FIG. 6, a barrier metal film 19 having a thickness of 40 nm is formed so as to cover the upper surface of polycrystalline silicon film 16 and the side and bottom surfaces of contact holes 17 and 18. After the formation of the barrier metal film 19, a 200-nm-thick tungsten film 20 is formed so as to cover the barrier metal film 19 and fill the contact holes 17 and 18. The barrier metal film 19 prevents a reaction between the formed tungsten film 20 and the polycrystalline silicon film 16. As the barrier metal film 19, for example, a Ti film (not shown) covering the polycrystalline silicon film 16 and the contact holes 17, 18 and a TiN film (not shown) covering the Ti film can be used. In this case, the tungsten film 20 is formed on the TiN film.
[0026]
Subsequently, as shown in FIG. 7, unnecessary portions of the polycrystalline silicon film 16, the barrier metal film 19, and the tungsten film 20 (that is, portions outside the contact holes 15, 17, and 18) are formed. Removed by CMP. By this CMP process, a polycrystalline silicon plug 21 filling the contact hole 15 is formed in the memory cell portion 100, and tungsten plugs 22 and 23 filling the contact holes 17 and 18 are formed in the peripheral circuit portion 200, respectively. . The tungsten plug 22 includes a barrier metal portion 22a covering the inner surface of the contact hole 17 and a tungsten portion 22b formed thereon. The tungsten plug 23 forms a barrier metal portion 23a covering the inner surface of the contact hole 18. And a tungsten portion 23b formed thereon.
[0027]
Thus, the formation of the polycrystalline silicon plug 21 and the tungsten plugs 22 and 23 is performed by one CMP process. This is advantageous in that the number of manufacturing steps is reduced.
[0028]
Subsequently, as shown in FIG. 8, a bit line 24 is formed in the memory cell unit 100, and a peripheral circuit wiring 25 is formed in the peripheral circuit unit 200. Bit line 24 is formed on polycrystalline silicon plug 21, and peripheral circuit wiring 25 is formed on tungsten plugs 22 and 23.
[0029]
The formation of the bit line 24 and the peripheral circuit wiring 25 is performed in the following steps. After a barrier metal film, a tungsten film, and a silicon nitride film are sequentially formed, these films are patterned. By this patterning, the bit line 24 and the silicon nitride layer 26 covering the bit line 24 are formed in the memory cell portion 100, and the peripheral circuit wiring 25 and the silicon nitride layer 27 covering the peripheral circuit wiring 25 are formed in the peripheral circuit. Formed in the part 200. Each of the bit line 24 and the peripheral circuit wiring 25 is composed of a plug barrier metal layer and a tungsten layer (neither is shown) covering the barrier metal layer.
[0030]
Subsequently, after a silicon nitride film is formed on the entire surface, the silicon nitride film is etched back. By this etch back, a sidewall 28 covering the side surfaces of the bit line 24 and the silicon nitride layer 26 and a sidewall 29 covering the side surfaces of the peripheral circuit wiring 25 and the silicon nitride layer 27 are formed.
[0031]
Subsequently, as shown in FIG. 9, after an interlayer insulating film 30 covering the interlayer insulating film 14 is formed, the interlayer insulating film 30 reaches the diffusion layer 12 through the interlayer insulating film 30 and the interlayer insulating film 14. A contact hole 31 is formed. The formation of the interlayer insulating film 30 and the contact hole 31 is performed in the following steps. After a BPSG film having a thickness of 600 nm covering the interlayer insulating film 14, the bit lines 24, and the peripheral circuit wiring 25 is grown, the BPSG film is polished by CMP to a thickness of 300 nm, and the planarized interlayer insulating film 30 is formed. Is formed. After the formation of the interlayer insulating film 30, a contact hole 31 penetrating through the interlayer insulating film 30 and the interlayer insulating film 14 and reaching the diffusion layer 12 is formed by a photolithography technique and an etching technique. The etching of the contact holes 31 is performed under conditions where the selectivity of silicon oxide to silicon nitride is sufficiently high. For example, etching CHF ₃ An etching gas containing a gas and a CO gas is used. Since the etching is performed under the condition that the selectivity is sufficiently high, the contact hole 31 is formed such that it passes between the bit lines 25 and between the gate electrodes 4 (word lines 4). Self-aligned.
[0032]
Subsequently, as shown in FIG. 10, after a polycrystalline silicon film is formed so as to fill the contact hole 31, a portion of the polycrystalline silicon film outside the contact hole 31 is formed by etch back or CMP. Is removed, and a polycrystalline silicon plug 32 is formed.
[0033]
It should be noted that, in the manufacturing method of the present embodiment, the formation of the plug 21 connected to the bit line 25 and the formation of the plug 32 connected to the memory cell capacitor are performed separately. Performing the formation of the plug 21 and the formation of the plug 32 separately facilitates the photolithography process for forming the contact hole 15 and the contact hole 31 suitably. In order to simultaneously form a contact connected to the bit line and a contact connected to the memory cell capacitor, it is necessary to form an opening for defining the position of the contact in the photoresist. Higher integration of semiconductor memory devices requires a reduction in the distance between these openings, and reduces the margin of the positions of the openings. However, when the distance between these openings is reduced, the margin of the positions of the openings is reduced, and it is difficult to form these openings correctly. Such a problem can be avoided by the manufacturing method according to the present embodiment in which the formation of the plug 21 connected to the bit line 25 and the formation of the plug 32 connected to the memory cell capacitor are performed separately.
[0034]
Further, it should be noted that in the manufacturing method of the present embodiment, a storage contact for connecting the capacitor lower electrode 33 to the diffusion layer 12 can be formed by one polycrystalline silicon plug 32. Many DRAM manufacturing methods require that a contact connecting a memory cell capacitor and a memory cell transistor be formed by a plurality of plugs. This creates an interfacial resistance between the plugs and increases the contact resistance. However, according to the manufacturing method of the present embodiment, the contact connecting capacitor lower electrode 33 to diffusion layer 12 can be formed by one polysilicon plug 32, and the contact connecting capacitor lower electrode 33 to diffusion layer 12 can be formed. Resistance can be effectively suppressed.
[0035]
After the formation of the polycrystalline silicon plug 32, a capacitor lower electrode 33 is formed so as to be connected to the plug 32, as shown in FIG. The formation of the capacitor lower electrode 33 is performed as follows. After an interlayer insulating film 34 having a thickness of 2 μm covering the interlayer insulating film 30 is formed, a through hole 35 penetrating through the interlayer insulating film 34 and reaching the polycrystalline silicon plug 32 is formed. Subsequently, after a polycrystalline silicon film is formed to cover the upper surface of the interlayer insulating film 34 and the side and bottom surfaces of the through hole 35 in a conformal manner, a portion of the polycrystalline silicon film outside the through hole 35 is subjected to photolithography. The capacitor lower electrode 33 that covers the side and bottom surfaces of the through-hole 35 is removed by the technique and the etch-back technique.
[0036]
After the formation of the capacitor lower electrode 33, a capacitor insulating film and a capacitor upper electrode (both not shown) are formed by a known process, and the formation of the memory cell capacitor is completed.
[0037]
As described above, in the first embodiment, the polycrystalline silicon plug 21 and the conductive plug 23 are formed at the same time, thereby effectively reducing the number of manufacturing steps.
[0038]
Further, in the present embodiment, the storage contact for connecting the capacitor lower electrode 33 to the diffusion layer 12 is formed of one polycrystalline silicon plug 32, and the resistance of the storage contact is effectively reduced.
[0039]
Further, in the present embodiment, the formation of the plug 21 connected to the bit line 25 and the formation of the plug 32 connected to the memory cell capacitor are performed separately, so that the contact hole 15 and the contact hole 31 are formed. Photolithography process is facilitated.
[0040]
(Second embodiment)
In the second embodiment, a method of forming a contact connecting a memory cell capacitor and a memory cell transistor is changed. After the contact hole 31 is formed by the same process as that of the first embodiment (see FIG. 9), the upper surface of the interlayer insulating film 30 and the inner surface of the contact hole 31 are covered as shown in FIG. A polycrystalline silicon film 41 having a thickness of 30 nm is formed. The polycrystalline silicon film 41 completely fills the space between the gate electrodes 4 in the contact hole 31, but does not fill the entire contact hole 31. The polycrystalline silicon film 41 is formed such that a space 41 a is provided above the contact hole 31.
[0041]
After the formation of the polycrystalline silicon film 41, as shown in FIG. 13, an insulating film 42 having a thickness of 50 nm and covering the polycrystalline silicon film 41 is formed of silicon oxide.
[0042]
Subsequently, as shown in FIG. 14, a portion of the polycrystalline silicon film 41 and the insulating film 42 outside the contact hole 31 is removed by CMP to form a polycrystalline silicon plug 43. By such a process, the polycrystalline silicon plug 43 is formed so as to have a concave portion on the upper portion. The inside of the concave portion is filled with the remaining portion 42a of the insulating film 42.
[0043]
After the formation of the polycrystalline silicon plug 43, the capacitor lower electrode 44 is formed so as to be connected to the polycrystalline silicon plug 43, as shown in FIG. The formation of the capacitor lower electrode 44 is performed in the following steps. First, the interlayer insulating film 30 and the polycrystalline silicon plug 43 are covered with a 2 μm thick interlayer insulating film 45 made of silicon oxide. After the formation of the interlayer insulating film 45, a through hole 46 that penetrates the interlayer insulating film 45 and reaches the polycrystalline silicon plug 43 is formed. When forming through hole 46, remaining portion 42a of insulating film 42 remaining in the recess of polycrystalline silicon plug 43 is removed. The through-hole 46 is formed by etching the interlayer insulating film 45 under conditions that silicon nitride is hardly etched and silicon oxide is easily etched. Etching under these conditions obviates the need for through hole 46 to be perfectly aligned with polycrystalline silicon plug 43. Even if the position of the through hole 46 is shifted from the position of the polycrystalline silicon plug 43, the etching for forming the through hole 46 is performed by etching the silicon nitride layer 26 covering the upper surface of the bit line 24 and the side surface of the bit line 24. It stops at the sidewall 28 to cover, or stops at the silicon nitride layer 9 covering the upper surface of the gate electrode 4. After the through holes 46 are formed, a polycrystalline silicon film is formed to conformally cover the upper surface of the interlayer insulating film 45 and the bottom and side surfaces of the through holes 46. The portion of the polycrystalline silicon film outside the through-hole 46 is removed by photolithography and etch-back techniques, and a capacitor lower electrode 44 covering the inner surface of the through-hole 46 is formed.
[0044]
The recess provided above polycrystalline silicon plug 43 increases the contact area between plug 43 and capacitor lower electrode 44. The increase in the contact area reduces the contact resistance between the plug 43 and the capacitor lower electrode 44, thereby effectively reducing the resistance of the contact connecting the memory cell capacitor and the memory cell transistor. In order to increase the contact area as much as possible, the capacitor lower electrode 44 is preferably formed so as to fill the recess.
[0045]
After the formation of the capacitor lower electrode 44, a capacitor insulating film and a capacitor upper electrode (both not shown) are formed by a known process, and the formation of the memory cell capacitor is completed.
[0046]
In the present embodiment, a concave portion is provided above polycrystalline silicon plug 43, and capacitor lower electrode 44 and polycrystalline silicon plug 43 are joined at the concave portion. Thereby, the resistance of the contact connecting the memory cell capacitor and the memory cell transistor is reduced.
[0047]
【The invention's effect】
According to the present invention, a semiconductor memory device in which a contact reaching a peripheral circuit is formed of a metal material and a contact reaching a source and a drain of a MOS transistor forming a memory cell is formed of polycrystalline silicon can be manufactured in fewer manufacturing steps. Manufacturing techniques are provided.
According to the present invention, a memory cell of a semiconductor memory device in which a contact reaching a peripheral circuit is formed of a metal material and a contact reaching a source and a drain of a MOS transistor forming the memory cell is formed of polycrystalline silicon, A technique for facilitating a photoresist process for forming two contacts reaching a source and a drain of a MOS transistor to be constituted is provided.
According to the present invention, a memory cell capacitor of a semiconductor memory device in which a contact reaching a peripheral circuit is formed of a metal material and a contact reaching a source and a drain of a MOS transistor forming a memory cell is formed of polysilicon. And a technique for reducing the resistance of a storage contact that connects the MOS transistor and the source / drain of the MOS transistor.
[Brief description of the drawings]
FIG. 1 is a plan view showing a first embodiment of a semiconductor memory device manufacturing method according to the present invention.
FIG. 2 is a sectional view showing a first embodiment of a method for manufacturing a semiconductor memory device according to the present invention.
FIG. 3 is a sectional view showing a first embodiment of a method for manufacturing a semiconductor memory device according to the present invention.
FIG. 4 is a sectional view showing a first embodiment of a method for manufacturing a semiconductor memory device according to the present invention.
FIG. 5 is a sectional view showing a first embodiment of a method for manufacturing a semiconductor memory device according to the present invention.
FIG. 6 is a sectional view showing a first embodiment of a method for manufacturing a semiconductor memory device according to the present invention.
FIG. 7 is a sectional view showing a first embodiment of a method for manufacturing a semiconductor memory device according to the present invention.
FIG. 8 is a sectional view showing a first embodiment of a method for manufacturing a semiconductor memory device according to the present invention.
FIG. 9 is a sectional view showing a first embodiment of a method for manufacturing a semiconductor memory device according to the present invention.
FIG. 10 is a sectional view showing a first embodiment of a method for manufacturing a semiconductor memory device according to the present invention.
FIG. 11 is a sectional view showing a first embodiment of a method for manufacturing a semiconductor memory device according to the present invention.
FIG. 12 is a sectional view showing a second embodiment of a method for manufacturing a semiconductor memory device according to the present invention.
FIG. 13 is a sectional view showing a second embodiment of the method of manufacturing the semiconductor memory device according to the present invention.
FIG. 14 is a sectional view showing a second embodiment of the method of manufacturing the semiconductor memory device according to the present invention.
FIG. 15 is a sectional view showing a second embodiment of a method for manufacturing a semiconductor memory device according to the present invention.
[Explanation of symbols]
1: Semiconductor substrate
2: element separation
3, 6: gate insulating film
4, 7: gate electrode
5, 8: silicon nitride layer
9, 10: Side wall
11, 12, 13: diffusion layer
14: interlayer insulating film
15: Contact hole
16: Polycrystalline silicon film
17, 18: Contact hole
19: Barrier metal film
20: Tungsten film
21: Polycrystalline silicon plug
22, 23: Tungsten plug
22a, 23a: barrier metal part
22b, 23b: tungsten part
24: bit line
25: Peripheral circuit wiring
26, 27: silicon nitride layer
28, 29: Sidewall
30: interlayer insulating film
31: Contact hole
32: Polycrystalline silicon plug
33: Capacitor lower electrode
34: interlayer insulating film
35: Through hole
41: Polycrystalline silicon film
42: Insulating film
42a: remaining portion
43: Polycrystalline silicon plug
44: Capacitor lower electrode
45: interlayer insulating film
46: Through hole

Claims (6)

(A) forming a first MIS transistor in a memory cell array portion of a semiconductor substrate and forming a second MIS transistor in a peripheral circuit portion;
(B) forming a first interlayer insulating film covering the first MIS transistor and the second MIS transistor;
(C) forming a bit line contact hole penetrating the first interlayer insulating film and reaching one source / drain of the first MIS transistor;
(D) forming a first polycrystalline silicon film so as to cover the first interlayer insulating film and bury the bit line contact;
(E) forming a peripheral circuit contact hole penetrating through the first interlayer insulating film and the first polycrystalline silicon film and reaching the second MIS transistor;
(F) forming a conductive film that covers the first polycrystalline silicon film, includes a metal film, and fills the peripheral circuit contact hole;
(G) removing a portion of the first polycrystalline silicon film outside the bit line contact hole and a portion of the conductive film outside the peripheral circuit contact hole to bury the bit line contact; (1) forming a polycrystalline silicon plug and a conductive plug filling the peripheral circuit contact hole;
(H) forming a bit line connected to the first polycrystalline silicon plug;
(I) forming a wiring connected to the conductive plug. 2. The method of manufacturing a semiconductor memory device according to claim 1,
The method of manufacturing a semiconductor memory device, wherein the conductive film further includes a barrier metal film interposed between the metal film and the first polysilicon film to prevent a reaction between the metal film and the first polysilicon film. Method. 2. The method of manufacturing a semiconductor memory device according to claim 1,
Furthermore,
(J) forming a second interlayer insulating film covering the first interlayer insulating film, the bit line, and the wiring;
(K) forming a second polysilicon plug penetrating through the first interlayer insulating film and the second interlayer insulating film and reaching another source / drain of the first MIS transistor;
(L) forming a capacitive element connected to the second polycrystalline silicon plug for holding data. The method of manufacturing a semiconductor memory device according to claim 3,
The second polycrystalline silicon plug is formed to have a concave portion on an upper portion thereof,
A method for manufacturing a semiconductor memory device, wherein one electrode of the capacitive element is joined to the second polycrystalline silicon plug at the recess. A semiconductor substrate;
A first MIS transistor formed in a memory cell array portion of the semiconductor substrate;
A second MIS transistor formed in a peripheral circuit portion of the semiconductor substrate;
A first interlayer insulating film covering the first MIS transistor and the first MIS transistor;
A first polysilicon plug penetrating the first interlayer insulating film and reaching one source / drain of the first MIS transistor;
A bit line connected to the first polycrystalline silicon plug;
A conductive plug that penetrates through the first interlayer insulating film and reaches the second MIS transistor; and the conductive plug includes a metal part formed of metal.
Wiring connected to the conductive plug,
A second interlayer insulating film covering the first interlayer insulating film, the bit line, and the wiring;
A second polysilicon plug penetrating the first interlayer insulating film and the second interlayer insulating film and reaching another source / drain of the first MIS transistor;
A semiconductor memory device comprising: a capacitor connected to the second polycrystalline silicon plug for holding data. The semiconductor device according to claim 5,
The second polycrystalline silicon plug has a concave portion on an upper part thereof,
The semiconductor memory device, wherein one electrode of the capacitive element is joined to the second polycrystalline silicon plug at the concave portion.

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