KR100338952B1 - Address generating circuit for zig-zag scanning - Google Patents

Abstract

The present invention relates to an address generator for zigzag scanning. In the prior art, when a variable size of a block in a memory to be accessed is used such as 4, 8, 16, etc., the address generation circuit lacks compatibility and thus, Since an address generating circuit for generating another address is required, there is a problem that the delay time and the circuit size increase rapidly as the size of the overall design block increases. Accordingly, the present invention has been devised to solve the above-mentioned problems. When the size of the image block in the memory to be accessed is variably used, the design variable to the maximum size to be implemented is changed according to the needs of the user. By generating a suitable address in one address generating circuit according to the size of the image block, there is an effect of preventing an increase in delay time and circuit area generated by minimizing the number of address generating circuits regardless of the size of the image block. have.

Description

Address generator for zigzag scanning {ADDRESS GENERATING CIRCUIT FOR ZIG-ZAG SCANNING}

The present invention relates to an address generator for zigzag scanning, and more particularly, to be suitable for performing image processing requiring data access in a specific order including operations such as a variable length coder / decoder. An address generator for zigzag scanning.

1 is a block diagram showing the configuration of a conventional address generator, which is initialized by a reset signal as shown in the figure, and then counts and outputs a system clock counting counter 10; And an address conversion unit 20 which receives the output signal ADDR of the NB counter 10 and converts it into an address signal ADDR of a desired form, and attaches an operation process according to the related art. This will be described in detail with reference to FIG. 2.

First, in the case of a variable length coder / decoder used for image processing, data processing is divided into N × N block forms as shown in FIG. 2, and an order of generating an address according to last scanning and an address according to zigzag scanning is shown. First, the last scanning method generates the addresses in the same order as the structure of the address conversion unit and reads data, that is, 0, 1, 2, 3, 4, 5,... The data is sequentially processed by increasing the address of the data in the order of 61, 62, and 63.

However, zigzag scanning differs from 0, 1, 8, 16, 9, 2,... The data will be read and processed in the order of 55, 62, and 63.

Therefore, when the general enbit counter 10 outputs the last scan address ADDR, the address converter 20 receiving the input converts the address suitable for the zigzag scan method into the final output address ADDR. It was.

For example, when the address conversion unit 20 is a ROM, the address conversion unit 20 stores a final address corresponding to the address ADDR output from the enbit counter 10 in the form of a table. The address matching the address ADDR output from the N-bit counter 10 is output as the final address ADDR.

As described above, when the size of a block in the memory to be accessed is variablely used such as 4, 8, 16, etc., there is a lack of compatibility of the address generator circuit and an address generator circuit for generating different addresses for each is required. As a result, the delay time and the size of the circuit increase rapidly as the size of the overall design block increases.

Accordingly, the present invention was devised to solve the above-described problems, and implements image processing by implementing a circuit of the maximum size to be implemented and variably designating the size of the image block as necessary. It is an object of the present invention to provide an address generator for zigzag scanning suitable for the following.

1 is a block diagram showing the configuration of a conventional address generator.

FIG. 2 is a pattern diagram illustrating a data processing sequence according to the zigzag scan method in FIG. 1. FIG.

3 is a block diagram showing the configuration of an address generator for zigzag scanning of the present invention;

4 is a block diagram showing the configuration of the n-bit self increment counter in FIG.

5 is a circuit diagram showing the configuration of a state controller in FIG.

*** Description of the symbols for the main parts of the drawings ***

100: Enbit self increase / decrease counter 101: Maximum minimum detector

102: flip flip flops 103, 130, 140: Enbit increase and decrease counter

110: n-bit decrement counter 120: state controller

OR1: logical sum gate I1 to I4: inverter

NAND1, NAND2: Integer gate AND1-AND3: Logic gate

The configuration of the present invention for achieving the above object comprises: an Enbit self-decrease counter for outputting a self-decrease output signal which is reset by a reset signal and counts down a diagonal length by a boundary signal; The threshold signal accepts the self-decrease output signal of the N-bit self-deceleration counter as an initial value and decreases it by 1 for every system clock to determine whether its value is '1' or '0'. An n-bit decrement counter for driving the n-bit self-deceleration counter and loading a new initial value; An upper n-bit increase / decrease counter which is reset by a reset signal and increases and decreases an upper address by a first increase and decrease signal input by a system clock; A lower n-bit increase / decrease counter which is reset by a reset signal and increases and decreases a lower address by a second increase and decrease signal input by a system clock; And a state controller that receives the output signals of the n-bit self-decrease counter and the n-bit decrement counter and controls the up-down operation of the upper and lower enbit increase / decrease counters by the final address signals of the upper and lower enbit increase / decrease counters. It is characterized by.

Hereinafter, with reference to the accompanying drawings, the operation and effect of an embodiment of the present invention will be described in detail.

FIG. 3 is a block diagram showing the configuration of an address generator for zigzag scanning according to the present invention. As shown in FIG. 3, an enbit itself is reset by a reset signal RESET and counts a diagonal length by a boundary signal B. As shown in FIG. Increase and decrease counter 100; The threshold signal B receives the output signal LSB of the n-bit self-deceleration counter 100 as an initial value and decreases' 1 'for every system clock so that its value is' 1' or ' An n-bit decrement counter 110 for driving the n-bit self-increment counter 100 and loading a new initial value when it is determined to be '0'; An n-bit increase / decrease counter 130 which is reset by the reset signal RESET and increases or decreases the upper address High_Addr by the up or down signal UP DN inputted by the system clock SYSTEM CLOCK; An n-bit increase / decrease counter 140 which is reset by the reset signal RESET and increases or decreases the lower address Low_Addr by the up or down signal UP DN inputted by the system clock SYSTEM CLOCK; The output signal LSB (ONE) of the n-bit self-decrease counter 100 and the n-bit decrement counter 110 is received and the final address signal Qmax of the n-bit increase / decrease counters 130 and 140 is used. The state controller 120 controls the up-down operation of the n-bit increase and decrease counters 130 and 140.

In addition, the N-bit self-deceleration counter 100 receives an output signal CNT as shown in FIG. 4 and outputs a maximum value of '1' and a minimum value of '0' for all bits of the output signal CNT. A maximum minimum detection unit 101 for detecting; A logic sum gate (OR1) for performing a logic sum operation on the minimum detection signal (ZERO) and the reset signal (RESET) of the maximum minimum detection unit (101) and outputting the logical sum gate (OR1); The maximum detection signal ONE of the maximum minimum detection unit 101 and the output signal of the OR gate OR1 are respectively input to the S stage S and the al stage R to the output stage Q and the inverted output stage QB. An RS flip-flop 102 for outputting; The output signal CNT is reset by the output signal Q (QB) of the RS flip-flop 102 in synchronization with the clock CLK of the clock terminal CK by being reset by the reset signal RESET. It consists of the n-bit increase / decrease counter 103 which increases and decreases and outputs.

As shown in FIG. 5, the state controller 120 outputs an output signal LSB (ONE) of the enbit self-decrement counter 100, the enbit decrement counter 110, and the enbit decrement counter 130, respectively. Inverters (I1) (I2) (I3) respectively receiving and inverting (Ymax); A negative gate NAND1 that receives and outputs the output signal ONE of the n-bit reduction counter 110, the output signal Xmax of the increase / decrease counter 140, and the output signal of the inverter I3; A negative gate NAND2 that receives an output signal of the inverters I1 and I3 and performs a multiplication; An AND gate AND1 that receives the output signal of the inverters I1 and I2 and performs an AND operation; An AND gate AND2 for receiving the output signal LSB of the N-bit self-deceleration counter 100 and the output signal of the inverter I2 and performing an AND operation; An AND gate AND3 for performing an AND operation on the output signals of the AND gates NAND1 and NAND2; An inverter I4 for inverting the output signal of the AND gate AND3 will be described in detail.

The case of zigzag scanning will be described by way of example when the image data block in the form of an N × N block is N = 4 as shown in Table 1 below.

First, the n-bit increase / decrease counters 130 and 140 and the n-bit self-decrease counter 100 are reset by the reset signal RESET to initialize the output signals High_Addr (Low_Addr) LSB, respectively.

At this time, the n-bit increase / decrease counter 103 in the n-bit self-deceleration counter 100 is initialized to '1' by the reset signal RESET, and the output signal Q (QB) of the RS flip-flop 102 is reset. ) Is set to disable and enable, respectively, so that the n-bit increase / decrease counter 103 is incremented by '1' by the output signal B of the n-bit decrease counter 110 input to the clock terminal CK. .

When the output of the n-bit increase / decrease counter 103 becomes 'N', that is, when all bits of the output signal CNT become '1', the maximum minimum detector 101 detects the maximum detection signal ONE. Enable the flip-flop (102), and accordingly, the output signal (Q) (QB) of the flip-flop (102) is set to enable and disable, respectively, so that the N-Bit counter Operate 103 in the reduced mode.

In addition, the maximum minimum detector 101 which receives the output signal CNT of the n-bit increase / decrease counter 103 detects the minimum value of all bits of the output signal CNT as '0' and detects the minimum detection signal ZERO. The N-bit increase / decrease counter 103 is operated in the incremental mode by outputting the logic sum gate to the OR1 and resetting the RS flip-flop 102.

Accordingly, the n-bit self-up and down counter 100 is an auto-up and down counter item which is a third waveform in order to count the diagonal length of the image block, starting from the value of '1' and maintaining the value of 'M' for the 'M' clock. After that, it increments by 1 and keeps the value of 'M' for 'M' clock after M = N, and then decreases by 1 and then stops at M = 1, then goes back to the beginning of the next block. Repeat the operation.

In addition, the N-bit decrement counter 110 receiving the output signal of the N-bit self-deceleration counter 100 is responsible for maintaining the value of the N-bit self-deceleration counter 100 during the 'M' clock. Accepts the value of the current Enbit self-deceleration counter 100 as the initial value by the signal RD, and decreases the value of '1' every system clock (SYSTEM CLOCK) so that its value is '1' and '0'. Activate.

That is, the n-bit decrement counter 110 drives the n-bit self-increment counter 100 by the boundary signal B generated when its value is '0' and loads a new initial value.

Accordingly, the state controller 120 which receives the output signal LSB (ONE) of the n-bit self-deceleration counter 100 and the n-bit decrement counter 110 has an order of generating addresses 0, 1, 4, 8, Since 5,2,3,6,9,12,13,10,7,11,14,15, the n-bit increase and decrease counters 130 and 140 control to operate in the order of 'NUUDDNUUUNDDUUNN' and 'UDNUUUDDDUUUNDUN', respectively.

Here, N is a state in which there is no change in the address (NO CHANGE), U is a state in which the address increases (UP), and D is a state in which the address decreases (DOWN).

Accordingly, the state controller 120 determines whether the current scan direction moves from the bottom left to the top right or from the top right to the bottom left through the output signal LSB, and the last state in the diagonal direction is determined by the output signal ONE. Determine if it is a cell

In this case, when the output signal LSB has a low potential, the state controller 120 which receives the output signal LSB outputs the up signal XU and the down signal XD at high potential and low potential, respectively, to output the enbit increase / decrease counter 140. The lower address Low_Addr is increased, and the up signal YU and the down signal YD are output at low potential and high potential, respectively, and the upper address High_Addr is decreased through the n-bit increase / decrease counter 130.

Thus, the current scan direction moves from bottom left to top right.

In this case, since the increase occurs only in one direction in the last cell in the diagonal direction, the state controller 120 causes the n-bit increase / decrease counters 130 and 140 by the output signal ONE of the n-bit decrease counter 110. Only one counter controls to increment the address.

Here, since the output signal ONE (LSB) is a high potential and a magnetization potential, respectively, the state controller 120 increments only an upper address High_Addr through the n-bit increment counter 130.

In addition, when the output signal LSB has a high potential, the state controller 120 which receives the output signal LSB outputs the up signal XU and the down signal XD at low potential and high potential, respectively. The lower address Low_Addr is decreased, and the up signal YU and the down signal YD are output at high potential and low potential, respectively, and the upper address High_Addr is increased through the n-bit increase / decrease counter 130.

Thus, the current scan direction moves from the upper right to the lower left.

In this case, when the output signal ONE of the n-bit decrement counter 110 is applied at high potential in order to increase only in one direction in the last cell in the diagonal direction, the state controller 120 performs the n-bit increase / decrease counter 130. Increase only the upper address (High_Addr).

When the final address signal Qmax output from the n-bit increase / decrease counters 130 and 140 indicating the end of the high address High_Addr and the low address Low_Addr is simultaneously input at high potential, the state controller 120 Determines that the last address has been output.

As described in detail above, the present invention is designed to the maximum size to be implemented, the size of the image block by generating a suitable address in one address generating circuit according to the size of the image block which is variable according to the needs of the user Regardless, the number of address generation circuits can be minimized, thereby preventing an increase in delay time and circuit area.

Claims (3)

An n-bit self-decrease counter for resetting by a reset signal and outputting a self-decreasing output signal in which the length of the diagonal direction is counted down by a boundary signal; When the self-deceleration output signal of the N-bit self-deceleration counter is received as an initial value by a boundary signal, it decreases by '1' every system clock to determine whether its value is '1' or '0'. An n-bit decrement counter for driving the n-bit self-deceleration counter and loading a new initial value; An upper n-bit increase and decrease counter for increasing and decreasing an upper address by a first increment and decrease signal inputted by a system clock and reset by a reset signal; A lower n-bit increase and decrease counter which is reset by the reset signal and increases and decreases the lower address by the second increase and decrease signals input by the system clock; And a state controller that receives the output signals of the n-bit self-decrease counter and the n-bit decrement counter and controls the up-down operation of the upper and lower enbit increase / decrease counters by the final address signals of the upper and lower enbit increase / decrease counters. Address generator for zigzag scanning. 2. The apparatus of claim 1, wherein the n-bit self-decrease counter comprises: a maximum minimum detector which receives a self-decrease output signal and detects maximum and minimum values thereof; A logic sum gate for performing an OR operation on the minimum detection signal and the reset signal of the maximum minimum detection unit and outputting the logic sum; An RS flip-flop that operates an flip-flop by a maximum detection signal of the maximum minimum detection part and an output signal of a logic sum gate input to an S-end and an al-end; And an n-bit increase / decrease counter which is reset by the reset signal and up-counts the output signal by the output signal of the flip-flop in synchronism with the clock of the clock stage, and outputs the self-increase / decrease output signal. Address generator for zigzag scanning. 2. The apparatus of claim 1, wherein the state controller comprises: first, second, and third inverters which respectively receive and invert output signals of an enbit self-decrement counter, an enbit decrement counter, and an upper enbit decrement counter; A first negative gate that receives an output signal of the third inverter and an output signal of the n-bit decrement counter and the lower n-bit increase / decrease counter; A second negative gate that receives an output signal of the first and third inverters and performs a multiplication; A first AND gate receiving the output signal of the first and second inverters and performing an AND operation to output the second reduced signal; A second AND gate that receives the output signal of the second inverter and the output signal of the N-bit self-incrementation counter, performs an AND operation on the output signal, and outputs the first decrease signal; A third AND gate for performing an AND operation on the output signals of the first and second odd gates and outputting the second AND signal; And a fourth inverter configured to invert the output signal of the third AND gate and output the inverted signal as a first incremental signal.