KR100335270B1 - High voltage generator of semiconductor memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high voltage generator of a semiconductor memory device, and more particularly, to a high voltage generator of a semiconductor memory device having a pumping efficiency of a high voltage pumping circuit having a circuit for determining an output cycle of a pump oscillator. And a periodic expansion means for doubling the output period of the pump oscillator between the input of the high voltage pumping circuit and the pump to increase the pumping efficiency by stably producing the output pulse of the pump oscillator.

Description

High voltage generator of semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high voltage generator of a semiconductor memory device, and more particularly, to a high voltage generator of a semiconductor memory device having a circuit for extending an output period of a pump oscillator to increase the pumping efficiency of a high voltage pumping circuit.

1 is a conventional pump oscillator and a high voltage pumping circuit. FIG. 2 illustrates waveforms output from the pump oscillator of FIG. 1.

As shown in FIG. 2, the output waveform from the pump oscillator of FIG. 1 has the same pulse period, but the width of the high level and the width of the low level are different within the same period.

Hereinafter, the operation and problems occurring when the waveform enters the input of the pumping circuit of FIG. 1 will be described.

First, when the output high of the pump oscillator is input, as shown in FIG. 1, the potential of the node A1 rises and the potential of the node B1 falls so that the PMOS transistor P1 is turned on.

Therefore, the raised potential of the node value A1 performs the pumping operation through the PMOS transistor P1 to generate the Vpp voltage.

Similarly, when the output low of the pump oscillator is input, the potential on the node A1 drops and the potential on the node B1 rises to turn on the PMOS transistor P2.

Therefore, the raised potential of the B1 node value performs the pumping operation through the PMOS transistor P2 to generate the Vpp voltage.

In other words, when the output of the pump oscillator has a high level and a low level, each of the high voltage pumping circuits is pumped.

Therefore, the pulse waveform output from the pump oscillator should have the same pulse width at the high level and the low level, but the pumping efficiency of Vpp is increased by performing the stable pumping operation.

However, as shown in FIG. 2, the output of the pump oscillator differs from the high level and the low level within the same period due to process variations. Thus, in the conventional high voltage pumping circuit, the Vpp pumping efficiency is deteriorated. There was a problem.

The present invention has been devised to solve the above-mentioned problems, and the pump oscillator output is increased by making the width of the high level and the low level constant through the periodic expansion circuit.

1 is a conventional high voltage generating pump circuit diagram.

2 is an output waveform diagram of FIG.

3 is a periodic expansion circuit proposed as an embodiment of the present invention.

4 is an output waveform diagram of an output of a conventional oscillator and a periodic expansion circuit proposed in the present invention.

<Explanation of symbols for main parts of drawing>

1: first inverting portion 2: second inverting portion

3: first latch portion 4: second latch portion

osil: Pump oscillator output signal n-osil: Periodic expansion output signal

sttz: Periodic expansion initialization signal

The high voltage generator of the semiconductor memory device of the present invention for achieving the above object is provided with a pump oscillator for outputting a pulse signal for performing the pumping operation, and an output terminal of the pump oscillator, the pulse signal applied from the pump oscillator is first In the case of the level, the output waveform is maintained as it is, and if the pulse signal is the second level, the output waveform is shifted, and according to the output period applied from the period expansion means and the period expansion means for doubling the output period of the pump oscillator. And a high voltage pumping circuit which operates to generate a high voltage.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

3 is a periodic expansion circuit proposed as an embodiment of the present invention.

FIG. 4B is a waveform illustrating a result of constantly adjusting the pulse width of the high level and the pulp width of the low level through the circuit of FIG. 3.

First, referring to the configuration of the periodic expansion circuit shown in FIG. 3, the first PMOS transistor MP1 and the gate connected to the power supply voltage terminal Vcc and to which the periodic extension output signal n-osil is applied to the gate are described. A pump oscillator output signal osil is applied and a sixth inverter is connected to a gate and a second PMOS transistor MP2 connected between the drain terminal of the first PMOS transistor MP1 and the first node N1. IV6) The periodic expansion output signal n-osil is applied to the first NMOS transistor MN1 and the gate to which the output signal is applied and the first node N1 and the drain terminal are connected. The first inverting portion 1 constituted by the second NMOS transistor MN2 connected between the source transistor MN1 source terminal and the ground voltage terminal Vss, and the potential of the first node N1 are inverted. The second inverter IV2 and the second node N2 outputted to the second node N2 The first latch unit 3 including the third inverter IV3 outputted to the first node N1 by inverting the above and the output of the sixth inverter IV6 are applied to the gate and the power voltage terminal Vcc is applied. ) And a third PMOS transistor MP3 connected between one terminal of the third inverter IV3 and the pump oscillator output signal osil is applied to a gate, and the other terminal and the ground voltage of the third inverter IV3 are applied. A third NMOS transistor MN3 connected between the terminals Vss and a fourth PMOS transistor having a gate applied to the second node N2 potential and a source terminal connected to the power supply voltage terminal Vcc. An output of the sixth inverter IV6 to the gate MP4 and a gate, and a sixth PMOS transistor MP6 connected between the drain terminal of the fourth PMOS transistor MP4 and the third node N3; The pump oscillator output signal (osil) is applied to a gate and is applied to the third node (N3). A potential of the second node N2 is applied to a fifth NMOS transistor MN5 and a gate to which an in terminal is connected, and between a source terminal of the fifth NMOS transistor MN5 and a ground voltage terminal Vss. A second inversion unit 2 composed of a sixth NMOS transistor MN6 to be connected, and a period expansion initialization signal sttz connected to a gate, which is connected between the power supply voltage terminal Vcc and the third node N3. Is the fifth PMOS transistor MP5 inverted and applied by the first inverter IV1 and the fourth inverter IV4 inverting the potential of the third node N3 and outputting the inverted voltage to the fourth node N4. ) And a second latch portion 4 including a fifth inverter IV5 for inverting the potential of the fourth node N4 and outputting the potential to the third node N3, and a gate oscillator output signal ( a seventh PMOS transistor (osil) is applied and is connected between the power supply voltage terminal (Vcc) and one terminal of the fifth inverter (IV5). MP7) and a seventh NMOS transistor having a sixth inverter IV6 output applied with a gate inverted and outputting the pump oscillator output signal osil, and a drain terminal connected to the other terminal of the fifth inverter IV5. A MN7 and a first inverter IV1 output for inverting and outputting the period extension initialization signal sttz to a gate are applied, and between a source terminal of the seventh NMOS transistor MN7 and a ground voltage terminal Vss. And an eighth NMOS transistor MN8 connected to and a sixth inverter IV6 inverting and outputting the pump oscillator output signal osil.

The periodic extension output signal n-osil is output from the third node N3 and applied to the Vpp pumping circuit.

First, the period extension initialization signal sttz is initially high and then continues to be low.

Therefore, when the period extension initialization signal sttz is initially high, the fifth PMOS transistor MP5 is turned on so that the period extension output signal n-osil becomes high so that the second latch portion 4 becomes high. In this case, since the pump oscillator output signal osil is high level, the first latch unit 3 latches a low level.

Thereafter, since the period extension initialization signal sttz is kept low, the fifth PMOS transistor MP5 is continuously turned off.

When the pump oscillator output signal osil becomes low, the first and second NMOS transistors MN1 and MN2 of the first inverting unit 1 are turned on to become low level at the first node N1.

Thus, the first latch portion 3 still latches the previous low level.

The second inverting unit 2 maintains a high-impedance state at this time, and thus the second latching unit 4 maintains a high level of previous data, so that the periodic expansion output signal n-osil becomes a pump oscillator output signal ( osil) still remains high even if it transitions from high level to low level.

Thereafter, when the pump oscillator output signal osil transitions from the low level to the high level again, the first inverting unit 1 turns on the first and second NMOS transistors MN1 and MN2 to turn on the first node N1. ) Becomes low level and still latches low level.

In the second latch unit 4, since the second node N2 is high and the pump oscillator output signal osil is high, the fifth and sixth NMOS transistors MN5 and MN6 are turned on to turn on the third node ( N3) goes low.

Thus, the second latch portion 4 now latches the low level and eventually the periodic extension output signal n-osil drops from the high level to the low level.

Subsequently, when the pump oscillator output signal osil falls low, the first inverting unit 1 turns on the first and second PMOS transistors MP1 and MP2 so that the first node N1 becomes a high level. The first latch portion 3 now latches high.

On the other hand, the second inverting unit 2 is in a high-impedance state because the second node N2 is low, and thus the second latching unit 4 still latches the previous low level.

As a result, the periodic extension output signal n-osil outputs low.

As described above, when the pump oscillator output signal osil is low, the value of the periodic extension output signal n-osil is latched by the first latch unit 3 and the periodic extension output signal n-osil value. Keeps latching in the second latch portion 4.

After that, when the pump oscillator output signal osil changes to high, the value latched in the first latch unit 3 is inverted and output as the period extension output signal n-osil.

When the pump oscillator output signal (osil) is turned low again, the periodic expansion output signal (n-osil) is output with the previous periodic expansion output signal (n-osil) value latched to the second latch unit (4) and the value thereof. The first latch portion 3 is continuously latched.

As the pump oscillator output signal (osil) repeats low and high, the periodic expansion output signal (n-osil) maintains its previous value when the value is low, and only extends when the pump oscillator output signal (osil) changes to high. Since the output signal (n-osil) outputs the inverted value of the previous value, although the width of the high level and the width of the low level are different from each other within one period, the input waveform has the same period. The widths of the high and low levels are equal.

As described above, the present invention has an effect of increasing the pumping efficiency by making the output pulse of the pump oscillator used in the Vpp pumping circuit stable.

Preferred embodiments of the present invention are for the purpose of illustration and various modifications, changes, substitutions and additions are possible to those skilled in the art through the spirit and scope of the present invention disclosed in the appended claims.

Claims (4)

A pump oscillator for outputting a pulse signal for performing a pumping operation; It is provided at the output terminal of the pump oscillator, the output waveform is maintained as it is when the pulse signal applied from the pump oscillator is the first level, the output waveform transitions when the pulse signal is the second level, the output of the pump oscillator Period expansion means for doubling the period; And And a high voltage pumping circuit operating according to an output period applied from said period expansion means to generate a high voltage. The method of claim 1, The periodic expansion means maintains an output waveform when the pulse signal applied from the pump oscillator is at a low level, and the output waveform transitions only when the pulse signal rises to a high level, so that the high and low levels of the output waveform are increased. A high voltage generator of a semiconductor memory device, characterized by generating the same pulse width. The method according to claim 1 or 2, The period extending means includes first inverting means which is controlled by an input waveform and an output waveform; First latch means connected to an output terminal of the first inverting means and latching a potential level of the output waveform when the input waveform is at a low level; Second inverting means connected to an output terminal of the first latching means and outputting an inverted output only when the input waveform is at a high level; And And a second latch means for latching an output potential of the second inverting means. The method of claim 3, wherein The first and second inverting means is a high voltage generator of the semiconductor memory device, characterized in that provided using a MOS transistor.