KR100334964B1 - Method for forming analog capacitor of MML device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an analog capacitor of a composite semiconductor device. In particular, the method includes forming a gate electrode over an active region of a semiconductor substrate corresponding to a memory cell array, and at the same time a lower portion of the capacitor in a field oxide layer corresponding to a logic circuit. Forming an electrode, forming a TEOS film to be used as a dielectric of the capacitor while preventing ions of the BPSG interlayer insulating film to be formed on the front surface of the substrate, and then forming an etch stop film of the nitride material on the TEOS film, and the lower portion of the logic circuit portion After removing all of the etch stop layer except the upper part of the electrode, the interlayer insulating film is formed, and the interlayer insulating film and the etch stop film are selectively etched to open the contact and the source / drain region of the memory cell array unit in the opening and the upper surface of the insulator thin film. Forming holes at the same time, the upper electrode in the opening At the same time, a bit line contacting the source / drain is formed through the contact hole. Accordingly, the present invention can simultaneously perform the process of manufacturing a contact hole to secure the region of the upper electrode and the bit line without damaging the characteristics of the insulator thin film of the capacitor by an etch stop film having a different etching selectivity from the BPSG interlayer insulating film. It simplifies the mask process.

Description

Method for manufacturing analog capacitor of composite semiconductor device {Method for forming analog capacitor of MML device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a composite semiconductor device in which a memory cell array and a logic circuit are integrated into one chip. In particular, the present invention relates to manufacturing a PIP (Poly Insulator Poly) type analog capacitor during a gate electrode and a bit line process of a memory cell. The present invention relates to an analog capacitor manufacturing method of a composite semiconductor device capable of shortening the process.

In general, a semiconductor device requires a logic circuit such as an analog to digital converter (ADC) or a digital to analog converter (DAC) to convert an analog signal input to a logic circuit into a digital signal. These logic circuits usually use analog capacitors of polysilicon-insulator-polysilicon (PIP) structure.

Recently, multimedia functions have been greatly improved due to the emergence of a merged memory logic device in which a memory cell array unit and a logic circuit unit are integrated into one chip, and thus, higher integration and higher speed of semiconductor devices have been achieved. .

In the composite semiconductor device, the ADC to the DCA circuit is also indispensably used, and therefore, an analog capacitor is included in the logic circuit.

1A to 1G are cross-sectional views illustrating a manufacturing process for forming an analog capacitor of a conventional composite semiconductor device. Referring to this, the prior art is as follows.

First, as shown in FIG. 1A, a field oxide film 12 is formed on the silicon substrate 10 as an element isolation region for distinguishing an active region and an isolation region between elements. Subsequently, after the gate oxide layer and the doped polysilicon are stacked on the substrate 10, the gate electrode 14a is placed in the active region of the substrate 10 of the memory cell array unit 200 by a photolithography and etching process using a gate mask. While forming, the lower electrode 14b of the analog capacitor is formed in the field oxide film 12 of the logic circuit unit 100.

Then, sidewall spacers 16 made of an insulating material are formed on the sidewalls of the gate electrode 14a and the lower electrode 14b, and conductive impurities are formed in the active region of the memory cell array with the gate electrode 14a therebetween. Ion implanted source / drain regions 18 are formed.

Subsequently, as shown in FIG. 1B, an insulator 20 is used on top of the resultant to be used as a dielectric of the analog capacitor. Here, the insulator 20 uses TEOS (Tetra-Ethyl-Ortho-Silicate) to prevent the boron dopant of BPSG (Boro Phospho Silicate Glass) from penetrating into the lower memory cell as an interlayer insulating film to be formed later. do.

Next, as shown in FIGS. 1C and 1D, the doped polysilicon 22 is deposited on the insulator 20, and then the stacked doped polysilicon 22 is patterned by performing a photo and etching process. The upper electrode 22 'is formed.

1E and 1F, after the BPSG is deposited on the entire surface of the substrate to form the interlayer dielectric layer 24, the interlayer dielectric layer 24 is selectively etched before the bit line process of the cell. A contact hole 26 is formed in which the source / drain 18 of the cell array is opened.

Next, as illustrated in FIG. 1G, doped polysilicon is embedded in the contact hole 26 to form a bit line 28.

As described above, the conventional method of manufacturing a composite semiconductor device uses a doped polysilicon material as a bit line of a memory cell, thus eliminating the need for an additional polysilicon fabrication process. I had to keep it.

Accordingly, in the conventional technology, the cell gate and the lower electrode are formed by the first polysilicon process, the second polysilicon process is performed to form the upper electrode, and then the polysilicon process is performed again to perform the bit line process of the memory cell. There was a problem that the manufacturing process is somewhat complicated because it proceeds.

An object of the present invention is to solve the above problems of the prior art by adding an etch stop film having a different etch selectivity with oxide between the interlayer insulating film and the lower structure without compromising the characteristics of the insulator thin film of the capacitor afterwards The present invention provides a method for manufacturing an analog capacitor of a composite semiconductor device, which can simultaneously perform a line manufacturing process, thereby simplifying the manufacturing process.

1A to 1G are cross-sectional views illustrating a manufacturing process for forming an analog capacitor of a conventional composite semiconductor device;

2A to 2G are cross-sectional views illustrating a manufacturing process for forming an analog capacitor of a composite semiconductor device according to the present invention.

* Description of the symbols for the main parts of the drawings *

10 silicon substrate 12 field oxide film

14a: gate electrode 14b: lower electrode

16: sidewall spacers 18: source / drain regions

20: insulator thin film 22 ', 44a: upper electrode

24: BPSG interlayer insulating film 26, 42b: bit line contact hole

28, 44b: bit line 40: etch stop film

42a: opening for upper electrode

In order to achieve the above object, the present invention provides a method of manufacturing an analog capacitor of a composite semiconductor device in which a memory cell array unit and a logic circuit unit are integrated into one chip. Forming a lower electrode of the capacitor in the field oxide film of the substrate corresponding to the logic circuit portion, forming a source / drain region in the active region corresponding to the memory cell array portion, and ions of the interlayer insulating film to be subsequently formed on the entire surface of the substrate. Forming an insulator thin film to be used as a dielectric of the capacitor while preventing penetration into the substrate, laminating an etch stop film on the insulator thin film, and removing the etch stop film except the upper portion of the lower electrode of the logic circuit part. And a lower structure on the front of the substrate and an upper structure to be formed later. Forming an interlayer insulating film for inter-insulating, and simultaneously forming an opening in the contact hole where the source / drain region of the memory cell array part is opened and the upper portion of the insulating thin film of the logic circuit part by selectively etching the interlayer insulating film and the etch stop film; Forming an upper electrode in the opening and forming a wiring contacting the source / drain through the contact hole.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings of this embodiment, the same reference numerals are used for the same parts as the prior art.

2A to 2G are cross-sectional views illustrating a manufacturing process for forming an analog capacitor of a composite semiconductor device according to the present invention. Referring to this, the manufacturing process of the present invention is as follows.

First, referring to FIG. 2A, after the field oxide film 12 is formed on the silicon substrate 10 as in the prior art, the gate electrode 14a of the memory cell and the lower electrode 14b of the analog capacitor are formed.

Then, the sidewall spacers 16 are formed on the sidewalls of the gate electrode 14a and the lower electrode 14b, and the source in which the conductive impurities are ion-implanted with the gate electrode 14a interposed in the active region of the memory cell array. / Drain region 18 is formed.

Subsequently, as shown in FIG. 2B, TEOS material is deposited on the resultant to serve to prevent the boron dopant of the BPSG of the interlayer dielectric layer to be formed later, from being penetrated into the memory cell. An insulator thin film 20 is formed.

Next, as illustrated in FIG. 2C, a nitride film is deposited on the insulator thin film 20 to form an etch stop film 40. Here, the etch stop layer 40 serves to protect the insulator thin film 20 during the etching process to secure the bit line region and the capacitor upper electrode region.

Subsequently, as shown in FIG. 2D, the etch stop layer is etched by performing a photo and etching process to selectively leave only the etch stop layer 40 ′ on the lower electrode of the logic circuit unit 100.

Subsequently, as shown in FIGS. 2E and 2F, after the BPSG is deposited on the entire surface of the substrate to form the interlayer dielectric layer 24, the upper electrode of the analog capacitor of the logic circuit unit 100 and the memory cell array unit 200 may be formed. The interlayer insulating layer 24 and the etch stop layer 40 are selectively etched by performing a photo process and a dry etching process to define the bit line region. Then, a contact hole 42a through which the source / drain region 18 of the memory cell array unit 100 is opened is formed, and an opening 42b is formed in the upper surface of the insulator thin film 20 of the logic circuit unit 200.

Next, as shown in FIG. 2G, doped polysilicon is buried in the contact hole 42a and the opening 42b to the bit line 44a and the logic circuit unit 100 in the memory cell array unit 200. Upper electrodes 44b are formed, respectively.

Meanwhile, when removing the nitride film, which is the etch stop film 40, only the interlayer insulating film 24 may be etched and removed separately using phosphoric acid, which is an etching solution of the nitride film.

As described above, the present invention can secure a predetermined area where a bit line of a memory cell array and an analog capacitor upper electrode of a logic circuit are to be formed by using a mask pattern of 1, thereby shortening the manufacturing process time and simultaneously manufacturing. Cost reduction and quality stabilization can be achieved.

Claims (2)

A method of manufacturing an analog capacitor of a composite semiconductor device in which a memory cell array portion and a logic circuit portion are formed into one chip, Forming a gate electrode over an active region of the semiconductor substrate corresponding to the memory cell array and simultaneously forming a lower electrode of the capacitor in an isolation region of a substrate corresponding to the logic circuit unit; Forming a source / drain region in an active region corresponding to the memory cell array; Forming an insulator thin film to be used as a dielectric of a capacitor while preventing the ions of the interlayer insulating film to be subsequently formed from penetrating the substrate onto the substrate; Stacking an etch stop layer on the insulator thin film; Removing the etch stop layer on the lower electrode of the logic circuit unit; Forming an interlayer insulating film interlayer insulating the lower structure and the upper structure to be formed later on the substrate; Selectively etching the interlayer insulating layer and the etch stop layer to simultaneously form an opening in a contact hole in which a source / drain region of a memory cell array unit is opened and an upper surface of an insulator thin layer of a logic circuit unit; And And forming a wiring in contact with the source / drain through the contact hole while forming an upper electrode in the opening. The method of claim 1, wherein the etch stop layer is a nitride film.