KR100326814B1 - Method for forming a inter layer dielectric of metal line in semiconductor device - Google Patents
Method for forming a inter layer dielectric of metal line in semiconductor device Download PDFInfo
- Publication number
- KR100326814B1 KR100326814B1 KR1019990066573A KR19990066573A KR100326814B1 KR 100326814 B1 KR100326814 B1 KR 100326814B1 KR 1019990066573 A KR1019990066573 A KR 1019990066573A KR 19990066573 A KR19990066573 A KR 19990066573A KR 100326814 B1 KR100326814 B1 KR 100326814B1
- Authority
- KR
- South Korea
- Prior art keywords
- insulating film
- interlayer insulating
- forming
- semiconductor device
- thin film
- Prior art date
Links
- 239000011229 interlayer Substances 0.000 title claims abstract description 51
- 238000000034 method Methods 0.000 title claims abstract description 42
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 31
- 239000002184 metal Substances 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 239000010408 film Substances 0.000 claims abstract description 69
- 239000010409 thin film Substances 0.000 claims abstract description 26
- 238000009832 plasma treatment Methods 0.000 claims abstract description 7
- 239000007789 gas Substances 0.000 claims description 16
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 7
- 229910052799 carbon Inorganic materials 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000010410 layer Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 239000011261 inert gas Substances 0.000 claims description 2
- 239000002904 solvent Substances 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims 1
- 238000000151 deposition Methods 0.000 claims 1
- 238000002156 mixing Methods 0.000 claims 1
- 238000002161 passivation Methods 0.000 claims 1
- 229910052709 silver Inorganic materials 0.000 claims 1
- 239000004332 silver Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 7
- 150000004767 nitrides Chemical class 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
본 발명은 반도체 소자의 금속 배선간 층간 절연막 형성방법에 관한 것으로, 특히 금속배선이 형성된 구조의 상부에 증착된 하부 층간 절연막의 상부에 제1 층간 절연막으로 SiOxCy 박막을 사용하고, 상기 제1 층간 절연막의 상부에 형성되는 제2 층간 절연막인 캐핑 절연막으로 산화막 혹은 질화막의 유전상수보다 낮은 SiOxFy 박막을 형성함에 의해 2중 저유전율 층간 절연막 구조를 구비하여, 금속배선의 전체 캐패시턴스를 낮추고, 저유전율 박막에서 구비한 낮은 부착력 문제를 CH4혹은 CF4플라즈마를 이용하여 개선할 수 있고, 또한 비아 콘택 식각 후 포토레지스트를 스트립할 경우, SiOxCy 박막 측벽의 어택(attack)에 의한 비아 보잉 문제를 상기 CH4혹은 CF4플라즈마 처리를 통하여 최소화하여 반도체 소자의 제조 공정 수율을 향상시킬 수 있다.The present invention relates to a method for forming an interlayer interlayer insulating film of a semiconductor device, in particular using a SiOxCy thin film as the first interlayer insulating film on top of the lower interlayer insulating film deposited on the structure of the metal wiring formed, the first interlayer insulating film By forming a SiOxFy thin film having a lower dielectric constant than an oxide film or a nitride film as a capping insulating film, which is a second interlayer insulating film formed on the upper part of the structure, the double low dielectric constant interlayer insulating film structure is provided to reduce the overall capacitance of the metal wiring, and thus, in the low dielectric constant thin film. having a low adhesion problem can be improved by using a CH 4 or CF 4 plasma, and the via if the strip after contact etch photoresist, the vias Boeing problems caused by the attack (attack) of SiOxCy thin sidewall CH 4 or Minimization through the CF 4 plasma treatment can improve the manufacturing process yield of the semiconductor device.
Description
본 발명은 반도체 소자의 금속배선간 층간 절연막 형성방법에 관한 것으로, 특히 저유전율 층간 절연막 기술을 고집적 반도체 소자의 제조공정에 도입함에 의해 금속배선의 디자인 룰(design rule)을 감소시켜 반도체 소자의 제조공정 수율 및 신뢰성 향상을 도모할 수 있는 반도체 소자의 금속배선간 층간 절연막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an interlayer insulating film between metal wirings of a semiconductor device, and in particular, by introducing a low dielectric constant interlayer insulating film technology into a manufacturing process of a highly integrated semiconductor device, a design rule of metal wiring is reduced to manufacture a semiconductor device. The present invention relates to a method for forming an interlayer insulating film between metal wirings of a semiconductor device capable of improving process yield and reliability.
종래의 알루미늄을 금속배선으로 사용하는 층간 절연막 형성 기술은 절연막으로 주로 실리콘 산화막을 사용한다. 상기 실리콘 산화막은 유전상수 k 값이 4로서, 선간 캐패시턴스(capacitance)는 거리에 반비례하고 면적에 비례하는데, 종래의 0.16 Tech. 이상 디램 소자의 제조 공정에서 금속 선간 간격이 0.3㎛ 이상이었기 때문에 RC 지연 현상이나 크로스-토킹(cross-talking) 현상 등의 원하지 않는 오동작 현상이 없었다.The conventional interlayer insulation film forming technique using aluminum as a metal wiring mainly uses a silicon oxide film as the insulating film. The silicon oxide film has a dielectric constant k of 4, and the line capacitance is inversely proportional to the distance and proportional to the area. In the manufacturing process of the DRAM device, since the metal line spacing was 0.3 µm or more, there was no unwanted malfunction phenomenon such as the RC delay phenomenon or the cross-talking phenomenon.
그러나 0.1Tech. 이하의 소자에서는 금속선간 간격이 0.3㎛ 이하로 줄어 들기 때문에 금속선간 캐패시턴스가 급격히 증가하고, 이에 따른 상기의 문제점이 심각해져 소자가 제대로 작동하지 않게 된다.0.1Tech. In the following devices, the spacing between metal lines decreases to 0.3 μm or less, and the capacitance between metal lines increases rapidly, and the above problems become serious and the devices do not operate properly.
동일한 금속배선 구조에서 선간/층간 캐패시턴스를 줄이기 위해서는 층간 절연막을 저유전율을 갖는 물질로 대치해야 한다. 저유전율막으로는 카본을 함유하는 산화막, 즉 SiOxCy 박막을 금속배선위에 형성하고 그 위에 비아 식각시 포토레지스트와 선택비를 갖는 캐핑 산화막(capping oxide)을 증착해야 하는데, 상기 SiOxCy 박막과 캐핑 산화막 사이의 접착력이 충분하지 않아 후속 열처리(annealing) 공정 혹은 비아 콘택 형성 공정에서 박막 리프팅(ligting)이나 크랙 등이 발생하게 되어 반도체 소자의 제조 공정 수율을 저하시키게 되는 문제점이 있다.In the same metallization structure, in order to reduce the interline / interlayer capacitance, the interlayer insulating film needs to be replaced with a material having a low dielectric constant. As the low dielectric constant film, an oxide film containing carbon, i.e., a SiOxCy thin film, must be formed on the metal interconnection, and a capping oxide having a selectivity and a photoresist when the via is etched is deposited therebetween. Insufficient adhesive force may cause thin film lifting or cracking in subsequent annealing or via contact formation, thereby lowering the yield of the semiconductor device manufacturing process.
따라서 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로, 본 발명은 반도체 소자의 제조 공정 중 금속배선간 층간 절연막 형성시, 저유전율 층간 절연막을 적용함에 따라 고집적 소자의 제조 공정에서 문제시 되고 있는 RC 지연 및 크로서-토킹 현상을 제거할 수 있고, 아울러 저유전율 층간 절연막과 캐핑 절연막 사이의 플라즈마 처리를 수행함에 따라 후속 공정에서 취약한 부착력(adhesion)으로 발생되는 박막의 리프팅 및 크랙 등의 공정상 문제점을 해결하여 반도체 소자의 제조 공정 수율을 향상시킬 수 있는 반도체 소자의 금속배선 간 층간 절연막 형성 방법을 제공하는 것을 목적으로 한다.Accordingly, the present invention is to solve the above-described problems, the present invention is a problem in the manufacturing process of the high-density device by applying a low dielectric constant interlayer insulating film when forming the inter-metal interlayer insulating film during the manufacturing process of the semiconductor device. It is possible to eliminate the RC delay and crack-talking phenomenon, and also to perform the plasma treatment between the low dielectric constant interlayer insulating film and the capping insulating film. It is an object of the present invention to provide a method for forming an interlayer insulating film between metal wirings of a semiconductor device capable of solving the problem and improving the yield of the semiconductor device manufacturing process.
도 1 내지 도 3 은 본 발명의 방법에 따른 금속배선간 층간 절연막 형성 공정 단계를 도시한 단면도1 to 3 are cross-sectional views illustrating the steps of forming an interlayer insulating film between metal lines according to the method of the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
1 : 캐패시터 2 : 하부 층간 절연막1 capacitor 2 lower interlayer insulating film
3 : 금속배선 4 : 제1 층간 절연막3: metallization 4: first interlayer insulating film
5 : 제2 층간 절연막 6 : 콘택 마스크(PR)5: second interlayer insulating film 6: contact mask PR
상기 목적을 달성하기 위한 본 발명의 방법에 따른 반도체 소자의 금속배선간 층간 절연막 형성방법은,Method for forming an interlayer insulating film between metal wirings of a semiconductor device according to the method of the present invention for achieving the above object,
하부 층간 절연막의 상부에 금속배선을 형성한 후, 전체 구조 상부에 제1 층간 절연막으로 SiOxCy 박막을 코팅하는 단계와;Forming a metal wiring on the lower interlayer insulating film, and then coating the SiOxCy thin film with the first interlayer insulating film on the entire structure;
카본을 포함한 기체 플라즈마로 상기 SiOxCy 박막을 표면처리하는 단계와;Surface treating the SiO x C y thin film with a gas plasma containing carbon;
상기 SiOxCy 박막의 상부에 제2 절연막을 형성하되, 캐핑 절연막인 SiOxFy 박막으로 형성하는 단계와;Forming a second insulating film on the SiOxCy thin film and forming a SiOxFy thin film which is a capping insulating film;
상기 각 절연막을 식각하여 비아 콘택을 형성하는 단계와;Etching each of the insulating layers to form a via contact;
카본을 포함한 기체 플라즈마로 노출된 박막의 표면처리를 하는 단계와;Surface treatment of the thin film exposed to a gas plasma including carbon;
콘택 마스크를 제거하는 단계를 포함하는 것을 특징으로 한다.Removing the contact mask.
이하 첨부된 도면을 참조하여 본 발명에 대해 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 3 은 본 발명의 방법에 따른 금속배선 간 층간 절연막 형성 공정을 도시한 단면도이다.1 to 3 are cross-sectional views illustrating a process for forming an interlayer insulating film between metal lines according to the method of the present invention.
먼저, 상기 도 1을 참조하면, 하부 층간 절연막(2)의 상부에 금속배선(3)을 형성한 후, 전체 구조 상부에 제1 층간 절연막(4)으로 SiOxCy 박막을 스핀-온코팅(spin-on coating)하고 솔벤트(solvent)를 제거하기 위한 경화 또는 베이킹(baking)을 실시한다.First, referring to FIG. 1, after the metal wiring 3 is formed on the lower interlayer insulating film 2, the SiOxCy thin film is spin-on-coated with the first interlayer insulating film 4 on the entire structure. on coating) and harden or bake to remove solvent.
이때 스핀-온 코팅시 사용되는 케미칼은 실록산(siloxane) 계열 에스오지(SOG; Spin On Glass)에 메틸(methyl)기가 포함되어 있는 MSQ(Methyl-SilsesQuioxane) 케미칼을 사용한다.In this case, the chemical used for spin-on coating uses MSQ (Methyl-SilsesQuioxane) chemical, which contains a methyl group in siloxane-based spin on glass (SOG).
상기 베이킹(baking) 공정은 150℃, 200℃, 350℃에서 각 1분씩하며, 경화 또는 베이킹은 400∼500℃에서 약 30분∼60분 동안 한다.The baking process is performed at 150 ° C., 200 ° C. and 350 ° C. for 1 minute each, and curing or baking is performed at 400 ° C. to 500 ° C. for about 30 minutes to 60 minutes.
한편, 상기 하부 층간 절연막(4)의 하부구조에는 캐패시터(1)가 형성된다. (도 1 참조)Meanwhile, a capacitor 1 is formed in the lower structure of the lower interlayer insulating film 4. (See Figure 1)
다음, 상기 제1 층간 절연막(4)의 상부에 제2 층간 절연막(5)으로 캐핑 절연막인 SiOxFy 박막을 형성한다. 상기 SiOxFy 박막을 형성하기 위해 웨이퍼를 SiOxFy 박막을 형성하는 PECVD(Plasma Enhanced Chemical Vapor Deposition) 혹은 HDP-CVD 반응실에 넣고, CH4혹은 CF4단일기체나 CH4(혹은 CF4) + 불활성 기체(He, Ar, Ne 등)의 혼합기체를 0∼5,000sccm 사용한다.Next, a SiOxFy thin film, which is a capping insulating film, is formed as a second interlayer insulating film 5 on the first interlayer insulating film 4. To form the SiOxFy thin film, a wafer is placed in a Plasma Enhanced Chemical Vapor Deposition (PECVD) or HDP-CVD reaction chamber that forms a SiOxFy thin film, and a CH 4 or CF 4 single gas or CH 4 (or CF 4 ) + an inert gas ( He, Ar, Ne, etc.) is used a mixed gas of 0 to 5,000 sccm.
반응기체를 제외한 다른 플라즈마 조건으로 RF PECVD 법에서는 반응실 압력은 0.1∼10Torr, 플라즈마 발생 전력은 50∼2000W, 웨이퍼 온도는 상온∼450℃ 로 조절한다. 그리고 플라즈마 처리 단계가 완료되면 SiOxFy 박막을 형성하는 혼합기체를 반응실로 주입하여 플라즈마를 켜서 일정 두께의 캐핑 SiOxFy 박막을 형성한다.Under the plasma conditions other than the reactor, in the RF PECVD method, the reaction chamber pressure is controlled to 0.1 to 10 Torr, the plasma generation power to 50 to 2000 W, and the wafer temperature to room temperature to 450 ° C. When the plasma treatment step is completed, a mixed gas forming the SiOxFy thin film is injected into the reaction chamber to turn on the plasma to form a capping SiOxFy thin film having a predetermined thickness.
이때 상기 SiOxFy 박막 증착용 기체는 SiH4가 0∼500sccm, SiF4가 0∼5,000sccm, N2O 가 0∼5,000sccm을 사용하며, 반응실 압력은 0.1∼10Torr, 플라즈마 발생 전력은 50∼2,000W, 웨이퍼 온도는 상온∼450℃로 조절한다.In this case, the SiOxFy thin film deposition gas uses SiH 4 of 0 to 500 sccm, SiF 4 of 0 to 5,000 sccm, N 2 O of 0 to 5,000 sccm, reaction chamber pressure of 0.1 to 10 Torr, and plasma generation power of 50 to 2,000. W and wafer temperature are adjusted to normal temperature-450 degreeC.
다음, 상기 제2 절연막(5)의 상부에 감광막을 도포한 후 식각하여 비아 콘택 마스크(6)를 형성한다.Next, the via contact mask 6 is formed by applying a photoresist film on the second insulating film 5 and then etching the same.
상기 비아 콘택 마스크(6)을 이용하여 비아 콘택 형성을 위한 식각을 하고, 포토레지스를 스트립하기 전 SiOxCy 측벽 보잉(bowing)을 방지하기 위해 CH4혹은 CF4플라즈마 처리를 진행하여 측벽에 단단한 Si-C 본드 리치(bond rich)막을 형성한다. 혹은 포토레지스트를 스트립하는 과정중 O2기체에 CH4혹은 CF4기체를 소량 혼입하고 반응실 압력을 가급적 낮게 유지하여 측벽은 카본 패시베이션(carbon passivation)되게 하고, 캐핑 절연막 상부 및 비아 콘택 홀의 바닥에 남아 있는 포토레지스를 비등방성 식각으로 제거하여 비아 보잉(via bowing)을 최소화 한다.The via contact mask 6 is etched for via contact formation, and CH 4 or CF 4 plasma treatment is performed to prevent SiOxCy sidewall bowing before stripping the photoresist, thereby forming a hard Si— A C bond rich film is formed. Alternatively, a small amount of CH 4 or CF 4 gas is mixed into the O 2 gas during the stripping of the photoresist, and the reaction chamber pressure is kept as low as possible so that the sidewalls are carbon passivated, and the top of the capping insulating layer and the bottom of the via contact hole are The remaining photoresist is removed by anisotropic etching to minimize via bowing.
한편, 상기에서 산소와 CF4의 가스 혼합비(CF4/O2)는 0.01∼0.1 로 하고, 반응실의 압력은 0.1Torr 이하로 유지되게 한다.On the other hand, the gas mixture ratio (CF 4 / O 2 ) of oxygen and CF 4 in the above to be 0.01 to 0.1, the pressure of the reaction chamber is maintained at 0.1 Torr or less.
이상 상술한 바와 같이, 금속배선이 형성된 구조의 상부에 증착된 하부 층간 절연막의 상부에 제1 층간 절연막으로 SiOxCy 박막을 사용하고, 상기 제1 층간 절연막의 상부에 형성되는 제2 층간 절연막인 캐핑 절연막으로 산화막 혹은 질화막의유전상수보다 낮은 SiOxFy 박막을 형성함에 의해 2중 저유전율 층간 절연막 구조를 구비한 본 발명은 금속배선의 전체 캐패시턴스를 낮출 수 있으며, 저유전율 박막에서 가지고 있는 낮은 부착력 문제를 CH4혹은 CF4플라즈마를 이용하여 개선할 수 있고, 또한 비아 콘택 식각 후 포토레지스트를 스트립할 경우, SiOxCy 박막 측벽의 어택(attack)에 의한 비아 보잉 문제를 상기 CH4혹은 CF4플라즈마 처리를 통하여 최소화하여 반도체 소자의 제조 공정 수율을 향상시킬 수 있다.As described above, the capping insulating film is a second interlayer insulating film formed on the first interlayer insulating film by using a SiOxCy thin film as the first interlayer insulating film on the lower interlayer insulating film deposited on the structure of the metal wiring. a low adhesion problems with the present invention having a low dielectric constant interlayer dielectric film structure of the 2 by forming a low SiOxFy thin film than the dielectric constant of the oxide film or a nitride film can reduce the total capacitance of the metal leads, with the low dielectric constant films CH 4 or can be improved by using a CF 4 plasma, and if the strips and then via contact etching the photoresist, and the via-Boeing problems caused by the attack (attack) of SiOxCy thin wall minimizes via the CH 4 or CF 4 plasma treatment The manufacturing process yield of a semiconductor element can be improved.
Claims (13)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990066573A KR100326814B1 (en) | 1999-12-30 | 1999-12-30 | Method for forming a inter layer dielectric of metal line in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990066573A KR100326814B1 (en) | 1999-12-30 | 1999-12-30 | Method for forming a inter layer dielectric of metal line in semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010059183A KR20010059183A (en) | 2001-07-06 |
| KR100326814B1 true KR100326814B1 (en) | 2002-03-04 |
Family
ID=19633710
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990066573A KR100326814B1 (en) | 1999-12-30 | 1999-12-30 | Method for forming a inter layer dielectric of metal line in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100326814B1 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06302593A (en) * | 1993-04-16 | 1994-10-28 | Oki Electric Ind Co Ltd | Fabrication of semiconductor device |
| JPH0729976A (en) * | 1993-07-13 | 1995-01-31 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JPH1041382A (en) * | 1996-04-29 | 1998-02-13 | Texas Instr Inc <Ti> | Integrated circuit inter-level insulation structure |
| US5759906A (en) * | 1997-04-11 | 1998-06-02 | Industrial Technology Research Institute | Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits |
-
1999
- 1999-12-30 KR KR1019990066573A patent/KR100326814B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06302593A (en) * | 1993-04-16 | 1994-10-28 | Oki Electric Ind Co Ltd | Fabrication of semiconductor device |
| JPH0729976A (en) * | 1993-07-13 | 1995-01-31 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JPH1041382A (en) * | 1996-04-29 | 1998-02-13 | Texas Instr Inc <Ti> | Integrated circuit inter-level insulation structure |
| US5759906A (en) * | 1997-04-11 | 1998-06-02 | Industrial Technology Research Institute | Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010059183A (en) | 2001-07-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100407542B1 (en) | Semiconductor device and production method therefor | |
| US6605863B2 (en) | Low k film application for interlevel dielectric and method of cleaning etched features | |
| KR100358545B1 (en) | Semiconductor device and process for producing the same | |
| US7741224B2 (en) | Plasma treatment and repair processes for reducing sidewall damage in low-k dielectrics | |
| US9607883B2 (en) | Trench formation using rounded hard mask | |
| KR20030030838A (en) | Method of manufacturing semiconductor device having silicon carbide film | |
| CN1065657C (en) | Manufacture of semiconductor device | |
| US7022582B2 (en) | Microelectronic process and structure | |
| KR20020068958A (en) | Method of Manufacturing a Semiconductor Device and the Semiconductor Device | |
| WO1991010261A1 (en) | Semiconductor interconnect structure utilizing a polyimide insulator | |
| JP2003303880A (en) | Wiring structure using insulating film structure between laminated layers and manufacturing method therefor | |
| KR100326814B1 (en) | Method for forming a inter layer dielectric of metal line in semiconductor device | |
| KR20030050951A (en) | Method for forming metal wiring of semiconductor device | |
| JP2004006708A (en) | Method for manufacturing semiconductor device | |
| JP2003133411A (en) | Semiconductor device and its manufacturing method | |
| KR100876532B1 (en) | Manufacturing Method of Semiconductor Device | |
| US20060166491A1 (en) | Dual damascene interconnection having low k layer and cap layer formed in a common PECVD process | |
| KR20010059540A (en) | Method for forming metal line of semiconductor device | |
| JPH1131683A (en) | Manufacture of semiconductor device | |
| JPH05206282A (en) | Manufacturing method of multilayer wiring structure of semiconductor device | |
| KR100866135B1 (en) | Method of manufacturing semiconductor device | |
| KR19990057932A (en) | Semiconductor Device Manufacturing Method for Improving Contact Hole Profile | |
| KR100483202B1 (en) | Method of manufacturing a semiconductor device | |
| KR100585082B1 (en) | Method for forming a contact hole of a semiconductor device | |
| CN111952242A (en) | Dual damascene trench structure and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20110126 Year of fee payment: 10 |
|
| LAPS | Lapse due to unpaid annual fee |