JPH1131683A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, through which an insulating film containing moisture or an organic solvent can be worked with high precision and ease. SOLUTION: A low dielectric SiO2 film 14 as an interlayer insulating film is formed by causing a reaction between Si(CH3 )H3 (monomethylsilane) and H2 O2 by an LP-CVD method (low pressure-chemical vapor deposition). When the low dielectric SiO2 film 14 is selectively etched with a mask of resist 16 for a pattern of via holes, plasma etching is performed with a large amount of moisture contained in the film without performing annealing. At this time, a large amount of H2 O is desorbed in gaseous form, as indicated by arrows 20 from the sidewalls of the low dielectric SiO2 film 14 exposing in the via holes 18 and prevents radicals in plasma from approaching the sidewalls of the low dielectric SiO2 film 14. Accordingly, isotropic etching of the sidewalls of the low dielectric SiO2 film 14 by radicals is inhibited, and bowing of the cross-section of the sidewalls of the low dielectric SiO2 film 14 is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for processing an insulating film used as an interlayer insulating film of a semiconductor device.

[0002]

2. Description of the Related Art In a multilayer metal wiring structure of a semiconductor device, it is necessary to cover the lower wiring layer well and to planarize the surface of the interlayer insulating film serving as a base of the upper wiring layer. A highly fluid insulating film containing water or an organic solvent is used. Further, in order to enable high-speed operation of a semiconductor device, an attempt to use a low dielectric film as an interlayer insulating film between multilayer metal wirings has been continued.

When a low dielectric film containing such water or an organic solvent is used as an interlayer insulating film,
In order to improve the film quality, heat treatment is performed immediately after film formation,
It is customary to work after removing the water or organic solvent in the film.

For example, as a low dielectric film used for an interlayer insulating film, LP (Low Pressure) -CVD (Chemical
Vapor Deposition (chemical vapor deposition)
H ₄ (silane) and H ₂ O ₂ (hydrogen peroxide) at a temperature of 0 ° C.
In HSO (Hydrogen peroxide and
When a Silane based CVD Oxide (Si) film is formed, it is post-annealed at 400 ° C. for 30 minutes (Post Anneal).
ealing) (M. Matuura and
M. Hirayama, “An Advanced Planarizing Interlayer D
ielectric Using SiH ₄ and H ₂ O ₂ Chemistry ", Dry Proc
ess Symposium, 1995, pp. 261-268).

When a fluororesin film is formed by spin coating, baking is performed for 150 to 2 hours after the film formation.
It has also been reported that curing is carried out at 50 ° C for several minutes and at 400 ° C in a nitrogen atmosphere for 30 minutes (Toshiaki Hasegawa, Masanaga Fukasawa, Shingo Kadomura, Junichi Aoyama, "Low dielectric constant using fluororesin film"
Etching characteristics are clear, the challenge is oxygen plasma resistance. "
Monthly Semicondur World 1997.2, pp.82-84).

In the case of processing a low dielectric film, for example, etching or ashing (ashing) after removing moisture and an organic solvent in the film by such a heat treatment after film formation, a conventional interlayer insulating film is used. SiO ₂ film to be used,
For example, P (Pasma) -TEOS (Tetraethoxysilane)
-Generally, the etching method and the ashing method of the P-TEOS film formed by using the CVD method are directly followed.

[0007]

However, in the case of a low dielectric film containing moisture or an organic solvent, even if the moisture or organic solvent in the film is removed by a heat treatment after the film is formed, the quality of the film is improved. As compared with a conventional P-TEOS film used as an interlayer insulating film, the film quality tends to be inferior. Therefore, if the conventional etching method or ashing method for the P-TEOS film or the like is applied as it is, some problems occur. For example, using a conventional P-TEOS film etching method or the like, a low-dielectric film is selectively plasma-etched using a resist of a predetermined pattern as a mask,
When a via hole is opened, there is a problem in that the side wall of the low dielectric film exposed in the via hole is etched by radicals in the plasma, and the cross-sectional shape of the via hole becomes so-called bowing.

When a via hole is opened by etching a low dielectric film and then ashing is performed on the resist used as a mask, the side wall of the low dielectric film exposed in the via hole is removed together with the resist, and the opening is formed by etching. There is also a problem that the shape of the via hole is deformed.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of easily and precisely processing an insulating film containing water or an organic solvent. Aim.

[0010]

The above object is achieved by the following method of manufacturing a semiconductor device according to the present invention. That is, the method for manufacturing a semiconductor device according to claim 1 is a method for manufacturing a semiconductor device, comprising: forming an insulating film containing moisture or an organic solvent on a substrate; and selectively etching the insulating film using a resist having a predetermined pattern as a mask. In a manufacturing method, before performing an annealing process on the insulating film, the insulating film is plasma-etched in a state where the insulating film contains moisture or an organic solvent.

As described above, in the method of manufacturing a semiconductor device according to the first aspect, in a state where the insulating film contains moisture or an organic solvent, selective plasma etching of the insulating film using a resist of a predetermined pattern as a mask. Is performed, moisture or an organic solvent contained in the insulating film is desorbed from the insulating film as a gas with the selective etching of the insulating film by radicals and ions in the plasma. Then, the gaseous moisture or organic solvent released from the insulating film hinders the radicals in the plasma from approaching the insulating film side wall exposed by etching, so that the radicals reach the insulating film side wall. And the isotropic etching of the insulating film by radicals is suppressed.

On the other hand, the ions in the plasma are accelerated by the electrostatic force and fly in a direction substantially perpendicular to the surface of the insulating film and fly. Therefore, the ions desorbed from the insulating film are affected by the gas. Since it is difficult, anisotropic etching of the insulating film by ions proceeds. In this manner, isotropic etching due to radicals is suppressed, and anisotropic etching due to ions becomes mainstream, whereby etching of the insulating film proceeds.
Therefore, an insulating film containing moisture or an organic solvent has a poor film quality as compared with a conventional P-TEOS film or the like used as an interlayer insulating film, and therefore, a low dielectric film whose side walls are easily etched by radicals. Even in the case of (1), occurrence of bowing in which the cross-sectional shape of the side wall exposed by the etching is arcuate is prevented, and high-precision processing in which the cross-sectional shape of the side wall becomes vertical by the anisotropic etching can be easily performed.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, the substrate is heated when the insulating film containing water or the organic solvent is plasma-etched. With such a structure, the amount of desorbed gas when water or an organic solvent contained in the insulating film is desorbed as a gas further increases, so that the insulating film isotropically generated by radicals in plasma. Etching is further suppressed, and the processing accuracy of the insulating film is further improved.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, the insulating film containing water or an organic solvent is plasma-etched using a resist having a predetermined pattern as a mask. rear,
Before the annealing of the insulating film, the resist on the insulating film is removed by ashing in a state where the insulating film contains water or an organic solvent, so that radicals and ions in the plasma cause the resist to be removed. By heating when ashing is performed, moisture or an organic solvent contained in the film from the exposed insulating film side wall is desorbed as a gas, and plasma is generated by gaseous water or the organic solvent desorbed from the insulating film. Since the radicals inside are prevented from approaching the insulating film side wall exposed by the etching, it becomes difficult for the radicals to reach the insulating film side wall, and the etching of the insulating film side wall by the radicals is suppressed.

On the other hand, the ions in the plasma are accelerated by electrostatic force and fly in a direction substantially perpendicular to the surface of the insulating film and fly. Since it is hard to receive, the reaction product attached to the side wall of the insulating film exposed at the time of ashing is removed by the ions. Therefore, when ashing the resist on the insulating film by radicals and ions, the insulating film containing water or an organic solvent has poor film quality as compared with a P-TEOS film or the like used as a conventional interlayer insulating film, Therefore, even in the case of a low dielectric film in which the side wall is easily etched by radicals, bowing in which the cross-sectional shape of the insulating film side wall is prevented is prevented, and the shape of the insulating film processed by plasma etching is reduced. There is no loss of processing accuracy due to damage.

In the method of manufacturing a semiconductor device according to the first aspect of the present invention, the insulating film to be processed by plasma etching is formed of SiH ₄ and H ₂ by CVD.
SiO ₂ film formed by reacting with O ₂ or Si (C
H ₃ ) H ₃ (monomethylsilane), Si (CH ₃ ) ₂ H
SiO ₂ film formed by reacting organic silane such as ₂ (dimethylsilane), Si (CH ₃ ) ₃ H (trimethylsilane) or Si (CH ₃ ) ₄ (tetramethylsilane) with H ₂ O ₂ Is preferred. In this case, the SiO ₂ film thus formed becomes a low dielectric film, and the S
A large amount of water is contained in the iO ₂ film.

Alternatively, in the method of manufacturing a semiconductor device according to the first aspect, the insulating film to be processed by the plasma etching may be SOG (Spin On Glass).
An SOG film formed by applying an organic insulating material using a method is preferable. In this case, the SOG film may be a low-dielectric film or a high-low-dielectric film. In any case, a large amount of organic solvent is contained in the SOG film immediately after the formation. Is contained.

[0018]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
An embodiment of the present invention will be described. 1 to 6 are process cross-sectional views illustrating a method for processing an insulating film according to an embodiment of the present invention. First, as shown in FIG. 1, a metal wiring layer 12 made of an Al (aluminum) alloy having a height of 0.65 μm and a width of 0.4 μm is formed on a Si (silicon) wafer 10. Here, Si
The structure of the impurity region and the like formed on the surface of the wafer 10 is not shown.

Subsequently, by using LP (CVD), Si (CH ₃ ) H ₃ as an organic source and H ₂ O ₂ in a gaseous state are used to cover the entire surface of the substrate with a film thickness of 1 to be used as an interlayer insulating film. A low-dielectric SiO ₂ film 14 having a thickness of 0 μm is formed, and the metal wiring layer 12 on the Si wafer 10 is buried with the low-dielectric SiO ₂ film 14. Here, this low dielectric SiO ₂ film 1
The film formation conditions of No. 4 were as follows: flow rate of H ₂ O _{2 in} a gas phase: 0.7 g / min. Flow rate of Si (CH ₃ ) H ₃ : 100 SCCM flow rate of Ar (argon): 500 SCCM reaction pressure: 1200 mTorr substrate (wafer) Temperature: 0 ° C.

At this time, Si (CH ₃ ) H ₃ and H ₂ O ₂
H ₂ O (moisture) is generated from the reaction with, and the substrate temperature during film formation is 0 ° C.
_{The two} films 14 contain a large amount of moisture. And by containing this large amount of H ₂ O,
Since this low dielectric SiO ₂ film 14 has high fluidity,
The surface of the low-dielectric SiO ₂ film 14 buried in the metal wiring layer 12 and formed on the entire surface of the substrate is flattened.

Next, as shown in FIG.
A resist 16 is applied on the iO ₂ film 14, and a pattern of a via hole having a diameter of, for example, 0.35 μm is formed by using a lithography technique. At this time, the low dielectric SiO ₂ film 14
Is different from the conventional case in that post-annealing of the low dielectric SiO ₂ film 14 is not performed after the formation of the resist and before the application of the resist 16. Thus, even at the stage of the low dielectric SiO ₂ film 14 resist 16 pattern of the via hole on are formed, the low dielectric SiO ₂ film 14 is left in the state containing a large amount of H ₂ O.

Then, as shown in FIG. 3, a low dielectric SiO ₂ film 14 containing a large amount of H ₂ O is formed by a plasma etching method using a magnetron etching apparatus, using the resist 16 of the via hole pattern as a mask.
Is started. Here, the plasma etching conditions are as follows: C ₄ F ₈ flow rate: 12 SCCM CO flow rate: 150 SCCM Ar flow rate: 200 SCCM O ₂ flow rate: 5 SCCM Pressure: 30 mTorr RF power: 1500 W Substrate temperature: 180 ° C.

[0023] The radicals and ions are generated from an etching gas C ₄ F _8, selective etching of the low dielectric SiO ₂ film 14 progresses and the via holes 18a to the low dielectric SiO ₂ film 14 surface begins to form, in FIG. As shown by a small arrow 20, a large amount of H ₂ O contained in the low dielectric SiO ₂ film 14 exposed in the via hole 18a is desorbed as a gas from the side wall. At this time, S
Since the i-wafer 10 is heated to a substrate temperature of 180 ° C., the amount of gas released from the side wall of the low dielectric SiO ₂ film 14 is sufficiently large.

[0024] Then, gaseous H ₂ to be released in large quantities from the low dielectric SiO ₂ film 14 sidewall in the via hole 18a
O functions to prevent radicals generated from the etching gas C ₄ F ₈ from approaching the side wall of the low dielectric SiO ₂ film 14. For this reason, this radical is generated in the via hole 18a.
It is difficult to reach the side wall of the low dielectric SiO ₂ film 14 in the inside, and isotropic etching of the side wall of the low dielectric SiO ₂ film 14 by radicals is suppressed.

On the other hand, ions generated from the etching gas C ₄ F ₈ are accelerated by the applied voltage and aligned in a direction substantially perpendicular to the surface of the Si wafer 10 as indicated by a large arrow 22 in the figure. Flying, low dielectric Si
Since the light is incident on the surface of the O ₂ film 14 almost perpendicularly, it is hardly affected by gaseous H ₂ O released from the side wall of the low dielectric SiO ₂ film 14. Therefore, the anisotropic etching of the low dielectric SiO ₂ film 14 by the ions proceeds.

Thus, in the selective plasma etching of the low dielectric SiO ₂ film 14 using the resist 16 as a mask, isotropic etching due to radicals is suppressed,
Anisotropic etching by ions becomes mainstream, and the etching of the low dielectric SiO ₂ film 14 proceeds.

Therefore, as shown in FIG.
_The low-dielectric SiO ₂ film 14 containing ₂ O is inferior in film quality as compared with a conventional P-TEOS film or the like used as an interlayer insulating film, so that the low-dielectric SiO ₂ film 14 exposed in the via hole 18 is formed. Despite the fact that the side walls are easily etched by radicals, bowing in which the cross-sectional shape of the low dielectric SiO ₂ film 14 in the via hole 18 becomes arcuate is prevented, and is generated from the etching gas C ₄ F _8. The via holes 18 reaching the surface of the metal wiring layer 12 are opened with a vertical cross-sectional shape with high precision and ease by anisotropic etching using ions.

Incidentally, as in the conventional case, the low dielectric SiO ₂ film 1 is used.
4 and before the application of the resist 16, low dielectric SiO ₂
The post-annealing of the film 14 is performed to obtain the low dielectric SiO ₂ film 14.
When H ₂ O is removed from the inside, in the selective plasma etching of the low dielectric SiO ₂ film 14 using the resist 16 as a mask, the isotropic etching by radicals proceeds simultaneously with the anisotropic etching by ions. Also, the side wall of the low dielectric SiO ₂ film 14 exposed in the via hole 18 is easily etched, and bowing occurs in which the cross section of the low dielectric SiO ₂ film 14 has an arcuate cross section.

Next, as shown in FIG. 5, the Si wafer 10 is subjected to low dielectric SiO ₂ using a μ (micro) wave downstream type ashing device (asher) 24.
Ashing of the resist 16 used for the selective plasma etching of the film 14 is performed. Here, the ashing conditions are as follows: O ₂ flow rate: 2000 SCCM N ₂ flow rate: 100 SCCM Pressure: 1.2 Torr μ wave power: 1000 W Substrate temperature: 250 ° C.

At this time, in the microwave downstream type ashing apparatus 24, ashing by ions and ashing by radicals occur, and the resist 16 on the low dielectric SiO ₂ film 14 is removed.

By the way, since the low dielectric SiO ₂ film 14 has not been subjected to post-annealing yet and contains a large amount of H ₂ O in the film, when the ashing is performed by heating to a substrate temperature of 250 ° C. The low dielectric Si exposed in the via hole 18 as indicated by a small arrow 26 in the figure.
H ₂ O contained in the O ₂ film 14 is desorbed from the side wall of the O ₂ film 14 as a gas. And this via hole 1
A large amount of gaseous H ₂ O released from the side wall of the low dielectric SiO ₂ film 14 in the inner layer 8 causes radicals during ashing to have a low dielectric S
This radical acts to inhibit the approach to the side wall of the iO ₂ film 14, so that the radical forms a low dielectric SiO 2 in the via hole 18.
_This makes it difficult to reach the side wall of the _second film 14 and prevents the side wall of the low dielectric SiO ₂ film 14 in the via hole 18 from being etched by radicals.

On the other hand, the ions during ashing are accelerated by the applied voltage, fly in a direction substantially perpendicular to the surface of the Si wafer 10 and fly, and enter the surface of the low dielectric SiO ₂ film 14 almost perpendicularly, and Since the gaseous H ₂ O released from the side wall of the dielectric SiO ₂ film 14 is hardly affected by the gaseous H ₂ O, a reaction product is formed on the side wall of the low dielectric SiO ₂ film 14 exposed in the via hole 18 during ashing. Even if it adheres, the reaction product adhering to the side wall of the low dielectric SiO ₂ film 14 is removed by the ions entering the via hole 18.

Thus, in the ashing of the resist 16, the resist 16 on the low-dielectric SiO ₂ film 14 is removed by ashing with ions and radicals, and the low-dielectric SiO ₂ in the via holes 18 is removed by radicals.
While the etching of the side wall of the film 14 is prevented, the reaction products attached to the side wall of the low dielectric SiO ₂ film 14 in the via hole 18 are removed by ions.

Therefore, as shown in FIG.
_The low-dielectric SiO ₂ film 14 containing ₂ O is inferior in film quality as compared with a conventional P-TEOS film or the like used as an interlayer insulating film, so that the low-dielectric SiO ₂ film 14 exposed in the via hole 18 is formed. When the resist 16 on the low-dielectric SiO ₂ film 14 is ashed, the cross-sectional shape of the low-dielectric SiO ₂ film 14 in the via hole 18 becomes arcuate even though the side walls are easily etched by radicals. The occurrence is prevented. That is, the via hole 1 opened in the plasma etching process shown in FIG.
Good ashing that easily maintains the high-precision machining accuracy without impairing the vertical cross-sectional shape of No. 8 is easily realized.

As described above, according to the present embodiment, the low-dielectric Si
When selectively etching the O ₂ film 14, a large amount of H ₂ is contained in the low-dielectric SiO ₂ film 14 without performing an annealing process.
In the state where O is still contained, and the substrate temperature is 1
By performing the plasma etching was heated to 80 ° C., the mass is contained in the film a low dielectric SiO ₂ film 14 sidewall exposed in the via hole 18 begins to be formed in the low dielectric SiO ₂ film 14 surface H ₂ O is desorbed becomes gas, since radicals in the plasma acts to inhibit the approach to low dielectric SiO ₂ film 14 sidewall, isotropic etching of the low dielectric SiO ₂ film 14 sidewall by radicals is suppressed Rutotomoni, low dielectric anisotropy etching of the SiO ₂ film 14 low dielectric SiO by ion mostly does not receive the plasma the influence of gas released from the side wall ₂ film 14 progresses.

Therefore, low dielectric S containing a large amount of H ₂ O
iO ₂ film 14 is its quality is relatively poor, despite liable to be readily etched low dielectric SiO ₂ film 14 sidewall exposed in the via hole 18 for its by radicals, low dielectric SiO ₂ in the via hole 18 It is possible to prevent bowing in which the cross-sectional shape of the side wall of the film 14 becomes arcuate, and it is possible to easily and accurately open a via hole 18 having a vertical cross-sectional shape by anisotropic etching using ions.

Also, according to the present embodiment, low dielectric SiO
_When the resist 16 used for the selective plasma etching of the _second film 14 is ashed, the substrate temperature is kept high in a state where a large amount of H ₂ O is contained in the low dielectric SiO ₂ film 14 without performing an annealing process. By performing the ashing by heating to 250 ° C., the low dielectric SiO ₂ exposed in the via hole 18 formed on the surface of the low dielectric SiO ₂ film 14 is formed.
₍₂ ) A large amount of H ₂ O contained in the film from the side wall of the film 14 is desorbed as a gas, and radicals in the plasma are reduced to low dielectric S
Since it functions to inhibit approach to the side wall of the iO ₂ film 14, etching of the side wall of the low dielectric SiO ₂ film 14 by radicals is prevented.

Therefore, low dielectric S containing a large amount of H ₂ O
iO ₂ film 14 is its quality is relatively poor, despite liable to be readily etched low dielectric SiO ₂ film 14 sidewall exposed in the via hole 18 for its by radicals, low dielectric SiO ₂ in the via hole 18 Bowing in which the cross-sectional shape of the film 14 side wall becomes arcuate can be prevented, and the high-precision processing accuracy can be easily maintained without impairing the vertical cross-sectional shape of the via hole 18 opened by plasma etching. can do.

In the above embodiment, when the low dielectric SiO ₂ film 14 used as the interlayer insulating film is formed, Si (CH ₃ ) H ₃ as an organic source and H ₂ O _{2 in a} gaseous state are used. Is formed using an LP-CVD method in which Si (CH ₃ ) H is used as an organic source.
_It is not necessary to limit to ₃ , for example, Si (CH ₃ ) ₂ H ₂ ,
Organic silanes such as Si (CH ₃ ) ₃ H and Si (CH ₃ ) ₄ may be used.

Instead of reacting these organic sources with H ₂ O ₂ , a film may be formed by reacting SiH ₄ with H ₂ O ₂ . In each case, H ₂ O was added during the reaction.
Is generated, the formed low-dielectric SiO ₂ film 14 contains a large amount of H ₂ O in the film, and is required for an interlayer insulating film that covers the steps of the base well and planarizes the surface. Liquidity.

When an SOG film formed by applying an organic insulating material such as an SOG method is used as an interlayer insulating film instead of the low dielectric SiO ₂ film 14 formed by the LP-CVD method. Also, the present invention can be applied. That is, the SOG film may be a high-dielectric film or a low-dielectric film.
A large amount of organic solvent is contained in the SOG film immediately after film formation, and the organic solvent contained in this SOG film is similar to the H ₂ O contained in the low dielectric SiO ₂ film 14 described in the above embodiment. Act on.

Therefore, when selectively etching the SOG film using the resist of the via hole pattern as a mask, plasma etching should be performed in a state where a large amount of organic solvent is contained in the film without performing annealing treatment. This makes it possible to prevent bowing in which the cross-sectional shape of the side wall of the SOG film exposed in the via hole becomes arcuate, and to easily and precisely open a via hole having a vertical cross-sectional shape.

When ashing is performed on the resist used for the plasma etching, the ashing is performed in a state where a large amount of organic solvent is contained in the film without performing the annealing process, so that the S in the via hole is reduced.
It is possible to prevent occurrence of bowing in which the cross-sectional shape of the OG film side wall becomes arcuate, and easily maintain high-precision processing accuracy without damaging the vertical cross-sectional shape of the via hole opened by plasma etching. be able to.

In the above embodiment, the case where the low dielectric SiO ₂ film 14 has a single-layer structure as the interlayer insulating film has been described. However, another type of insulating film may be formed below or above the low dielectric SiO ₂ film 14. Even in the case of forming and processing an interlayer insulating film having a two-layer structure or a three-layer structure, the low-dielectric SiO ₂ film 14 constituting the interlayer insulating film having such a multilayer structure contains H ₂ O in the film. The present invention can be applied as long as plasma etching and ashing can be performed in the state as it is.

In the above embodiment, the low dielectric S
Although the case where the via hole 18 is opened in the iO ₂ film 14 has been described, the low-dielectric SiO ₂ film 14 is etched by using a resist of a predetermined pattern as a mask, for example, when forming a groove for damascene, for example, when forming a via hole 18. The present invention can be applied to all cases of processing. In addition, various conditions of each process described in the above embodiment can be changed without departing from the spirit of the present invention.

[0046]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the following effects can be obtained.

That is, according to the method of manufacturing a semiconductor device of the present invention, in a state where the insulating film contains moisture or an organic solvent, selective plasma etching of the insulating film using a resist of a predetermined pattern as a mask. With the selective etching of the insulating film by radicals and ions in the plasma, moisture or an organic solvent contained in the film is desorbed from the insulating film as a gas and desorbed from the insulating film. Since the gaseous moisture or the organic solvent prevents radicals in the plasma from reaching the side wall of the insulating film exposed by the etching, isotropic etching of the insulating film by the radicals is suppressed and the insulating film Anisotropic etching of the insulating film by ions in the plasma, which is hardly affected by the gas desorbed from Etching it will be to proceed.

Therefore, even if the insulating film containing water or the organic solvent is a low-dielectric film whose film quality is relatively poor and the side wall is easily etched by radicals, the cross-sectional shape of the side wall exposed by the etching can be obtained. It is possible to prevent bowing, which becomes arcuate, and to easily perform high-precision processing. As a result, various low dielectric films containing water or an organic solvent can be used as interlayer insulating films.

According to the method of manufacturing a semiconductor device of the present invention, when the insulating film containing moisture or an organic solvent is plasma-etched, the substrate is heated.
Since the amount of desorption when water or an organic solvent contained in the insulating film is desorbed as a gas increases, isotropic etching of the insulating film due to radicals in plasma is further suppressed, and the insulating film is insulated. The processing accuracy of the film can be further improved.

According to the method of manufacturing a semiconductor device of the present invention, after the insulating film containing water or an organic solvent is plasma-etched using a resist having a predetermined pattern as a mask, the insulating film contains water or an organic solvent. When the resist on the insulating film is removed by ashing in the state where the resist is ashing, the resist is contained in the film from the side wall of the insulating film exposed by the etching due to heating when ashing the resist by radicals and ions in the plasma. The water or the organic solvent is desorbed as a gas, and the gaseous water or the organic solvent desorbed from the insulating film prevents radicals in the plasma from reaching the side wall of the insulating film exposed by etching. While the etching of the insulating film side wall due to the radicals is suppressed,
The reaction products attached to the side walls of the insulating film during the ashing are removed by the ions in the plasma which are hardly affected by the gas desorbed from the insulating film.

Therefore, even when the insulating film containing water or the organic solvent is a low-dielectric film having relatively poor film quality and the side walls of which are easily etched by radicals, the insulating film is not easily removed when ashing the resist. It is possible to prevent bowing in which the cross-sectional shape of the film sidewall becomes arcuate, and it is possible to easily maintain high-precision processing accuracy without impairing the shape of the insulating film processed by plasma etching. . As a result, various low dielectric films containing water or an organic solvent can be used as interlayer insulating films.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view (part 1) for describing a method for processing an insulating film according to an embodiment of the present invention.

FIG. 2 is a process cross-sectional view (part 2) for describing the method for processing an insulating film according to one embodiment of the present invention.

FIG. 3 is a process cross-sectional view (part 3) for describing the method for processing an insulating film according to one embodiment of the present invention.

FIG. 4 is a process cross-sectional view (part 4) for describing the method for processing an insulating film according to one embodiment of the present invention.

FIG. 5 is a process sectional view (part 5) for describing the method for processing the insulating film according to the embodiment of the present invention.

FIG. 6 is a process sectional view (part 6) for describing the method for processing the insulating film according to the embodiment of the present invention.

[Explanation of symbols]

10: Si wafer, 12: metal wiring layer, 14: low dielectric SiO ₂ film, 16: resist, 18a, 18: via hole, 20: arrow indicating that H ₂ O in the film is desorbed as gas, 22: arrow indicating the arrival of ions, 24: microwave downstream ashing device, 26: H _{2 in the} film
Arrow indicating that O becomes a gas and desorbs.

Claims (6)

[Claims] 1. A method for manufacturing a semiconductor device, comprising: forming an insulating film containing water or an organic solvent on a substrate, and selectively etching the insulating film using a resist having a predetermined pattern as a mask; A method of manufacturing a semiconductor device, comprising: performing plasma etching on an insulating film in a state where the insulating film contains moisture or an organic solvent before performing an annealing process on the insulating film. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said substrate is heated when said insulating film is plasma-etched. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the insulating film contains moisture or an organic solvent after the insulating film is plasma-etched and before the insulating film is annealed. Removing the resist on the insulating film by ashing in the state. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the insulating film is formed by chemical vapor deposition for reacting silane with hydrogen peroxide or chemical vapor for reacting organic silane with hydrogen peroxide. A method for manufacturing a semiconductor device, wherein the semiconductor device is formed on the substrate by phase growth. 5. The method for manufacturing a semiconductor device according to claim 4, wherein the organic silane is monomethylsilane, dimethylsilane, trimethylsilane, or tetramethylsilane. 6. The method for manufacturing a semiconductor device according to claim 1, wherein the insulating film is formed on the substrate by applying an organic insulating material.