KR100313542B1 - Manufacturing method for gate in semiconductor device - Google Patents
Manufacturing method for gate in semiconductor device Download PDFInfo
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- KR100313542B1 KR100313542B1 KR1019990064663A KR19990064663A KR100313542B1 KR 100313542 B1 KR100313542 B1 KR 100313542B1 KR 1019990064663 A KR1019990064663 A KR 1019990064663A KR 19990064663 A KR19990064663 A KR 19990064663A KR 100313542 B1 KR100313542 B1 KR 100313542B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title description 5
- 238000005530 etching Methods 0.000 claims abstract description 48
- 238000000034 method Methods 0.000 claims abstract description 46
- 239000010408 film Substances 0.000 claims abstract description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 229920005591 polysilicon Polymers 0.000 claims abstract description 20
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 238000000427 thin-film deposition Methods 0.000 claims abstract description 3
- 229920000642 polymer Polymers 0.000 abstract description 6
- 238000007796 conventional method Methods 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 19
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000032683 aging Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
본 발명은 반도체 장치의 게이트 형성방법에 관한 것으로, 종래 반도체 장치의 게이트 형성방법은 두께가 얇은 게이트산화막의 상부측 게이트전극을 형성할때, Cl2와 O2, Cl2와 HBr, Cl2와 SF6를 사용하여 고선택비를 달성하여 기판의 손상을 방지할 수 있으나, 게이트전극의 형성시 폴리머의 발생량이 많고, 공정의 경시변화가 심하여 공정의 안정성이 저하됨과 아울러 공정신뢰성이 저하되는 문제점이 있었다. 이와 같은 문제점을 감안한 본 발명은 기판의 상부에 50~80Å의 두께를 갖는 게이트산화막을 증착하고, 그 게이트산화막의 상부전면에 다결정실리콘을 증착하는 박막증착단계와; 식각가스로 Cl2, N2혼합가스를 사용하는 식각공정으로 상기 다결정실리콘 일부영역의 상부일부를 제거하는 제1식각단계와; 상기 제1식각단계의 공정조건중 알에프 전력의 값을 낮추어 식각선택비를 향상시켜, 상기 제1식각단계에서 상부일부가 식각된 다결정실리콘을 식각하여 상기 게이트산화막을 노출시키는 제2식각단계로 구성되어, 두꺼운 게이트산화막을 갖는 게이트전극 형성시 사용하던 공정특성이 안정된 식각가스를 사용하며, 공정조건을 변경하여 게이트산화막과의 식각선택비를 향상시켜 기판이 손상되는 것을 방지함으로써, 공정의 신뢰성을 향상시킴과 아울러 공정의 안정성을 확보하는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a gate of a semiconductor device. In the conventional method of forming a gate of a semiconductor device, Cl 2 and O 2 , Cl 2 and HBr, and Cl 2 It is possible to prevent damage to the substrate by achieving a high selectivity by using SF 6 , but there is a large amount of polymer generated when forming the gate electrode, and the change over time of the process is so severe that the process stability is lowered and the process reliability is lowered. There was this. In view of the above problems, the present invention includes a thin film deposition step of depositing a gate oxide film having a thickness of 50 ~ 80Å on the top of the substrate, and depositing polysilicon on the upper surface of the gate oxide film; A first etching step of removing a portion of the upper portion of the polysilicon partial region by an etching process using a mixed gas of Cl 2 and N 2 as an etching gas; A second etching step of exposing the gate oxide layer by etching polycrystalline silicon having an upper portion etched in the first etching step by improving the etching selectivity by lowering the value of the RF power in the process conditions of the first etching step. By using an etching gas with stable process characteristics used in forming a gate electrode having a thick gate oxide film, and changing process conditions, the etching selectivity with the gate oxide film is improved to prevent damage to the substrate, thereby improving process reliability. In addition to improving the stability of the process is effective.
Description
본 발명은 반도체 장치의 게이트 형성방법에 관한 것으로, 특히 상대적으로 두꺼운 게이트산화막 패턴 형성에 사용하는 식각가스를 상대적으로 얇은 게이트산화막 패턴 형성에 적용할 수 있도록 공정조건을 최적화하여 공정의 안정화 및 신뢰성을 향상시키는데 적당하도록 한 반도체 장치의 게이트 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate of a semiconductor device. In particular, the process conditions are optimized to apply the etching gas used to form a relatively thick gate oxide pattern to form a relatively thin gate oxide pattern. A method for forming a gate of a semiconductor device suitable for improvement.
일반적으로 90Å이상의 두께를 갖는 두꺼운 게이트산화막의 상부에 위치하는 게이트전극 패턴의 형성을 위해서 취급이 용이하고, 공정진행에 따른 경시변화가 적은 Cl2/N2가스를 사용하였으나, 게이트 산화막의 두께가 얇아지면서 O2의 추가, 또는 HBr의 사용으로 게이트산화막과 기판인 실리콘과의 선택비를 향상시켜 게이트 형성시 기판에 손상을 주는 것을 방지하였으나, 게이트전극의 형성시 폴리머의 발생증가와 경시변화가 심해 공정의 신뢰성을 저하시키고 있으며, 이와 같은 종래 반도체 장치의 게이트 형성방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.In general, Cl 2 / N 2 gas, which is easy to handle and has a small change over time according to process progress, is used to form a gate electrode pattern positioned on a thick gate oxide film having a thickness of 90 GPa or more, but the thickness of the gate oxide film is thinner as O 2 added, or for increasing the selectivity of the silicon gate oxide film and the substrate with the use of HBr but prevent damage at the time of the gate-forming substrate, generated increased with the aging of the polymer during formation of the gate electrodes of the The reliability of the deep sea process is deteriorated, and the gate forming method of the conventional semiconductor device will be described in detail with reference to the accompanying drawings.
도1a 및 도1b는 종래 두꺼운 게이트산화막이 적용된 반도체 장치의 게이트 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 90Å이상의 게이트산화막(2)을 증착하고, 그 게이트산화막(2)의 상부전면에 다결정실리콘(3)을 증착한 후, Cl2, N2혼합가스를 사용하는 식각공정으로 상기 증착된 다결정실리콘(3)을 패터닝하여 게이트를 형성하는 단계(도1a)와; 식각공정을 통해 상기 다결정실리콘 패턴(3)의 형성시 발생하는 폴리머(4)를 제거하는 단계(도1b)로 구성된다.1A and 1B are cross-sectional views of a gate fabrication process of a semiconductor device to which a conventional thick gate oxide film is applied. As shown therein, a gate oxide film 2 having a thickness of 90 kV or more is deposited on the substrate 1, and the gate oxide film 2 Depositing polycrystalline silicon (3) on the upper surface of the N), and then patterning the deposited polysilicon (3) by an etching process using Cl 2 , N 2 mixed gas to form a gate (FIG. 1A); Removing the polymer (4) generated during the formation of the polysilicon pattern 3 through the etching process (Fig. 1b).
이와 같이 그 게이트산화막(2)이 충분히 두꺼운 경우에는 다결정실리콘(3)의 식각시 게이트산화막(2)의 일부가 식각되어 기판(1)이 노출되어 기판(1)이 손상되는 경우가 없으며, 이에 따라 특별히 실리콘과 산화막 간의 고선택비를 갖지않는 Cl2, N2혼합가스와 고전력(TOP POWER : 250W 이상, BOTTOM RF POWER : 80W이상)을 사용하였으나, 그 게이트산화막(2)이 50~80Å의 두께를 갖는 공정에서는 상기 Cl2, N2혼합가스를 사용할 경우에는 게이트산화막(2)의 일부가 유실되어 기판(1)이 손상될 우려가 있다.As such, when the gate oxide film 2 is sufficiently thick, a part of the gate oxide film 2 is etched during the etching of the polysilicon 3 so that the substrate 1 is not exposed and the substrate 1 is not damaged. Therefore, Cl 2 and N 2 mixed gas and high power (TOP POWER: 250W or more, BOTTOM RF POWER: 80W or more) that do not have a high selectivity between silicon and oxide film were used, but the gate oxide film (2) was 50 ~ 80Å. In the step having a thickness, when the Cl 2 and N 2 mixed gases are used, a part of the gate oxide film 2 may be lost and the substrate 1 may be damaged.
상기한 바와 같이 기판(1)의 손상을 방지하기 위해 Cl2가스와 N2가스가 아닌 Cl2과 다른 가스를 혼합하여 게이트전극을 형성하는 식각가스로 사용한다. 이와 같은 가스의 대표적인 예로 Cl2와 O2또는 Cl2와 HBr, Cl2와 SF6를 들수 있다.A mixture of Cl 2 and other gas than the Cl 2 gas and the N 2 gas to prevent damage to the substrate 1 as described above is used as an etching gas for forming the gate electrode. Representative examples of such gases include Cl 2 and O 2 or Cl 2 and HBr, Cl 2 and SF 6 .
상기 O2, HBr, SF6를 사용하는 경우 게이트산화막과 기판의 선택비를 증가시켜 기판의 손상은 방지할 수 있으나, 다결정실리콘의 식각시 폴리머 발생이 증가하고, 공정 특성의 경시변화가 심해 공정의 안정화와 그 신뢰성이 저하된다.In the case of using O 2 , HBr, and SF 6 , the damage of the substrate can be prevented by increasing the selectivity of the gate oxide layer and the substrate, but the polymer generation during the etching of the polysilicon is increased, and the process characteristics are severely changed over time. Stabilization and its reliability is lowered.
상기한 바와 같이 종래 반도체 장치의 게이트 형성방법은 두께가 얇은 게이트산화막의 상부측 게이트전극을 형성할때, Cl2와 O2, Cl2와 HBr, Cl2와 SF6를 사용하여 고선택비를 달성하여 기판의 손상을 방지할 수 있으나, 게이트전극의 형성시 폴리머의 발생량이 많고, 공정의 경시변화가 심하여 공정의 안정성이 저하됨과 아울러 공정신뢰성이 저하되는 문제점이 있었다.As described above, the gate forming method of the conventional semiconductor device has a high selectivity using Cl 2 and O 2 , Cl 2 and HBr, Cl 2 and SF 6 when forming the upper gate electrode of the thin gate oxide film. Although it is possible to prevent damage to the substrate, there is a problem in that a large amount of polymer is generated when the gate electrode is formed, and a change of the process over time causes a decrease in process stability and process reliability.
이와 같은 문제점을 감안한 본 발명은 공정의 안정성이 우수한 Cl2, N2혼합가스를 사용하며, 기판의 손상을 방지할 수 있는 반도체 장치의 게이트 형성방법을 제공함에 그 목적이 있다.In view of the above problems, an object of the present invention is to provide a method of forming a gate of a semiconductor device using Cl 2 , N 2 mixed gas having excellent process stability and preventing damage to a substrate.
도1a 및 도1b는 종래 반도체 장치의 게이트 제조공정 수순단면도.1A and 1B are cross-sectional views of a gate manufacturing process of a conventional semiconductor device.
도2a 및 도2b는 본 발명 반도체 장치의 게이트 제조공정 수순단면도.2A and 2B are cross-sectional views of a gate manufacturing process of the semiconductor device of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
1:기판 2:게이트산화막1: Substrate 2: Gate Oxide
3:다결정실리콘3: polycrystalline silicon
상기와 같은 목적은 기판의 상부에 50~80Å의 두께를 갖는 게이트산화막을 증착하고, 그 게이트산화막의 상부전면에 다결정실리콘을 증착하는 박막증착단계와; 식각가스로 Cl2, N2혼합가스를 사용하는 식각공정으로 상기 다결정실리콘 일부영역의 상부일부를 제거하는 제1식각단계와; 상기 제1식각단계의 공정조건중 알에프 전력의 값을 낮추어 식각선택비를 향상시켜, 상기 제1식각단계에서 상부일부가 식각된 다결정실리콘을 식각하여 상기 게이트산화막을 노출시키는 제2식각단계로 구성함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The above object is a thin film deposition step of depositing a gate oxide film having a thickness of 50 ~ 80Å on the top of the substrate, and depositing polysilicon on the upper surface of the gate oxide film; A first etching step of removing a portion of the upper portion of the polysilicon partial region by an etching process using a mixed gas of Cl 2 and N 2 as an etching gas; A second etching step of exposing the gate oxide layer by etching polycrystalline silicon having an upper portion etched in the first etching step by improving the etching selectivity by lowering the value of the RF power in the process conditions of the first etching step. This is achieved by, when described in detail with reference to the accompanying drawings, the present invention as follows.
도2a 및 도2b는 본 발명 반도체 장치의 게이트 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)의 상부전면에 50~80Å의 게이트산화막(2)을 증착하고, 그 게이트산화막(2)의 상부전면에 다결정실리콘(3)을 증착한 후, Cl2, N2혼합가스를 사용하는 식각공정으로, 상기 다결정실리콘(3)의 일부를 소정깊이로 식각하는 제1식각단계(도2a)와; 상기 공정의 진행중 소정깊이로 식각된 하부의다결정실리콘(3)을 상기 Cl2, N2혼합가스를 사용하며, 전력을 낮춘 분위기 하에서 식각하여 게이트전극을 형성하는 제2식각단계(도2b)로 구성된다.2A and 2B are cross-sectional views of a gate fabrication process of the semiconductor device according to the present invention. As shown therein, a gate oxide film 2 of 50 to 80 kV is deposited on the upper surface of the substrate 1, and the gate oxide film 2 is formed. After the deposition of the polysilicon 3 on the upper surface of the first etching step of etching a portion of the polysilicon 3 to a predetermined depth by an etching process using a Cl 2 , N 2 mixed gas (Fig. 2a) Wow; In the second etching step (FIG. 2B), the lower polycrystalline silicon 3 etched to a predetermined depth during the process is etched using the Cl 2 , N 2 mixed gas and is etched under a low power atmosphere to form a gate electrode. It is composed.
이하, 상기와 같은 본 발명 반도체 장치의 게이트 형성방법을 좀 더 상세히 설명한다.Hereinafter, a method of forming a gate of the semiconductor device of the present invention as described above will be described in more detail.
먼저, 도2a에 도시한 바와 같이 기판(1)의 상부전면에 두께가 50~80Å인 게이트산화막(2)을 증착하고, 그 게이트산화막(2)의 상부전면에 다결정실리콘(3)을 증착한다.First, as shown in FIG. 2A, a gate oxide film 2 having a thickness of 50 to 80 Å is deposited on the upper surface of the substrate 1, and polysilicon 3 is deposited on the upper surface of the gate oxide film 2. .
그 다음, 상기 다결정실리콘(3)의 상부에 포토레지스트(PR)를 도포하고, 노광 및 현상하여 상기 다결정실리콘(3)의 상부일부에 위치하는 패턴을 형성한다.Next, photoresist PR is applied on the polysilicon 3, exposed and developed to form a pattern located on an upper portion of the polysilicon 3.
그 다음, Cl2, N2혼합가스를 식각가스로 사용하며, 압력분위기 5.0mT, 챔버내의 직류전력인 TOP POWER를 150W 사용하며, 알에프전력을 100W로 사용하는 식각공정으로, 상기 포토레지스트(PR) 측면에 노출된 다결정실리콘(3)의 상부일부를 식각한다.Next, Cl 2 , N 2 mixed gas is used as an etching gas, the pressure atmosphere is 5.0mT, 150W of TOP power which is DC power in the chamber, and 100W of RF power is used for the etching process. Etch the upper portion of the polysilicon 3 exposed on the side.
이와 같은 식각공정은 낮은 알에프전력으로는 다결정실리콘(3) 패턴을 수직으로 형성하기 어렵기 때문에 높은 알에프전력을 사용하며, 상부일부만을 식각하여 기판(1)의 손상을 방지한다.Since the etching process is difficult to form the polysilicon 3 pattern vertically with low RF power, high etching power is used, and only a portion of the upper portion is etched to prevent damage to the substrate 1.
그 다음, 도2b에 도시한 바와 같이 상기 포토레지스트(PR) 패턴을 식각마스크로 사용하며, 식각가스로는 Cl2, N2혼합가스를, TOP POWER 150W로 하며, 알에프전력을 15W로 크게 낮춘 식각공정으로 상기 상부일부가 식각된 다결정실리콘(3)을 모두식각한다.Next, as shown in FIG. 2B, the photoresist (PR) pattern is used as an etching mask, and the etching gas is a mixture of Cl 2 and N 2 , TOP POWER 150W, and the RF power is greatly reduced to 15W. In the process, all of the polysilicon 3 etched above the upper portion is etched.
이때의 식각공정은 알에프전력을 낮추어 산화막과의 식각선택비를 증가시킬 수 있으며, 이에 따라 기판(1)이 손상되는 것을 방지할 수 있게 된다.In this case, the etching process may lower the RF power, thereby increasing the etching selectivity with the oxide film, thereby preventing the substrate 1 from being damaged.
또한, 상기 TOP POWER를 150W로 유지한다. 이는 고선택비를 확보하기 위해 알에프전력을 낮추면 다결정실리콘 패턴의 측면에 경사가 발생할 수 있다. TOP POWER가 높으면 폴리머의 발생량이 증가하여 다결정실리콘 패턴의 측면이 경사지게 되며, TOP POWER가 너무 낮아지면 다결정실리콘(3)에 언더커팅(UNDER CUTTING)이 발생하여 공정의 신뢰성이 저하되기 때문이다.In addition, the TOP POWER is maintained at 150W. This is because when the RF power is lowered to secure a high selectivity, the slope of the polysilicon pattern may occur. If the TOP POWER is high, the amount of polymer generated increases and the side surface of the polycrystalline silicon pattern is inclined. If the TOP POWER is too low, undercutting occurs in the polysilicon 3, thereby lowering the reliability of the process.
상기한 바와 같이 본 발명은 두꺼운 게이트산화막을 갖는 게이트전극 형성시 사용하던 공정특성이 안정된 식각가스를 사용하며, 공정조건을 변경하여 게이트산화막과의 식각선택비를 향상시켜 기판이 손상되는 것을 방지함으로써, 공정의 신뢰성을 향상시킴과 아울러 공정의 안정성을 확보하는 효과가 있다.As described above, the present invention uses an etching gas having stable process characteristics when forming a gate electrode having a thick gate oxide film, and improves an etching selectivity with the gate oxide film by changing process conditions to prevent damage to the substrate. In addition, it improves the reliability of the process and secures the stability of the process.
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