KR100312382B1 - Method of manufacturing a transistor in a semiconductor device - Google Patents
Method of manufacturing a transistor in a semiconductor device Download PDFInfo
- Publication number
- KR100312382B1 KR100312382B1 KR1019990023929A KR19990023929A KR100312382B1 KR 100312382 B1 KR100312382 B1 KR 100312382B1 KR 1019990023929 A KR1019990023929 A KR 1019990023929A KR 19990023929 A KR19990023929 A KR 19990023929A KR 100312382 B1 KR100312382 B1 KR 100312382B1
- Authority
- KR
- South Korea
- Prior art keywords
- gate
- oxide film
- doped polysilicon
- polysilicon layer
- semiconductor device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 44
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 28
- 229920005591 polysilicon Polymers 0.000 claims abstract description 28
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 22
- 239000010937 tungsten Substances 0.000 claims abstract description 22
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 20
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 18
- 230000003647 oxidation Effects 0.000 claims abstract description 15
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 5
- 230000008021 deposition Effects 0.000 claims abstract 2
- 230000004888 barrier function Effects 0.000 claims description 12
- 238000009792 diffusion process Methods 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 7
- 238000004140 cleaning Methods 0.000 claims description 5
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 3
- -1 tungsten nitride Chemical class 0.000 claims description 2
- 238000000059 patterning Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000002955 isolation Methods 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 반도체 소자의 트랜지스터 제조 방법에 관한 것으로, 텅스텐/폴리 게이트 전극 형성시 텅스텐(W) 과 실리콘(Si)의 산화 비(oxidation rate) 차이에 의한 산화 공정의 어려움을 해결하기 위하여, 폴리실리콘층 증착 및 패터닝 공정을 진행한 후, 폴리 산화 공정을 진행하고, 소오스/드레인 접합부를 형성한 후, 절연막을 증착하고, 이후 노광/식각 공정을 거친 후 텅스텐(W)을 증착하여 텅스텐/폴리 게이트 전극을 갖는 트랜지스터 제조 방법에 관하여 기술된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor manufacturing method of a semiconductor device. In order to solve the difficulty of an oxidation process due to a difference in oxidation rate of tungsten (W) and silicon (Si) when forming a tungsten / poly gate electrode, polysilicon After the layer deposition and patterning process, the poly-oxidation process is performed, the source / drain junction is formed, the insulating film is deposited, and after the exposure / etching process, the tungsten (W) is deposited to deposit the tungsten / poly gate. A method of manufacturing a transistor having an electrode is described.
Description
본 발명은 반도체 소자의 트랜지스터 제조 방법에 관한 것으로, 특히 메탈/폴리(metal/poly) 게이트 전극 형성시 메탈과 폴리의 산화 비(oxidation rate) 차이에 의한 산화 공정의 어려움을 해결하여 양호한 메탈/폴리 게이트 전극을 형성하므로써, 성능이 향상된 트랜지스터를 얻을 수 있는 트랜지스터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor of a semiconductor device, and in particular, to solve the difficulty of the oxidation process due to the difference in oxidation rate between metal and poly when forming a metal / poly gate electrode. By forming a gate electrode, the present invention relates to a transistor manufacturing method capable of obtaining a transistor having improved performance.
일반적으로, 반도체 소자가 고집적화 됨에 따라 게이트에서의 시정수 지연 시간(RC delay time)은 소자의 프리퀀시 시간(frequency time)특성을 결정하는 주요 인자로 대두되고 있다. 0.2㎛ 이상의 소자에서는 비저항 70 내지 100μΩ㎝를 갖는 텅스텐실리사이드/폴리실리콘(WSix/Poly Si) 구조를 사용하고 있으나, 소자가 더욱 고집적화 됨에 따라 텅스텐실리사이드/폴리실리콘의 높은 저항 문제로 시정수 지연 시간이 증가되어, 이로 인하여 0.2㎛이하의 소자에서는 사용하기 힘들며, 0.15㎛ 이하의 소자에서는 10Ω/?이하의 낮은 면저항이 요구된다. 이러한 낮은 면저항을 갖기 위해서는 50μΩ㎝이하의 비저항을 갖는 물질이 요구되며, 이러한 조건을 만족하는 것이 텅스텐/폴리실리콘(W/Poly Si) 구조이다. 일반적인 MOSFET에서 게이트와 드레인간의 오버랩 캐패시턴스(overlap capacitance)를 감소시키고, GOI(gate oxide integrity) 특성 향상을 위해 게이트 가장자리 부위에서 게이트 산화(gate oxide) 강화가 필수적이다. 그래서 게이트를 형성한 후 소오스/드레인 지역에 이온 주입(implant)전 산화(oxidation) 공정이 필수적이다. 그러나 텅스텐/폴리실리콘 게이트 구조에서는 폴리실리콘과 텅스텐의 산화 비 차이에 의해 텅스텐의 비정상 산화(W abnormal oxidation)에 의한 결함(defect) 및 게이트간의 브릿지(bridge)를 유발시켜 텅스텐/폴리실리콘 구조를 갖는 소자에서는 게이트 패터닝을 위한 식각 공정 후, 산화 공정을 적용할 수 없어 소자의 특성을 저하시키는 문제가 있다.In general, as semiconductor devices are highly integrated, an RC delay time at a gate has become a major factor in determining a frequency time characteristic of a device. Tungsten silicide / polysilicon (WSix / Poly Si) structure with specific resistivity of 70 to 100μΩcm is used in devices larger than 0.2㎛, but time constant delay time is increased due to high resistance of tungsten silicide / polysilicon as the device becomes more integrated. As a result, it is difficult to use in devices of 0.2 탆 or less, and low sheet resistance of 10 Ω /? Or less is required in devices of 0.15 탆 or less. In order to have such a low sheet resistance, a material having a resistivity of 50 µΩcm or less is required, and a tungsten / polysilicon (W / Poly Si) structure is satisfied. Gate oxide reinforcement at the gate edge is essential to reduce overlap capacitance between gate and drain and improve gate oxide integrity (GOI) in a typical MOSFET. Thus, after the gate is formed, an oxidation process before ion implantation into the source / drain region is essential. However, in the tungsten / polysilicon gate structure, defects caused by abnormal abnormality of tungsten and bridges between gates are caused by the difference in the oxidation ratio between polysilicon and tungsten. In the device, an oxidation process cannot be applied after the etching process for the gate patterning, and thus there is a problem of deteriorating the characteristics of the device.
따라서, 본 발명은 메탈/폴리(metal/poly) 게이트 전극 형성시 메탈과 폴리의 산화 비(oxidation rate) 차이에 의한 산화 공정의 어려움을 해결하여 양호한 메탈/폴리 게이트 전극을 형성하므로써, 성능이 향상된 트랜지스터를 얻을 수 있는 트랜지스터 제조 방법을 제공함에 그 목적이 있다.Accordingly, the present invention solves the difficulty of the oxidation process due to the difference in oxidation rate between metal and poly when forming a metal / poly gate electrode to form a good metal / poly gate electrode, thereby improving performance. It is an object of the present invention to provide a transistor manufacturing method capable of obtaining a transistor.
이러한 목적을 달성하기 위한 본 발명의 반도체 소자의 트랜지스터 제조 방법은 반도체 기판상에 게이트 산화막, 도프트 폴리실리콘층 게이트 패턴 및 반사 방지막이 순차적으로 적층된 패턴을 형성하는 단계; 폴리 산화 공정을 실시하여 열산화막을 형성하는 단계; LDD 이온 주입 공정을 실시한 후, 게이트 스페이서를 형성하고, 소오스/드레인 이온 주입 공정으로 소오스/드레인 접합부를 형성하는 단계; 전체 구조상에 산화막을 증착한 후, 상기 도프트 폴리실리콘층 게이트 패턴 위의 산화막, 열산화막 및 제 1 반사 방지막을 제거하여 상부면을 노출시키는 단계; 세정 공정을 진행한 후, 전체구조상에 확산 방지막, 텅스텐층 및 제 2 반사 방지막을 순차적으로 형성하고, 게이트 마스크를 사용하여 노광 및 배선 공정을 거쳐 상기 도프트 폴리실리콘층 게이트 패턴상에 상기 확산 방지막 및 텅스텐층이 적층되도록 하고, 이로 인하여 도프트 폴리실리콘층 게이트 패턴, 확산 방지막 및 텅스텐층이 적층된 게이트 전극이 완성되는 단계를 포함하여 이루어지는 것을 특징으로 한다.The transistor manufacturing method of the semiconductor device of the present invention for achieving the above object comprises the steps of forming a pattern in which a gate oxide film, a doped polysilicon layer gate pattern and an antireflection film are sequentially stacked on a semiconductor substrate; Performing a poly oxidation process to form a thermal oxide film; After performing the LDD ion implantation process, forming a gate spacer and forming a source / drain junction by a source / drain ion implantation process; After depositing an oxide film on the entire structure, exposing an upper surface by removing an oxide film, a thermal oxide film, and a first anti-reflection film on the doped polysilicon layer gate pattern; After the cleaning process, a diffusion barrier film, a tungsten layer and a second antireflection film are sequentially formed on the entire structure, and the diffusion barrier film is formed on the doped polysilicon layer gate pattern through an exposure and wiring process using a gate mask. And allowing the tungsten layer to be stacked, thereby completing a doped polysilicon layer gate pattern, a diffusion barrier layer, and a gate electrode on which the tungsten layer is stacked.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 트랜지스터 제조 방법을 설명하기 위한 소자의 단면도.1A to 1D are cross-sectional views of a device for explaining a transistor manufacturing method of a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>
1: 반도체 기판 2: 소자 분리막1: semiconductor substrate 2: device isolation film
3: 게이트 산화막 4: 도프트 폴리실리콘층 게이트 패턴3: gate oxide film 4: doped polysilicon layer gate pattern
5: 제 1 반사 방지막 6: 열산화막5: first antireflection film 6: thermal oxide film
7: 게이트 스페이서 8: 소오스/드레인 접합부7: gate spacer 8: source / drain junction
9: 산화막 10: 포토레지스트 패턴9: oxide film 10: photoresist pattern
11: 확산 방지막 12: 텅스텐층11: diffusion barrier film 12: tungsten layer
13: 제 2 반사 방지막 100: 게이트 전극13: second antireflection film 100: gate electrode
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 트랜지스터 제조 방법을 설명하기 위한 소자의 단면도이다.1A to 1D are cross-sectional views of devices for describing a method of manufacturing a transistor of a semiconductor device in accordance with an embodiment of the present invention.
도 1a를 참조하면, 반도체 기판(1)에 소자 분리막(2)을 형성하여 액티브 영역(active region)과 필드 영역(field region)을 확정(define)한 후, 게이트 산화막(3)을 형성한다. 게이트 산화막(3) 상에 도프트 폴리실리콘층(4) 및 제 1 반사 방지막(5)을 순차적으로 증착한다. 게이트 마스크를 사용하여 노광 및 배선 공정을 거쳐 도프트 폴리실리콘층 게이트 패턴(4)을 형성한다.Referring to FIG. 1A, an isolation layer 2 is formed on a semiconductor substrate 1 to define an active region and a field region, and then form a gate oxide layer 3. The doped polysilicon layer 4 and the first antireflection film 5 are sequentially deposited on the gate oxide film 3. The doped polysilicon layer gate pattern 4 is formed through an exposure and wiring process using a gate mask.
상기에서, 게이트 산화막(3)은 40 내지 70Å의 두께로 형성한다. 도프트 폴리실리콘층(4)은 500 내지 1000Å의 두께로 형성한다. 제 1 반사 방지막(5)은 질화물을 300 내지 600Å의 두께로 증착하여 형성한다.In the above, the gate oxide film 3 is formed to a thickness of 40 to 70 Å. The doped polysilicon layer 4 is formed to a thickness of 500 to 1000 mm 3. The first anti-reflection film 5 is formed by depositing nitride to a thickness of 300 to 600 kPa.
도 1b를 참조하면, 폴리 산화(poly oxidation) 공정을 실시하여 열산화막(6)을 형성한다. LDD 이온 주입 공정을 실시한 후, 게이트 스페이서(7)를 형성하고, 소오스/드레인 이온 주입 공정으로 소오스/드레인 접합부(8)를 형성한다.Referring to FIG. 1B, a thermal oxidation film 6 is formed by performing a poly oxidation process. After the LDD ion implantation process, the gate spacer 7 is formed, and the source / drain junction 8 is formed by the source / drain ion implantation process.
상기에서, 폴리 산화 공정은 700 내지 900℃의 온도에서 실시하여 열산화막(6)이 30 내지 100Å의 두께가 되도록 한다. 열산화막(6)은 게이트와 드레인간의 오버랩 캐패시턴스를 감소시키고, 게이트 가장자리 부분에서 게이트 산화(gate oxide)를 강화시켜 GOI 특성을 향상시킨다.In the above, the poly-oxidation process is carried out at a temperature of 700 to 900 ℃ so that the thermal oxidation film 6 is 30 to 100 kPa thickness. The thermal oxide film 6 reduces the overlap capacitance between the gate and the drain, and enhances the gate oxide at the gate edge to improve GOI characteristics.
도 1c를 참조하면, 전체 구조상에 산화막(9)을 증착한 후, 도프트 폴리실리콘층 게이트 패턴(4) 부분이 개방된 포토레지스트 패턴(10)을 형성한다. 포토레지스트 패턴(10)을 식각 마스크로 한 식각 공정으로 도프트 폴리실리콘층 게이트 패턴(4) 위의 산화막(9), 열산화막(6) 및 제 1 반사 방지막(5)을 순차적으로 제거하여 도프트 폴리실리콘층 게이트 패턴(4) 상부면을 노출시킨다.Referring to FIG. 1C, after the oxide film 9 is deposited on the entire structure, the photoresist pattern 10 having the doped polysilicon layer gate pattern 4 open is formed. In the etching process using the photoresist pattern 10 as an etching mask, the oxide film 9, the thermal oxide film 6, and the first antireflection film 5 on the doped polysilicon layer gate pattern 4 are sequentially removed and doped. The upper surface of the polysilicon layer gate pattern 4 is exposed.
상기에서, 산화막(9)은 1000 내지 2000Å의 두께로 형성한다. 포토레지스트 패턴(10)은 네가티브 포토레지스트를 도포한 후, 게이트 마스크를 사용한 노광 및 현상 공정으로 형성된다.In the above, the oxide film 9 is formed to a thickness of 1000 to 2000 kPa. The photoresist pattern 10 is formed by an exposure and development process using a gate mask after applying the negative photoresist.
도 1d를 참조하면, 포토레지스트 패턴(10)을 제거하고, 세정 공정을 진행한 후, 전체구조상에 확산 방지막(11), 텅스텐층(12) 및 제 2 반사 방지막(13)을 순차적으로 형성하고, 게이트 마스크를 사용하여 노광 및 배선 공정을 거쳐 도프트 폴리실리콘층 게이트 패턴(4)상에 확산 방지막(11) 및 텅스텐층(12)이 적층되도록 하고, 이로 인하여 도프트 폴리실리콘층 게이트 패턴(4), 확산 방지막(11) 및 텅스텐층(12)이 적층된 게이트 전극(100)이 완성된다.Referring to FIG. 1D, after the photoresist pattern 10 is removed and the cleaning process is performed, the diffusion barrier 11, the tungsten layer 12, and the second antireflection layer 13 are sequentially formed on the entire structure. The diffusion barrier layer 11 and the tungsten layer 12 are stacked on the doped polysilicon layer gate pattern 4 through an exposure and wiring process using a gate mask, thereby forming a doped polysilicon layer gate pattern ( 4), the gate electrode 100 in which the diffusion barrier 11 and the tungsten layer 12 are stacked is completed.
상기에서, 세정 공정은 BOE 용액이나 HF 용액을 이용하여 도프트 폴리실리콘층 게이트 패턴(4)위의 자연 산화막을 제거한다. 확산 방지막(11)은 텅스텐나이트라이드(WNx)를 50 내지 100Å의 두께로 증착하여 형성된다. 텅스텐층(12)은 500 내지 1000Å의 두께로 형성된다. 제 1 반사 방지막(5)은 질화물을 300 내지 600Å의 두께로 증착하여 형성한다.In the above, the cleaning process removes the native oxide film on the doped polysilicon layer gate pattern 4 using a BOE solution or an HF solution. The diffusion barrier 11 is formed by depositing tungsten nitride (WNx) to a thickness of 50 to 100 kPa. The tungsten layer 12 is formed to a thickness of 500 to 1000 mm 3. The first anti-reflection film 5 is formed by depositing nitride to a thickness of 300 to 600 kPa.
상술한 바와 같이, 본 발명은 게이트에서 비저항이 낮은 메탈 게이트 적용으로 시정수 지연 시간을 감소시킬 수 있고, 게이트와 드레인간의 오버랩 캐패시턴스를 감소시키고, GOI 특성 향상을 위해 게이트 가장자리 부분에서 게이트 산화를 강화시킬 수 있어, 소자의 성능을 향상시킬 수 있다.As described above, the present invention can reduce the time constant delay time by applying a low-resistance metal gate at the gate, reduce the overlap capacitance between the gate and the drain, and enhance the gate oxidation at the gate edge to improve GOI characteristics. The performance of the device can be improved.
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990023929A KR100312382B1 (en) | 1999-06-24 | 1999-06-24 | Method of manufacturing a transistor in a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990023929A KR100312382B1 (en) | 1999-06-24 | 1999-06-24 | Method of manufacturing a transistor in a semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010003576A KR20010003576A (en) | 2001-01-15 |
| KR100312382B1 true KR100312382B1 (en) | 2001-11-03 |
Family
ID=19594872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990023929A KR100312382B1 (en) | 1999-06-24 | 1999-06-24 | Method of manufacturing a transistor in a semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100312382B1 (en) |
-
1999
- 1999-06-24 KR KR1019990023929A patent/KR100312382B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010003576A (en) | 2001-01-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111370306B (en) | Manufacturing method of transistor and full-surrounding grid electrode device structure | |
| KR20080103727A (en) | Method for manufacturing semiconductor memory device | |
| KR100312382B1 (en) | Method of manufacturing a transistor in a semiconductor device | |
| KR100535633B1 (en) | Semiconductor device having silicide layer for interconnecting gate and drain and method for forming the same | |
| KR100223736B1 (en) | Method of manufacturing semiconductor device | |
| KR100258347B1 (en) | Manufacture method of semiconductor apparatus | |
| KR100451042B1 (en) | Method for forming contact of semiconductor device to eliminate leakage current of contact | |
| KR100280537B1 (en) | Semiconductor device manufacturing method | |
| KR100191710B1 (en) | Metal wiring method of semiconductor device | |
| KR100633687B1 (en) | Method for Forming Salicide in Semiconductor Device | |
| KR100992631B1 (en) | Method of manufacturing semiconductor Device | |
| KR100851917B1 (en) | Method for fabricating silicon-oxide-nitride-oxide-silicon device | |
| KR100342394B1 (en) | manufacturing method of semiconductor devices | |
| KR20050023650A (en) | Method for fabricating semiconductor device having salicide | |
| KR100627570B1 (en) | Method for manufacturing the semicondutor device | |
| KR20020002644A (en) | Method for forming semiconductor device capable of preventing damage of interlayer insulating layer during additional ion implantation process for stbilizing bit line contact | |
| KR100265850B1 (en) | Method for forming metal interconnection in semiconductor device | |
| KR100433491B1 (en) | Method of manufacturing semiconductor device | |
| KR100660331B1 (en) | Method for fabricating semiconductor device | |
| KR20000004231A (en) | Method for forming a contact hole of semiconductor device | |
| JPH02143461A (en) | Semiconductor device and its manufacture | |
| KR100905182B1 (en) | Method for manufacturing semiconductor device | |
| KR100618692B1 (en) | Method for forming gate oxide | |
| KR100455444B1 (en) | Method of manufacturing a semiconductor device | |
| KR20050012947A (en) | Method for forming silicide of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20100920 Year of fee payment: 10 |
|
| LAPS | Lapse due to unpaid annual fee |