KR100307290B1 - Method for fabricating dram cell - Google Patents

Abstract

PURPOSE: A method for fabricating a DRAM cell is provided to prevent the generation of hot electron and a punch through phenomenon by forming a buried sidewall oxide layer. CONSTITUTION: A multitude of grooves are formed on a semiconductor substrate by etching a field oxide layer formed on the semiconductor substrate. A gate electrode is formed on a projection portion between the grooves. The third oxide layer and the low density dopant layer are formed on a whole surface of the semiconductor substrate. The first sidewall oxide layer and the second sidewall oxide layer are formed by etching the third oxide layer. A high density dopant layer is formed thereon by performing an annealing process. A capacitor including the first node polysilicon layer, a dielectric layer, and the second node polysilicon layer are formed on the groove of a source formation region. The third node polysilicon layer(27-4) is formed within a groove of a drain formation portion. The fourth oxide layer(28-1) and a BPSG(28-2) are deposited on the second node polysilicon layer(27-3). A DRAM cell(20) is formed by contacting a metal layer(29) with the third node polysilicon layer(27-4).

Description

Manufacturing method of DRAM cell.

1 is a cross-sectional view of a conventional DRAM cell.

2 is a diagram showing the manufacturing steps of the DRAM cell according to the present invention.

* Explanation of symbols for main parts of the drawings

10,20: DRAM cell 11,21: semiconductor substrate

12,22: field oxide film 13,23: gate electrode

13-1,23-1: First oxide film 13-2,23-2: Second oxide film

14: side oxide film 15,25: low concentration impurity layer

16,26: high concentration impurity layer 17-1,27-1: polysilicon layer for the first node

17-2, 27-2: dielectric film 17-3, 27-3: polysilicon layer for second node

18-1,28-1: 4th oxide film 18-2,28-2: BPSG

19,29 metal layer 27-4: polysilicon layer for third node

21-1: uneven groove 21-2: protrusion

24; Third Oxide Film 24-1: First Side Oxide Film

24-2: second side oxide film A, A ': source formation site

B, B ′: Drain formation site C ′: Gate formation site

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a DRAM cell, which is a semiconductor memory device. In particular, the present invention relates to a semiconductor substrate for preventing hot electron generation and punch through phenomenon due to the miniaturization of a DRAM cell structure. The present invention relates to a method for manufacturing a DRAM cell which forms a buried side wall by etching.

In a semiconductor memory device, a DRAM cell composed of one transistor and one capacitor has to have high density of devices as the memory capacity is increased, and thus the area of the capacitor and transistor elements on the semiconductor substrate should be minimized. do.

At this time, in the transistor region of the semiconductor substrate, in the source region and the drain region, due to the miniaturization of the element, a punch draw phenomenon generated as the channel width between them is narrowed and a hot electron generated by the high electric field generated in the drain region In order to prevent the phenomenon, a DRAM cell was generally manufactured by forming a light doped drain (LDD) region.

FIG. 1 is a diagram illustrating a cross-sectional structure of a conventional DRAM cell, which will be described in brief with reference to the accompanying drawings.

In order to manufacture the conventional DRAM cell 10, first, the field oxide film 12 is formed on the semiconductor substrate 11 through a selective oxidation process, and then the first oxide film, the polysilicon for the gate, and the second oxide film are formed. The gate electrode 13 is formed by a photolithography process.

Then, using the second oxide film 13-2 formed on the gate insulated from the substrate by the first oxide film 13-1 as a mask, ion-implanted low concentration impurities of the opposite conductivity type to the substrate are implanted.

Subsequently, a third oxide film is formed on the entire surface of the semiconductor substrate 11, and side source oxide films 14 are formed on both sides of the gate electrode 13 by an etch back process, and a source forming portion A and a drain are formed by an annealing process. The low concentration impurity layer 15 of the site B is formed.

Thereafter, a high concentration impurity of opposite conductivity type to the substrate is ion-implanted onto the semiconductor substrate 11, and a high concentration impurity layer 16 is formed at the bottom of the low impurity impurity layer 15 by an annealing process. In A), a capacitor composed of the first node polysilicon layer 17-1, the dielectric film 17-2, and the second node polysilicon layer 17-3 is formed.

Subsequently, an interlayer insulating film in which a fourth oxide film 18-1 and a BPSG (Borophospher Silicate Glass) 18-2 are sequentially deposited is formed on the upper surface of the second node polysilicon layer 17-3 of the capacitor. The DRAM layer by the LDD process was fabricated by forming a metal layer 19, which is a data line, on the entire surface of the semiconductor substrate so as to be in contact with the impurity layer of the drain forming portion B.

However, in the DRAM cell which prevents the hot electron and punch draw effect by the LDD process, when the device capacity becomes more fine while the storage capacity is gradually increased to 4 megabytes and 16 megabytes or 256 megabytes, the source portion and the drain portion Punch-draw phenomenon that occurs deep inside the semiconductor substrate under the channel formed between them and the hot electron generated by the high electric field generated in the drain portion can not prevent adverse effects on the operation of the device. It was.

In order to solve this problem, the present invention provides a method for forming a plurality of grooves by etching a portion of a field oxide layer by a trench process on a substrate on which a field oxide layer is formed by a selective oxidation process. And forming the gate polysilicon for the gate and the second oxide film in sequence, and then forming a gate electrode on the surface of the protrusion between the uneven grooves by a photolithography process, and forming the gate electrode on the upper surface of the gate electrode insulated by the substrate and the first oxide film. Applying an oxide film as a mask to ion implant a low concentration impurity into both substrate surface portions of the gate forming portion from the bottom portion of the uneven groove formed on the substrate and the protrusion between the uneven grooves and the third oxide film on the entire surface of the substrate And forming a first oxide film on both sides of the gate electrode by etching back the third oxide film and a second side embedded in both sides of the uneven groove. Forming a surface oxide film, applying a second oxide film on the upper surface of the gate electrode as a mask, and forming a boundary surface between both edge portions of the low concentration impurity layer formed on the surface of the protrusion with the first side oxide film as a boundary surface, and the buried second side oxide film Into the bottom surface of the uneven groove, ion-implanted high-concentration impurities of the opposite type to the substrate, and a capacitor comprising a polysilicon layer for the first node, a fluid film, and a polysilicon layer for the second node in the uneven groove of the source forming portion. And a method of manufacturing a DRAM cell comprising a step of forming a polysilicon layer for a third node in an uneven groove of a drain forming portion.

2 is a view illustrating a manufacturing step of the DRAM cell according to the present invention. Referring to the drawings, the manufacturing step of the DRAM cell according to the present invention will be described below.

In order to manufacture the DRAM cell 20 according to the present invention, first, a portion of the field oxide film is formed by a trench process on the semiconductor substrate 21 on which the field oxide film 22 is formed by the selective oxidation process as shown in FIG. Etching to form a plurality of uneven groove (21-1).

After the first oxide film, the gate polysilicon, and the second oxide film are sequentially formed on the semiconductor substrate, the projections 21 between the uneven grooves 21-1 are formed in the photolithography process as shown in FIG. 2 (b). -2) A gate electrode 23 is formed on the surface.

Next, as shown in FIG. 2 (c), ion-implanted low-concentration impurities of a conductivity type opposite to the substrate are implanted onto the semiconductor substrate 21.

At this time, the bottom surface of the uneven groove 21-1 formed in the semiconductor substrate by applying the second oxide film 23-2 on the upper surface of the gate electrode 23 insulated from the substrate by the first oxide film as a mask, and the uneven groove Low concentration impurity impurities are implanted into both substrate surfaces of the gate forming portion C 'in the protrusion 21-2.

Thereafter, as shown in FIG. 2 (d), the low concentration impurity layer 25 is formed by an annealing process while the third oxide film 24 is formed on the entire surface of the semiconductor substrate 21.

Then, as shown in FIG. 2 (e), the third oxide film is etched back on the semiconductor substrate 21 to form the first side oxide film 24-1 and the uneven groove 21-1 on both sides of the gate electrode 23. The second side oxide film 24-2 embedded in both sides of the inside is formed, and ion-implanted high concentration impurities of the opposite type to the substrate are implanted on the semiconductor substrate.

That is, while applying the second oxide film 23-2 on the upper surface of the gate electrode 23 as a mask, the substrate of the protrusion 21-2 is formed on the boundary surface of the first side oxide film 24-1 formed on both sides of the gate electrode. High impurity impurities are implanted between both edges of the low concentration impurity layer 26 formed on the surface and the buried second side oxide film 24-2 formed on both sides of the inside of the uneven groove.

Subsequently, as shown in FIG. 2 (f), the high impurity impurity layer 26 is formed in the annealing process, and the first node is formed in the uneven groove 21-1 of the source forming portion A 'on the semiconductor substrate 21. A capacitor formed of the polysilicon layer 27-1, the dielectric film 27-2, and the polysilicon layer 27-3 for the second node is formed, and the third recess is formed in the uneven groove of the formation portion B '. The polysilicon layer 27-4 for nodes is formed.

Thereafter, as shown in FIG. 2 (g), the fourth oxide film 28-1 and the BPSG 28-2 are sequentially deposited on the upper surface of the second node polysilicon layer 27-3 of the capacitor to form an interlayer insulating film. The DRAM cell 20 is manufactured by forming a metal layer 29, which is a data line, on the entire surface of the semiconductor substrate so as to be in contact with the polysilicon layer 27-4 for the third node.

In the DRAM cell according to the present invention, a plurality of concave-convex grooves are formed between the field oxide films of the semiconductor substrate by a trench process, and a second side oxide film formed on both sides of the concave-convex grooves is formed to form a polysilicon for the first node of the capacitor. The depletion layer diffuses into the layer and the drain portion to prevent punch draw phenomenon occurring between the drain portion and the source portion, and to reduce the junction capacitor.

In addition, the metal layer, which is a data line, was formed in contact with the polysilicon layer for the third node of the drain portion to reduce the contact resistance and suppress the generation of hot electrons in the semiconductor substrate.

Claims (1)

A method for manufacturing a DRAM cell in a semiconductor substrate, comprising the steps of: 1) forming a plurality of grooves by etching a portion of the field oxide film by a trench process on a substrate where the field oxide film is formed by a selective oxidation process; Forming a first oxide film, a gate polysilicon, and a second oxide film on the substrate in turn, and then forming a gate electrode on the surface of the protrusion between the uneven grooves by a photolithography process; and 3) By applying a second oxide film on the upper surface of the gate electrode insulated from the substrate as a mask, and a low concentration impurity on both substrate surface portions of the gate forming portion at the bottom surface portion of the uneven groove formed in the substrate and the protrusion between the uneven grooves. Implanting ions, 4) forming a third oxide film on the entire surface of the substrate, and 5) etching back the third oxide film on both sides of the gate electrode. Forming a side oxide film and second side oxide films buried on both side surfaces of the uneven groove; and 6) applying the second oxide film on the upper surface of the gate electrode as a mask, the surface of the protruding portion with the first side oxide film as an interface. On both edges of the low concentration impurity layer formed on the bottom surface and the buried second side oxide film, the ion implanted high conductivity impurity of the opposite type to the substrate is implanted into the bottom surface of the uneven groove, and into the uneven groove of the source forming portion. Forming a capacitor comprising a polysilicon layer for the first node, a fluid film, and a polysilicon layer for the second node; and 7) forming a polysilicon layer for the third node in the uneven groove of the dren-in forming region. Method for manufacturing a DRAM cell comprising a.