KR100304551B1 - Method for manufacturing thin film transistor - Google Patents
Method for manufacturing thin film transistor Download PDFInfo
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- KR100304551B1 KR100304551B1 KR1019940024033A KR19940024033A KR100304551B1 KR 100304551 B1 KR100304551 B1 KR 100304551B1 KR 1019940024033 A KR1019940024033 A KR 1019940024033A KR 19940024033 A KR19940024033 A KR 19940024033A KR 100304551 B1 KR100304551 B1 KR 100304551B1
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- forming
- active layer
- gate electrode
- depositing
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 title claims abstract description 13
- 239000010409 thin film Substances 0.000 title claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 238000000151 deposition Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 9
- 238000000059 patterning Methods 0.000 claims abstract description 8
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052804 chromium Inorganic materials 0.000 claims abstract description 4
- 239000011651 chromium Substances 0.000 claims abstract description 4
- 239000010408 film Substances 0.000 claims description 27
- 239000010410 layer Substances 0.000 claims description 20
- 239000011229 interlayer Substances 0.000 claims description 7
- 229910021332 silicide Inorganic materials 0.000 claims description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 4
- 239000007769 metal material Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 229910021357 chromium silicide Inorganic materials 0.000 abstract description 7
- 238000000137 annealing Methods 0.000 abstract description 6
- 239000002019 doping agent Substances 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 1
- 238000001259 photo etching Methods 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 description 7
- 239000011521 glass Substances 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 238000005984 hydrogenation reaction Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 210000004556 brain Anatomy 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000006356 dehydrogenation reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
Abstract
Description
제1도는 종래의 기술에 의한 박막트랜지스터의 제조방법을 도시한 단면도.1 is a cross-sectional view showing a method of manufacturing a thin film transistor according to the prior art.
제2도는 본 발명에 의한 박막트랜지스터의 제조방법을 도시한 단면도.2 is a cross-sectional view showing a method of manufacturing a thin film transistor according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 버퍼 산화막 20 : 활성층10: buffer oxide film 20: active layer
30 : 게이트 절연막 40' : 게이트 전극30: gate insulating film 40 ': gate electrode
70 : 층간절연막 90 : 화소전극70 interlayer insulating film 90 pixel electrode
100 : 기판 110 : 소스/드레인 전극100: substrate 110: source / drain electrode
본 발명은 박막트랜지스터 제조방법에 관한 것으로, 특히 다결정실리콘을 이용하여 활성층을 형성하기 위한 박막트랜지스터의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a thin film transistor, and more particularly, to a method for manufacturing a thin film transistor for forming an active layer using polycrystalline silicon.
일반적으로 다결정실리콘을 이용한 박막트랜지스터의 제조방법은 크게 두 가지로 분류되는데, 그 하나는 유리기판 위에 비정질실리콘을 증착시킨 후 레이저를 이용하여 상기 비정질실리콘을 어닐링(annealing)함으로써 다결정화시키는 것으로, 이 방법의 경우 고온기술과 저온기술의 온도기준점이 600℃∼650인데 비해 통상 사용되는 유리기판의 전이온도가 600℃이므로 600℃ 이상의 고온에서 다결정실리콘을 얻기위한 공정을 수행하게 되면 유리기판 자체가 구부러지거나 늘어나게 되어 유리기판 위에 제조되는 소자의 신뢰성을 보장할 수 없게 된다.Generally, a method of manufacturing a thin film transistor using polysilicon is classified into two types, one of which is to deposit polysilicon on a glass substrate and polycrystallize by annealing the amorphous silicon using a laser. In the case of the high temperature technology and the low temperature technology, the temperature reference point is 600 ℃ ~ 650, but the transition temperature of the commonly used glass substrate is 600 ℃, so when the process of obtaining polycrystalline silicon is performed at a high temperature of 600 ℃ or higher, the glass substrate itself is bent. This increases the reliability of the device manufactured on the glass substrate.
그리고 다결정실리콘을 이용한 박막트랜지스터의 다른 제조방법은, 600℃ 이상의 고온을 견딜수 있는 석영기판에 비정질실리콘을 증착시킨 후 고온으로 어닐링시키거나 LPCVD(Low Pressure Chemical Vapor Deposition) 처리하여 직접 다결정실리콘을 얻는 방법으로서 제1도를 참조하여 이를 좀 더 구체적으로 설명하면 다음과 같다.Another method of manufacturing a thin film transistor using polycrystalline silicon is to obtain amorphous polysilicon directly by depositing amorphous silicon on a quartz substrate that can withstand high temperatures of 600 ° C. or higher, or by annealing at a high temperature or by LPCVD (Low Pressure Chemical Vapor Deposition). As more specifically described with reference to Figure 1 as follows.
먼저 제1(a)도에서는 석영 기판(100)에 불순물의 확산을 방지하기 위한 소정의 두께로 버퍼 산화막(10)을 형성하고, 상기 버퍼산화막(10) 위에 다결정실리콘을 lPCVD를 이용하여 SiH4나 Si2H6를 반응가스로서 600℃이상에서 반응증착시키거나, 상기 lPCVD를 이용하여 비정질실리콘을 증착시킨 후 가열로(furnace)에서 어닐링하여 SPC(Solid Phase Crystallization)하여 다결정실리콘층을 형성한 후 상기 다결정실리콘을 패터닝하여 활성층(20)을 형성한다.First claim 1 (a) even in the SiH 4 using lPCVD polysilicon on a quartz substrate to form a buffer oxide film 10 to a predetermined thickness to prevent diffusion of impurities to 100, and the buffer oxide film 10 Or Si 2 H 6 as a reaction gas, the reaction vapor deposition at 600 ℃ or above, or by depositing amorphous silicon using the lPCVD and then annealed in a furnace (furnace) to form a polycrystalline silicon layer by SPC (Solid Phase Crystallization) Thereafter, the polysilicon is patterned to form an active layer 20.
제1(b)도에서는 상기 결과물 전면에 CVD 산화막이나 열산화막 등으로 게이트 절연막(30)을 형성하고, 이어서 상기 증착되어 있는 구조물들의 막질을 향상시키기 위해 질소(N2) 분위기에서 900℃ 정도의 온도로 어닐링을 실시한다.In FIG. 1 (b), the gate insulating film 30 is formed of a CVD oxide film or a thermal oxide film on the entire surface of the resultant material, and then, in order to improve the film quality of the deposited structures, about 900 ° C. in a nitrogen (N 2 ) atmosphere. Anneal to temperature.
제1(c)도 및 (d)도에서는 상기 게이트 절연막(30) 위에 도전물질로서 예를들면, n+로 도핑된 다결정실리콘을 소정의 두께로 스퍼터링(sputtering)한 후 패터닝하여 게이트 전극(40')을 형성한다.1 (c) and (d), for example, n + doped polysilicon is sputtered to a predetermined thickness as a conductive material on the gate insulating film 30 and then patterned to form the gate electrode 40 '. ).
그리고 LDD(Lightly Doped Brain)형 n채널의 경우, 제1(e)도 내지 (g)도에서 이온 주입기를 이용하여 상기 활성층(20) 상에 소스/드레인영역을 형성하며, n채널이나 p채널의 경우 채널별로 각각 도핑가스와 도우즈량을 다르게 한 후 도펀트를 활성화하기 위해 질소분위기에서 어닐링을 실시한다.In the case of LDD (Lightly Doped Brain) type n channel, source / drain regions are formed on the active layer 20 by using an ion implanter in FIGS. 1 (e) to (g) and n or p channels. In the case of different doping gas and dose amount for each channel after annealing is carried out in a nitrogen atmosphere to activate the dopant.
(h)도 및 (i)도에서 상기 어닐링 실시후 결과물 전면에 층간 절연막(70)을 형성하고, 상기 층간절연막(70)을 선택적으로 식각하여 상기 소스/드레인 영역을 노출시킴으로서 콘택홀을 형성한다.In (h) and (i), after the annealing is performed, an interlayer insulating film 70 is formed on the entire surface of the resultant, and the interlayer insulating film 70 is selectively etched to expose the source / drain regions to form contact holes. .
이어서 (j)도에서는 상기 콘택홀이 형성된 콘택 영역의 저항을 낮추기 위해 이온(80) 주입을 실시한 후 도펀트를 활성화하기 위해 어닐링을 실시한 후, 수소를 첨가시키기 위해 플라즈마 상태의 채임버(chamber) 내에서 수소 라디칼(radical)이 채널부분으로 흡입되도록 한다.Subsequently, in (j), after the ion 80 is implanted to lower the resistance of the contact region in which the contact hole is formed, the annealing is performed to activate the dopant, and then in the chamber of the plasma state to add hydrogen. The hydrogen radicals are sucked into the channel portion at.
(k)도 및 (l)도에서는 상기(j)도의 공정 후 결과물 전면에 투명도전물질로서 예를들면 ITO(Indium Tix Oxide)를 소정의 두께로 증착시킨 후 패터닝하여 화소전극(90)을 형성하고, (m)도에서는 상기 화소전극(90) 형성 후 결과물 전면에 금속물질을 증착시켜 상기 콘택홀을 통하여 소스/드레인 영역과 연결되도록 하며, 이어서 상기 금속물질을 패터닝하여 소스/드레인전극(110)을 형성한다.In (k) and (l), for example, ITO (Indium Tix Oxide) is deposited to a predetermined thickness as a transparent conductive material on the entire surface of the resultant after the process of (j) to form a pixel electrode 90 by patterning. In (m), after forming the pixel electrode 90, a metal material is deposited on the entire surface of the resultant to be connected to the source / drain region through the contact hole, and then the metal material is patterned to form the source / drain electrode 110. ).
그러나 종래와 같이 게이트 전극 형성시 n+ 도핑된 다결정실리콘을 사용하는 방법은, 상기 활성층 내에 함유되어 있는 수소가 게이트 전극을 형성하는 과정에서 빠져나오는 탈수소화현상이 발생하여 소자의 전류/전압(I/V) 특성을 저하시킴으로써 이를 사용하여 액정표시소자를 제조하게 되면 계조특성이 저하되는 문제점이 있으며, 이를 해결하기 위해서는 반드시 수소첨가공정(hydrogenation)이 수행되야 하므로 제조시간이 길어지고 공정이 복잡하며, 제조가가 상승하는 문제점이 있다.However, in the conventional method of using n + doped polysilicon when forming a gate electrode, dehydrogenation occurs in a process in which hydrogen contained in the active layer forms a gate electrode, and thus the current / voltage (I / V) When the liquid crystal display device is manufactured by lowering the characteristics, there is a problem in that the gray scale characteristic is lowered. In order to solve this problem, the hydrogenation process must be performed, so that the manufacturing time is long and the process is complicated. There is a problem that the manufacturing price rises.
따라서 본 발명의 목적은 상기와 같은 문제점을 해결하기 위하여 n+ 도핑된 다결정실리콘 대신 실리사이드를 사용하여 게이트 전극을 형성함으로써 제조공정을 단순화할 수 있는 박막트랜지스터 제조방법을 제공하는 것이다.Accordingly, an object of the present invention is to provide a thin film transistor manufacturing method that can simplify the manufacturing process by forming a gate electrode using silicide instead of n + doped polycrystalline silicon to solve the above problems.
상기 목적을 달성하기 위한 본 발명의 박막트랜지스터 제조방법은, 기판위에 버퍼산화막을 형성하는 공정과, 상기 버퍼 산화막위에 다결정실리콘을 증착시킨 후 패터닝하여 활성층을 형성하는 공정과, 상기 활성층이 형성된 결과를 전면에 절연물질을 증착시켜 게이트 절연막을 형성하는 공정과, 상기 활성층 위의 게이트 절연막 상에 실리사이드로 게이트 전극을 형성하는 공정과, 상기 게이트 전극을 마스크로 상기 활성층상에 불순물을 주입하여 소스/드레인 영역을 형성하는 공정과, 상기 소스/드레인 영역 형성 후 절연물질을 증착시켜 층간절연막을 형성하는 공정과, 상기 층간절연막을 선택적으로 식각하여 콘택홀을 형성하는 공정과, 상기 콘택홀 형성 후 결과물 전면에 투명도전물질을 증착시킨 후 패터닝하여 화소전극을 형성하는 공정과, 금속물질로 상기 콘택홀을 통해 소스/드레인 영역과 접촉하도록 소스/드레인 전극을 형성하는 공정을 포함하여 구성된 것을 특징으로 한다.The thin film transistor manufacturing method of the present invention for achieving the above object is a step of forming a buffer oxide film on the substrate, and a process of forming an active layer by depositing and patterning polycrystalline silicon on the buffer oxide film, and the result of forming the active layer Forming a gate insulating film by depositing an insulating material over the entire surface, forming a gate electrode with silicide on the gate insulating film on the active layer, and implanting impurities into the active layer using the gate electrode as a mask to source / drain Forming a region, forming an interlayer insulating film by depositing an insulating material after forming the source / drain regions, forming a contact hole by selectively etching the interlayer insulating film, and forming a contact hole after forming the contact hole Forming a pixel electrode by depositing a transparent conductive material on the substrate and patterning the same; And forming a source / drain electrode to be in contact with the source / drain region through the contact hole.
이하 첨부도면을 참조하여 본 발명을 좀 더 상세하게 설명하고자 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
본 발명의 박막트랜지스터 제조방법은, 먼저 제1(a)도 및 (b)도와 동일하게 기판(100)에 불순물의 확산을 방지하기 위한 소정의 두께로 버퍼 산화막(10)과, 활성층(20)을 형성한 후, 제2(a)도 및 (b)도에 도시한 바와 같이 상기 게이트 절연막(30) 위에 먼저 실리사이드로 완전히 변화될 수 있을 만큼의 비정질실리콘을 500Å 정도의 두께로 증착시킨 후 다시 상기 비정질실리콘 위에 크롬(C)을 소정의 두께로 증착시킨다.According to the method of manufacturing the thin film transistor of the present invention, first, the buffer oxide film 10 and the active layer 20 are formed to have a predetermined thickness to prevent diffusion of impurities in the substrate 100 in the same manner as in FIGS. 1 (a) and (b). As shown in FIG. 2 (a) and (b), after depositing amorphous silicon having a thickness of about 500 kPa on the gate insulating film 30, the silicon can be completely changed into silicide. Chromium (C) is deposited on the amorphous silicon to a predetermined thickness.
이어서 상기 비정질실리콘과 크롬을 250℃ 이하에서 어닐링하여 크롬실리사이드층(40″)을 형성하고, 이어서 상기 크롬 실리사이드층(40″) 상부에 포토레지스터를 도포, 노광 및 현상하여 사진식각마스크를 형성한 후 이를 적용하여 상기 크롬 실리사이드층을 패터닝함으로서 게이트 전극(40')을 형성한 다음 상기 사진식각마스크를 제거한다.Subsequently, the amorphous silicon and chromium are annealed at 250 ° C. or lower to form a chromium silicide layer 40 ″, and then a photoresist is applied, exposed and developed on the chromium silicide layer 40 ″ to form a photolithography mask. After that, the gate electrode 40 'is formed by patterning the chromium silicide layer and then the photolithography mask is removed.
그리고 상기 게이트 전극(40') 형성 이후 게이트 절연막, 게이트 전극, 소스/드레인 영역, 화소전극 및 소스/드레인 전극을 형성하는 공정은 종래와 동일하므로 제1(b)도로부터 (m)도를 참조하며, 단, 수소첨가를 위한 공정은 필요하지 않다.After the gate electrode 40 'is formed, a process of forming a gate insulating film, a gate electrode, a source / drain region, a pixel electrode, and a source / drain electrode is the same as in the prior art, and thus, see FIGS. 1 (b) to (m). However, a process for hydrogenation is not necessary.
이상에서와 같이 본 발명에 의하면 크롬 실리사이드로 게이트 전극을 형성함으로서 이를 제조공정을 단순화할 수 있으며, 이에따라 제조가를 감소시킬 수 있을뿐만 아니라 상기 게이트 전극으로 그 하부를 보호함으로써 채널영역의 열화를 방지할 수 있는 효과가 있다.As described above, according to the present invention, the gate electrode may be formed of chromium silicide, thereby simplifying the manufacturing process, thereby reducing the manufacturing cost and protecting the lower portion of the gate electrode, thereby preventing deterioration of the channel region. It can work.
Claims (3)
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| KR1019940024033A KR100304551B1 (en) | 1994-09-23 | 1994-09-23 | Method for manufacturing thin film transistor |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62229873A (en) * | 1986-03-29 | 1987-10-08 | Hitachi Ltd | Manufacture of thin film semiconductor device |
| US4954855A (en) * | 1985-04-08 | 1990-09-04 | Hitachi, Ltd. | Thin film transistor formed on insulating substrate |
| JPH05218422A (en) * | 1992-02-04 | 1993-08-27 | Seiko Epson Corp | Thin film transistor and manufacture thereof |
| JPH05235353A (en) * | 1992-02-21 | 1993-09-10 | Seiko Epson Corp | Active matrix substrate and manufacture thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4954855A (en) * | 1985-04-08 | 1990-09-04 | Hitachi, Ltd. | Thin film transistor formed on insulating substrate |
| JPS62229873A (en) * | 1986-03-29 | 1987-10-08 | Hitachi Ltd | Manufacture of thin film semiconductor device |
| JPH05218422A (en) * | 1992-02-04 | 1993-08-27 | Seiko Epson Corp | Thin film transistor and manufacture thereof |
| JPH05235353A (en) * | 1992-02-21 | 1993-09-10 | Seiko Epson Corp | Active matrix substrate and manufacture thereof |
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